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SN74LVC2G241 DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES210B - APRIL 1999 - REVISED FEBRUARY 2000
D D D D D D
EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25C Ioff Supports Partial-Power-Down Mode Operation Supports 5-V VCC Operation Package Options Include Plastic Thin Shrink Small-Outline (DCT, DCU) Packages
DCT OR DCU PACKAGE (TOP VIEW)
1OE 1A 2Y GND
1 2 3 4
8 7 6 5
VCC 2OE 1Y 2A
description
This dual buffer/line driver is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G241 is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking or the current-sourcing capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74LVC2G241 is characterized for operation from -40C to 85C.
FUNCTION TABLES INPUTS 1OE L L H 1A H L X OUTPUT 1Y H L Z
INPUTS 2OE H H L 2A H L X
OUTPUT 2Y H L Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright (c) 2000, Texas Instruments Incorporated
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PRODUCT PREVIEW
The SN74LVC2G241 is organized as two 1-bit line drivers with separate output-enable (1OE, 2OE) inputs. When 1OE is low or 2OE is high, the device passes data from the A inputs to the Y outputs. When 1OE is high or 2OE is low, the outputs are in the high-impedance state.
SN74LVC2G241 DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES210B - APRIL 1999 - REVISED FEBRUARY 2000
logic symbol
1OE 1 EN 6
1A
2
1Y
2OE
7
EN 3
2A
5
2Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE 1 2 6
PRODUCT PREVIEW
1A
1Y
2OE 2A
7 5 3
2Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DCT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296C/W DCU package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51.
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SN74LVC2G241 DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES210B - APRIL 1999 - REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
MIN VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 VCC = 1.65 V VCC = 2.3 V IOH High-level output current VCC = 3 V VCC = 4.5 V VCC = 1.65 V VCC = 2.3 V IOL Low-level output current VCC = 3 V VCC = 4.5 V VCC = 1.8 V 0.15 V, 2.5 V 0.2 V t/v Input transition rise or fall rate VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V 1.65 1.5 0.65 x VCC 1.7 2 0.7 x VCC 0.35 x VCC 0.7 0.8 0.3 x VCC 5.5 VCC -4 -8 -24 -32 4 8 16 24 32 20 10 5 ns/V mA -16 V V V V MAX 5.5 UNIT V
VIH
High-level High level input voltage
VIL
Low-level Low level input voltage
VI VO
Input voltage Output voltage
TA Operating free-air temperature -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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PRODUCT PREVIEW
mA
SN74LVC2G241 DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES210B - APRIL 1999 - REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = -100 mA IOH = -4 mA VOH IOH = -8 mA IOH = -16 mA IOH = -24 mA IOH = -32 mA IOL = 100 mA IOL = 4 mA IOL = 8 mA IOL = 16 mA IOL = 24 mA A inputs OE/OE inputs IOL = 32 mA VI = 5.5 V or GND VI = 5.5 V or GND VI or VO= 5.5 V VO = 0 to 5.5 V VI = 5.5 V or GND VI = 3.6 V to 5.5 V One input at VCC - 0.6 V, VI = VCC or GND TEST CONDITIONS VCC 1.65 V to 5.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V to 5.5 V 1.65 V 2.3 V 3V 4.5 V 0 to 5.5 V 0 to 5.5 V 0 3.6 V IO = 0 Other inputs at VCC or GND 5.5 55V 3 V to 5.5 V 3.3 V 3.3 V MIN VCC-0.1 1.2 1.9 2.4 2.3 3.8 0.1 0.45 0.3 0.4 0.55 0.55 5 5 10 10 10 10 500 V V TYP MAX UNIT
VOL
II
mA mA mA mA mA mA
pF pF
PRODUCT PREVIEW
Ioff IOZ ICC ICC Ci
Co VO = VCC or GND All typical values are at VCC = 3.3 V, TA = 25C. This applies in the disabled state only.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 4)
PARAMETER tpd ten tdis FROM (INPUT) A OE or OE OE or OE TO (OUTPUT) Y Y Y VCC = 1.8 V 0.15 V MIN MAX VCC = 2.5 V 0.2 V MIN MAX VCC = 3.3 V 0.3 V MIN MAX VCC = 5 V 0.5 V MIN MAX ns ns ns UNIT
operating characteristics, TA = 25C
PARAMETER Power dissipation ca acitance capacitance per buffer/driver Outputs enabled f = 10 MHz Outputs disabled pF TEST CONDITIONS VCC = 1.8 V TYP VCC = 2.5 V TYP VCC = 3.3 V TYP VCC = 5 V TYP UNIT
Cpd
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SN74LVC2G241 DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES210B - APRIL 1999 - REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 0.15 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 1 k 1 k S1 Open GND TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Control tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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PRODUCT PREVIEW
VCC
SN74LVC2G241 DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES210B - APRIL 1999 - REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu VCC VCC/2 0V th VCC VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Control tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
PRODUCT PREVIEW
Data Input
VCC
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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SN74LVC2G241 DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES210B - APRIL 1999 - REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V 0.3 V
500 S1 6V Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
From Output Under Test CL = 50 pF (see Note A)
LOAD CIRCUIT
tw 3V
Timing Input tsu Data Input 1.5 V
3V 1.5 V 0V th 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
Input
1.5 V
1.5 V 0V
VOLTAGE WAVEFORMS PULSE DURATION
3V Output Control tPZL 3V Output Waveform 1 S1 at 6 V (see Note B) tPZH VOH Output Waveform 2 S1 at GND (see Note B) 1.5 V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V VOL + 0.3 V tPHZ VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL
Input tPLH
1.5 V
1.5 V 0V tPHL
Output
1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
1.5 V VOL
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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PRODUCT PREVIEW
SN74LVC2G241 DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES210B - APRIL 1999 - REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION VCC = 5 V 0.5 V
500 S1 11 V Open GND 500
From Output Under Test CL = 50 pF (see Note A)
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 Open 11 V GND
LOAD CIRCUIT
Timing Input
VCC VCC/2 0V tsu th VCC VCC/2 VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 0V
tw VCC Input VCC/2 VCC/2 0V Data Input
PRODUCT PREVIEW
VOLTAGE WAVEFORMS PULSE DURATION
VCC Input tPLH Output tPHL VCC/2 VCC/2 VCC/2 VCC/2 0V tPHL VOH VCC/2 VOL tPLH VOH Output VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
Output Control tPZL
VCC VCC/2 VCC/2 0V tPLZ 5.5 V VCC/2 tPZH VOL + 0.3 V tPHZ VCC/2 VOH - 0.3 V VOH 0 V VOL
Output Waveform 1 S1 at 11 V (see Note B) Output Waveform 2 S1 at GND (see Note B)
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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