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| SN54LV126A, SN74LV126A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES131D - MARCH 1998 - REVISED MAY 2000 D D D D D D D D EPIC TM (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25C 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J) SN54LV126A . . . J OR W PACKAGE SN74LV126A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) 1OE 1A 1Y 2OE 2A 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4OE 4A 4Y 3OE 3A 3Y SN54LV126A . . . FK PACKAGE (TOP VIEW) 1Y NC 2OE NC 2A 1A 1OE NC VCC 4OE 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 4A NC 4Y NC 3OE description These quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation. The 'LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. NC - No internal connection To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. The SN54LV126A is characterized for operation over the full military temperature range of -55C to 125C. The SN74LV126A is characterized for operation from -40C to 85C. FUNCTION TABLE (each buffer) INPUTS OE H H L A H L X OUTPUT Y H L Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 Copyright (c) 2000, Texas Instruments Incorporated * DALLAS, TEXAS 75265 2Y GND NC 3Y 3A 1 SN54LV126A, SN74LV126A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES131D - MARCH 1998 - REVISED MAY 2000 logic symbol 1OE 1A 2OE 2A 3OE 3A 4OE 4A 1 2 4 5 10 9 13 12 11 8 6 EN 1 3 1Y 2Y 3Y 4Y This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. logic diagram (positive logic) 1OE 1A 1 2 3 3OE 1Y 3A 10 9 8 3Y 2OE 2A 4 5 6 4OE 2Y 4A 13 12 11 4Y Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LV126A, SN74LV126A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES131D - MARCH 1998 - REVISED MAY 2000 recommended operating conditions (see Note 4) SN54LV126A MIN VCC Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 High or low state 3-state VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 0 0 0 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC 5.5 -50 -2 -8 -16 50 2 8 16 200 100 0 0 0 0 0 MAX 5.5 SN74LV126A MIN 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC 5.5 -50 -2 -8 -16 50 2 8 16 200 100 ns/V mA A mA V V MAX 5.5 UNIT V VIH High-level High level input voltage VIL Low-level Low level input voltage VI VO Input voltage Output voltage V V A IOH High-level High level output current IOL Low-level Low level output current t/v Input transition rise or fall rate VCC = 4.5 V to 5.5 V 0 20 0 20 TA Operating free-air temperature -55 125 -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -50 A IOH = -2 mA IOH = -8 mA IOH = -16 mA IOL = 50 A IOL = 2 mA IOL = 8 mA IOL = 16 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 SN54LV126A VCC 2 V to 5.5 V 2.3 V 3V 4.5 V 2 V to 5.5 V 2.3 V 3V 4.5 V 0 V to 5.5 V 5.5 V 5.5 V 0V 3.3 V 1.6 MIN VCC-0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 1 5 20 5 1.6 TYP MAX SN74LV126A MIN VCC-0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 1 5 20 5 A A A A pF V TYP MAX UNIT VOH V VOL II IOZ ICC Ioff Ci PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54LV126A, SN74LV126A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES131D - MARCH 1998 - REVISED MAY 2000 switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER tpd ten tdis tpd ten tdis FROM (INPUT) A OE OE A OE OE TO (OUTPUT) Y Y Y Y Y Y CL = 50 pF F CL = 15 pF LOAD CAPACITANCE MIN TA = 25C TYP MAX 7.1* 7.4* 5.7* 9.2 9.5 8.1 13* 13* 14.7* 16.5 16.5 18.2 2 SN54LV126A MIN 1* 1* 1* 1 1 15 MAX 15.5* 15.5* 17* 18.5 18.5 20.5 SN74LV126A MIN 1 1 1 1 1 1 MAX 15.5 15.5 17 18.5 18.5 20.5 2 ns ns UNIT tsk(o) * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER tpd ten tdis tpd ten tdis FROM (INPUT) A OE OE A OE OE TO (OUTPUT) Y Y Y Y Y Y CL = 50 pF F CL = 15 pF LOAD CAPACITANCE TA = 25C MIN TYP MAX 5* 5.1* 4.4* 6.4 6.6 6.1 8* 8* 9.7* 11.5 11.5 13.2 1.5 SN54LV126A MIN 1* 1* 1* 1 1 1 MAX 9.5* 9.5* 11.5* 13 13 15 SN74LV126A MIN 1 1 1 1 1 1 MAX 9.5 9.5 11.5 13 13 15 1.5 ns ns UNIT tsk(o) * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tpd ten tdis tpd ten tdis FROM (INPUT) A OE OE A OE OE TO (OUTPUT) Y Y Y Y Y Y CL = 50 pF F CL = 15 pF LOAD CAPACITANCE MIN TA = 25C TYP MAX 3.5* 3.6* 3.3* 4.6 4.6 4.3 5.5* 5.1* 6.8* 7.5 7.1 8.8 1 SN54LV126A MIN 1* 1* 1* 1 1 1 MAX 6.5* 6* 8* 8.5 8 10 SN74LV126A MIN 1 1 1 1 1 1 MAX 6.5 6 8 8.5 8 10 1 ns ns UNIT tsk(o) * On products compliant to MIL-PRF-38535, this parameter is not production tested. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LV126A, SN74LV126A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES131D - MARCH 1998 - REVISED MAY 2000 noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25C (see Note 5) PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) VIL(D) Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage Low-level dynamic input voltage 2.31 0.97 SN74LV126A MIN TYP 0.3 -0.2 3.1 MAX 0.8 -0.8 UNIT V V V V V NOTE 5: Characteristics are for surface-mount packages only. operating characteristics, TA = 25C PARAMETER Cpd Power dissipation capacitance Outputs enabled TEST CONDITIONS CL = 50 pF pF, f = 10 MHz VCC 3.3 V 5V TYP 14.4 15.9 UNIT pF POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN54LV126A, SN74LV126A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES131D - MARCH 1998 - REVISED MAY 2000 PARAMETER MEASUREMENT INFORMATION RL = 1 k S1 VCC Open GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain S1 Open VCC GND VCC From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC Timing Input tw VCC Input 50% VCC 50% VCC 0V VOLTAGE WAVEFORMS PULSE DURATION VCC Input tPLH In-Phase Output tPHL Out-of-Phase Output 50% VCC 50% VCC 50% VCC 50% VCC tPHL VOH 50% VCC VOL tPLH VOH 50% VCC VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at VCC (see Note B) tPZH 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC tPZL tPLZ 50% VCC tPHZ VOH - 0.3 V VOH 0V 50% VCC 0V VCC VOL + 0.3 V VOL Data Input tsu 50% VCC 50% VCC 0V th VCC 50% VCC 0V Output Control 50% VCC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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