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SN54LVTH240, SN74LVTH240 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS679E - DECEMBER 1996 - REVISED APRIL 1999
D D D D D D D D D
description
These octal buffers and line drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When OE is low, the devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH240 is characterized for operation over the full military temperature range of -55C to 125C. The SN74LVTH240 is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
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2Y1 GND 2A1 1Y4 2A2
State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic (J) DIPs
SN54LVTH240 . . . J PACKAGE SN74LVTH240 . . . DB, DW, OR PW PACKAGE (TOP VIEW)
1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
SN54LVTH240 . . . FK PACKAGE (TOP VIEW)
2Y4 1A1 1OE VCC
1A2 2Y3 1A3 2Y2 1A4
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
2OE 1Y1 2A4 1Y2 2A3 1Y3
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SN54LVTH240, SN74LVTH240 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS679E - DECEMBER 1996 - REVISED APRIL 1999
FUNCTION TABLE (each buffer) INPUTS OE L L H A H L X OUTPUT Y L H Z
logic symbol
1OE 1 EN 18 16 14 12 2OE 19 EN 9 7 5 3
1A1 1A2 1A3 1A4
2 4 6 8
1Y1 1Y2 1Y3 1Y4
2A1 2A2 2A3 2A4
11 13 15 17
2Y1 2Y2 2Y3 2Y4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE 1 2OE 19
1A1
2
18
1Y1
2A1
11
9
2Y1
1A2
4
16
1Y2
2A2
13
7
2Y2
1A3
6
14
1Y3
2A3
15
5
2Y3
1A4
8
12
1Y4
2A4
17
3
2Y4
2
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* DALLAS, TEXAS 75265
SN54LVTH240, SN74LVTH240 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS679E - DECEMBER 1996 - REVISED APRIL 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Current into any output in the low state, IO: SN54LVTH240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTH240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVTH240 . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVTH240 . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVTH240 MIN VCC VIH VIL VI IOH IOL t/v t/VCC TA Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate Operating free-air temperature Outputs enabled 200 -55 125 2.7 2 0.8 5.5 -24 48 10 200 -40 85 MAX 3.6 SN74LVTH240 MIN 2.7 2 0.8 5.5 -32 64 10 MAX 3.6 UNIT V V V V mA mA ns/V s/V C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SN54LVTH240, SN74LVTH240 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS679E - DECEMBER 1996 - REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK TEST CONDITIONS VCC = 2.7 V, VCC = 2.7 V to 3.6 V, VCC = 2.7 V, VCC = 3 V VCC = 2 7 V 2.7 VOL VCC = 3 V II = -18 mA IOH = -100 A IOH = -8 mA IOH = -24 mA IOH = -32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 48 mA IOL = 64 mA VI = 5.5 V VI = VCC or GND VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V VO = 3 V VO = 0.5 V 5 -5 100 100 0.19 5 0.19 0.2 3 7 3 7 75 -75 MIN SN54LVTH240 TYP MAX -1.2 VCC-0.2 2.4 2 2 0.2 0.5 0.4 0.5 0.55 0.55 10 1 1 -5 75 -75 500 -750 5 -5 100 100 0.19 5 0.19 0.2 mA pF pF mA A 10 1 1 -5 100 A A 0.2 0.5 0.4 0.5 V VCC-0.2 2.4 MIN SN74LVTH240 TYP MAX -1.2 UNIT V
VOH
V
II
Control inputs Data inputs
VCC = 0 or 3.6 V, VCC = 3.6 V, VCC = 3 6 V 3.6 VCC = 0, VCC = 3 V
Ioff
II(hold)
Data inputs in uts VCC = 3.6 V,
IOZH IOZL IOZPU IOZPD
VCC = 3.6 V, VCC = 3.6 V,
A A A A
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high Outputs low Outputs disabled
ICC
ICC Ci Co
VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND VI = 3 V or 0 VO = 3 V or 0
On products compliant to MIL-PRF-38535, this parameter is not production tested. All typical values are at VCC = 3.3 V, TA = 25C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LVTH240, SN74LVTH240 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS679E - DECEMBER 1996 - REVISED APRIL 1999
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LVTH240 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V 0.3 V MIN tPLH tPHL tPZH tPZL tPHZ tPLZ A Y Y Y 0.9 1.2 1 1.2 1 1.1 MAX 4.3 4.7 5.7 5.5 5.1 5.4 VCC = 2.7 V MIN MAX 5.1 4.9 6.7 6.2 5.2 5.4 SN74LVTH240 VCC = 3.3 V 0.3 V MIN 1.1 1.3 1.1 1.4 2 1.8 TYP 2.2 2.6 2.6 2.7 2.9 3 MAX 3.8 4 4.6 4.4 4.4 4.3 VCC = 2.7 V MIN MAX 4.6 4.2 5.6 5 4.6 4.3 ns ns ns UNIT
OE OE
All typical values are at VCC = 3.3 V, TA = 25C.
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SN54LVTH240, SN74LVTH240 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS679E - DECEMBER 1996 - REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
2.7 V LOAD CIRCUIT tw 2.7 V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Output Control tPZL VOH Output 1.5 V tPHL Output 1.5 V 1.5 V VOL tPLH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 6 V (see Note B) tPZH 1.5 V 1.5 V 1.5 V 1.5 V 0V tPLZ 3V VOL + 0.3 V VOL tPHZ VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Data Input Timing Input 1.5 V 0V tsu 1.5 V th 2.7 V 1.5 V 0V
2.7 V Input tPLH 1.5 V 1.5 V 0V tPHL
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 2000, Texas Instruments Incorporated

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