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SN54ABT18646, SN74ABT18646 SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS131-AUGUST 1992-REVISED OCTOBER 1992
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Members of the Texas Instruments SCOPE TM Family of Testability Products Members of the Texas Instruments Widebus TM Family Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Include D-Type Flip-Flops and Control Circuitry to Provide Multiplexed Transmission of Stored and Real-Time Data Two Boundary-Scan Cells per I/O for Greater Flexibility State-of-the-Art EPIC-B TM BiCMOS Design Significantly Reduces Power Dissipation
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SCOPE TM Instruction Set - IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, and P1149.1A CLAMP and HIGHZ - Parallel Signature Analysis at Inputs With Masking Option - Pseudo-Random Pattern Generation From Outputs - Sample Inputs/Toggle Outputs - Binary Count From Outputs - Device Identification - Even-Parity Opcodes Packaged in 64-Pin Plastic Shrink Quad Flat Pack (PM) and 68-Pin Ceramic Quad Flat Pack (HV)
SN54ABT18646 . . . HV PACKAGE (TOP VIEW)
1A2 1A1 1OE GND 1SAB 1CLKAB TDO VCC NC TMS 1CLKBA 1SBA 1DIR GND 1B1 1B2 1B3
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
1A3 1A4 1A5 GND 1A6 1A7 1A8 1A9 NC VCC 2A1 2A2 2A3 GND 2A4 2A5 2A6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36
17 35 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
1B4 1B5 1B6 GND 1B7 1B8 1B9 VCC NC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7
2A7 2A8 2A9 GND 2OE 2SAB 2CLKAB TDI NC
VCC
NC - No internal connection
SCOPE, Widebus, and EPIC-B are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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TCK 2CLKBA 2SBA GND 2DIR 2B9 2B8
Copyright (c) 1992, Texas Instruments Incorporated
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PRODUCT PREVIEW
SN54ABT18646, SN74ABT18646 SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS131-AUGUST 1992-REVISED OCTOBER 1992
SN74ABT18646 . . . PM PACKAGE (TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1A3 1A4 1A5 GND 1A6 1A7 1A8 1A9 VCC 2A1 2A2 2A3 GND 2A4 2A5 2A6
1A2 1A1 1OE GND 1SAB 1CLKAB TDO V CC TMS 1CLKBA 1SBA 1DIR GND 1B1 1B2 1B3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1B4 1B5 1B6 GND 1B7 1B8 1B9 VCC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7
PRODUCT PREVIEW
description
The SN54ABT18646 and SN74ABT18646 scan test devices with 18-bit bus transceivers and registers are members of the Texas Instruments SCOPE TM testability IC family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed transmission of data directly from the input bus or from the internal registers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETM bus transceivers and registers. Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating both buses. Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB and SAB, respectively. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ABT18646.
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2A7 2A8 2A9 GND 2OE 2SAB 2CLKAB TDI VCC TCK 2CLKBA 2SBA GND 2DIR 2B9 2B8
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SN54ABT18646, SN74ABT18646 SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS131-AUGUST 1992-REVISED OCTOBER 1992
description (continued)
In the test mode, the normal operation of the SCOPE TM bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions such as parallel signature analysis on data inputs and pseudo-random pattern generation from data outputs. All testing and scan operations are synchronized to the TAP interface. Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. The SN54ABT18646 is characterized over the full military temperature range of - 55C to 125C. The SN74ABT18646 is characterized for operation from - 40C to 85C.
FUNCTION TABLE (normal mode, each 9-bit section) INPUTS OE X X H H L L L L DIR X X X X L L H H CLKAB X L X X X L CLKBA X L X L X X SAB X X X X X X L H SBA X X X X L H X X Input Unspecified Input Input disabled Output Output Input Input disabled DATA I/O A1 THRU A9 B1 THRU B9 Unspecified Input Input Input disabled Input Input disabled Output Output OPERATION OR FUNCTION Store A, B unspecified Store B, A unspecified Store A and B data Isolation, hold storage Real-time B data to A bus Stored B data to A bus Real-time A data to B bus
Stored A data to B bus The data output functions can be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs.
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PRODUCT PREVIEW
SN54ABT18646, SN74ABT18646 SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS131-AUGUST 1992-REVISED OCTOBER 1992
BUS B
OE L
DIR L
CLKAB CLKBA X X
SAB X
SBA L
OE L
DIR H
CLKAB X
CLKBA X
SAB L
BUS B SBA X REAL-TIME TRANSFER BUS A TO BUS B CLKAB X L CLKBA L X SAB X H BUS B SBA H X TRANSFER STORED DATA TO A AND/OR B
BUS A
REAL-TIME TRANSFER BUS B TO BUS A
BUS B
BUS A
OE X X H
DIR X X X
CLKAB CLKBA X X STORAGE FROM A, B, OR A AND B
SAB X X X
SBA X X X
OE L L
Figure 1. Bus-Management Functions
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BUS A DIR L H
BUS A
PRODUCT PREVIEW
SN54ABT18646, SN74ABT18646 SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS131-AUGUST 1992-REVISED OCTOBER 1992
functional block diagram
1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB 62 53 55 54 59 60
Boundary-Scan Register
C1 1D
1A1
63
C1 1D 1 of 9 Channels
51
1B1
2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB
30 27 28 23 22
C1 1D
2A1
10
C1 1D 1 of 9 Channels
40
2B1
Bypass Register
Boundary-Control Register Identification Register
VCC 24 TDI VCC 56 TMS 26 TCK Pin numbers shown are for the PM package.
58
Instruction Register
TDO
TAP Controller
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PRODUCT PREVIEW
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SN54ABT18646, SN74ABT18646 SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS131-AUGUST 1992-REVISED OCTOBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note NO TAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (I/O ports) (see Note NO TAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 5.5 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . - 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT18646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT18646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Maximum package power dissipation at TA = 55C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . 885 mW Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. For the SN74ABT18646 (PM package), the power derating factor for ambient temperatures greater than 55C is -10.5 mW/C.
recommended operating conditions (see Note 3)
PRODUCT PREVIEW
SN54ABT18646 MIN VCC VIH VIL VI IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate - 55 0 4.5 2 0.8 VCC - 24 48 10 125 MAX 5.5
SN74ABT18646 MIN 4.5 2 0.8 0 VCC - 32 64 10 - 40 85 MAX 5.5
UNIT V V V V mA mA ns /V C
TA Operating free-air temperature NOTE 3: Unused or floating pins (input or I/O) must be held high or low.
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SN54ABT18646, SN74ABT18646 SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS131-AUGUST 1992-REVISED OCTOBER 1992
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Note 4)
PARAMETER VIK VCC = 4.5 V, VCC = 4.5 V, VCC = 5 V, VCC = 4.5 V, VCC = 4.5 V, VOL VCC = 4 5 V 4.5 VCC = 5.5 V, VI = VCC or GND VCC = 5.5 V, VI = VCC VCC = 5.5 V, VI = GND VCC = 5.5 V, VCC = 5.5 V, VCC = 0, VCC = 5.5 V, VO = 5.5 V VCC = 5.5 V, VCC = 5.5 V, IO = 0, VI = VCC or GND TEST CONDITIONS II = -18 mA IOH = - 3 mA IOH = - 3 mA IOH = - 24 mA IOH = - 32 mA IOL = 48 mA IOL = 64 mA CLK, DIR, OE, S, TCK A or B ports TDI, TMS TDI, TMS VO = 2.7 V VO = 0.5 V VI or VO 5.5 V Outputs high VO = 2.5 V Outputs high A or B Outputs low orts ports Outputs disabled - 50 -100 0.9 30 0.9 MIN 2.5 3 2 2 0.55 0.55 1 100 10 -160 50 - 50 100 50 -180 2 38 2 1.5 15 3 10 - 50 50 -180 2 38 2 1.5 15 - 50 TA = 25C TYP MAX -1.2 2.5 3 2 2 0.55 0.55 1 100 10 -160 50 - 50 1 100 10 -160 50 - 50 100 50 -180 2 38 2 1.5 15 mA pF pF pF mA A A A A A A mA V SN54ABT18646 MIN MAX -1.2 2.5 3 V SN74ABT18646 MIN MAX -1.2 UNIT V
VOH
II
A
IIH IIL IOZH IOZL Ioff ICEX IO ICC
ICC# Ci Cio Co
VCC = 5.5 V, One input at 3.4 V, , , Other inputs at VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V Control inputs A or B ports
VO = 2.5 V or 0.5 V TDO 8 NOTE 4: Preliminary specifications based on SPICE analysis All typical values are at VCC = 5 V. On products compliant to MIL-STD-883, Class B, this parameter does not apply. The parameters IOZH and IOZL include the input leakage current. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
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PRODUCT PREVIEW
SN54ABT18646, SN74ABT18646 SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS131-AUGUST 1992-REVISED OCTOBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Note 4 and Figure 2)
SN54ABT18646 MIN fclock tw tsu th Clock frequency Pulse duration Setup time Hold time CLKAB or CLKBA CLKAB or CLKBA high or low A before CLKAB or B before CLKBA A after CLKAB or B after CLKBA 0 MAX 100 SN74ABT18646 MIN 0 3 5 0 MAX 100 UNIT MHz ns ns ns
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Note 4 and Figure 2)123
SN54ABT18646 MIN fclock tw tsu Clock frequency Pulse duration Setup time TCK TCK high or low A, B, CLK, DIR, OE, or S before TCK TDI before TCK TMS before TCK A, B, CLK, DIR, OE, or S after TCK th td tr Hold time Delay time TDI after TCK TMS after TCK Power up to TCK Rise time VCC power up NOTE 4: Preliminary specifications based on SPICE analysis 0 MAX 50 SN74ABT18646 MIN 0 5 5 6 6 0 0 0 50 1 ns s ns ns MAX 50 UNIT MHz ns
PRODUCT PREVIEW
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SN54ABT18646, SN74ABT18646 SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS131-AUGUST 1992-REVISED OCTOBER 1992
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Note 4 and Figure 2)
PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ FROM (INPUT) CLKAB or CLKBA A or B CLKAB or CLKBA SAB or SBA DIR B or A B or A B or A B or A B or A B or A B or A TO (OUTPUT) VCC = 5 V, TA = 25C MIN 100 TYP 130 MAX SN54ABT18646 MIN 100 MAX SN74ABT18646 MIN 100 1 1 2 2 2 2 2 2 2 2 2 2 2 2 6 6 6 6 8 8 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 MAX MHz ns ns ns ns ns ns ns UNIT
OE DIR OE
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Note 4 and Figure 2)123
PARAMETER fmax tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ FROM (INPUT) TCK TCK TCK TCK TCK TCK TCK A or B TDO A or B TDO A or B TDO TO (OUTPUT) VCC = 5 V, TA = 25C MIN 50 TYP 90 MAX SN54ABT18646 MIN 50 MAX SN74ABT18646 MIN 50 3 3 2 2 3 3 2 2 3 3 2 2 12 12 7 7 14 14 8 8 14 14 8 8 MAX MHz ns ns ns ns ns ns UNIT
tPLZ NOTE 4: Preliminary specifications based on SPICE analysis
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PRODUCT PREVIEW
SN54ABT18646, SN74ABT18646 SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS131-AUGUST 1992-REVISED OCTOBER 1992
PARAMETER MEASUREMENT INFORMATION
7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open
LOAD CIRCUIT FOR OUTPUTS 3V Timing Input tw 3V Input 1.5 V 1.5 V 0V Data Input tsu 1.5 V th 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 0V
PRODUCT PREVIEW
VOLTAGE WAVEFORMS PULSE DURATION
Input (see Note B) tPLH Output
3V 1.5 V 1.5 V 0V tPHL VOH 1.5 V 1.5 V VOL tPHL tPLH VOH 1.5 V 1.5 V VOL
Output Control tPZL Output Waveform 1 S1 at 7 V (see Note C) Output Waveform 2 S1 at Open (see Note C) tPZH
3V 1.5 V 1.5 V 0V tPLZ 1.5 V tPHZ VOH - 0.3 V VOH
3.5 V VOL + 0.3 V VOL
Output
1.5 V
[0V
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NON-INVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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Copyright (c) 1998, Texas Instruments Incorporated

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