View SCBS115A_1000126.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SN74BCT979 9-BIT REGISTERED BTL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
SCBS115A - OCTOBER 1990 - REVISED NOVEMBER 1993
* * * * * * * * * * * *
BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Support IEEE BTL Standard 1194.1-1991 Open-Collector B Port Drives Load Impedances as Low as 10 BTL Logic Level 1-V Bus Swing Reduces Power Consumption Latchable Transceiver With Output Sink of 24 mA at the A Bus and 100 mA at the B Bus Option to Generate and Check Parity or Feed-Through Data/Parity in Directions A to B or B to A Independent Latch Enables for A-to-B and B-to-A Directions Select Pin for ODD/EVEN Parity ERRA and ERRB Output Pins for Parity Checking Ability to Simultaneously Generate and Check Parity Packaged in 300-mil Plastic Shrink Small-Outline (DL) Package
DL PACKAGE (TOP VIEW)
VCC AI1 AO1 AI2 AO2 GND AI3 AO3 AI4 AO4 AI5 GND AO5 AI6 AO6 AI7 AO7 GND AI8 AO8 APARI APARO VCC LEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
OEBA LEAB B1 GND GND B2 ERRA B3 GND GND B4 ODD/EVEN B5 SEL B6 GND GND B7 ERRB B8 GND GND BPAR OEAB
description
The SN74BCT979 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver, or it can generate/check parity from the 8-bit data bus in either direction. It has a guaranteed current-sinking capability of 24 mA at the A bus and 100 mA at the open-collector B bus. The SN74BCT979 features independent latch-enable (LEAB, LEBA) inputs for the A-to-B direction and the B-to-A direction, an ODD/EVEN input to select odd or even parity, and separate error-signal (ERRA, ERRB) outputs for checking parity. When communication between buses occurs, parity is generated and passed on to either bus as APARO or BPAR. Error detection of the parity generated from AI1 - AI8 and B1 - B8 can be checked by ERRA and ERRB, providing LEAB and LEBA are high and the mode select (SEL) is low. If SEL is high, the communication between buses is in a feed-through mode where parity is still generated and checked as ERRA and ERRB. The SN74BCT979 features open-collector driver outputs (B port) with a series Schottky diode to reduce capacitive loading to the bus. By using a 2-V pullup on the bus, the output signal swing will be approximately 1 V, which reduces the power necessary to drive the bus load capacitance. The driver outputs are capable of driving an equivalent dc load of as low as 10 . The transceiver has a precision threshold set by an internal bandgap reference to give accurate input thresholds over VCC and temperature variations. This transceiver is compatible with backplane transceiver logic (BTL) technology at significantly reduced power dissipation per channel. The SN74BCT979 is characterized for operation from 0C to 70C.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
SN74BCT979 9-BIT REGISTERED BTL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
SCBS115A - OCTOBER 1990 - REVISED NOVEMBER 1993
FUNCTION TABLE INPUTS OEAB H H H H H L L L L OEBA H L L L L H H H H SEL X L L H H L L H H LEAB X X X X X H L H L LEBA X H L H L X X X X OPERATION OR FUNCTION Isolation. AO1 - AO8 /APARO are in the high-impedance state and B1 - B8 /APAR are high. Parity is generated from B1 - B8 data and output on APARO and is checked against BPAR and output on ERRB. Parity is generated from latched B1 - B8 data and output on APARO and is checked against BPAR and output on ERRB. BPAR is output on APARO. Parity is generated from B1 - B8 data, checked against BPAR, and output on ERRB. BPAR is output on APARO. Parity is generated from latched B1 - B8 data, checked against BPAR, and output on ERRB. Parity is generated from AI1 - AI8 data and output on BPAR and is checked against APARI and output on ERRA. Parity is generated from latched AI1 - AI8 data and output on BPAR and is checked against APARI and output on ERRA. APARI is output on BPAR. Parity is generated from AI1 - AI8 data, checked against APARI, and output on ERRA. APARI is output on BPAR. Parity is generated from latched AI1 - AI8 data, checked against APARI, and output on ERRA.
L L X X X AO1 - AO8 /APARO and B1 - B8 /BPAR are active (high or low logic levels). Parity is generated from AI1 - AI8 and from B1 - B8 based on the level present at ODD/EVEN. Parity is checked (AI1 - AI8 against APARI and B1 - B8 against BPAR) based on the level present at ODD/EVEN (see parity function table). PARITY FUNCTION TABLE INPUTS OEAB L L L L L L L L L L L L L L L L H SEL L L L L L L L L H H H H H H H H X ODD/EVEN L L L L H H H H L L L L H H H H X OF INPUTS AI1 - AI8 = H 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 X APARI L L H H L L H H L L H H L L H H X OUTPUTS BPAR L H L H H L H L L L H H L L H H H ERRA H L L H L H H L H L L H L H H L X
Parity functions for the A bus are shown. Parity functions for the B bus are similar, but use B1 - B8 and BPAR as inputs and APARO and ERRB as outputs.
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74BCT979 9-BIT REGISTERED BTL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
SCBS115A - OCTOBER 1990 - REVISED NOVEMBER 1993
LATCH FUNCTION TABLES INPUTS OUTPUT OEAB L L L H LEAB H H L X AI L H X X B L H Q0 H
INPUTS OEBA L L L LEBA H H L B L H X
OUTPUT AO L H Q0
H X X Z If LEAB = H, current AI1 - AI8 and APARI data is used. If LEAB = L, latched AI1 - AI8 and APARI data is used.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN74BCT979 9-BIT REGISTERED BTL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
SCBS115A - OCTOBER 1990 - REVISED NOVEMBER 1993
logic diagram (positive logic)
OEAB
LEAB AI1 - AI8 LEBA OEBA AO1 - AO8 8 8
C1 1D
Latch 8X
EN
Buffer 8X 8 B1 - B8
8 EN Buffer 8X C1 Latch 8X 1D 8 2k
ODD/EVEN C1 APARI 1D
Parity
ERRA
8
2k Parity ERRB
C1 1D
EN APARO 1 SEL G1 1 EN BPAR 1 G1 1
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74BCT979 9-BIT REGISTERED BTL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
SCBS115A - OCTOBER 1990 - REVISED NOVEMBER 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (see Note 1): B1- B8, BPAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 5.5 V Other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC Input clamp current, IIK (VI < 0) (A port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30 mA Current into any output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Maximum power dissipation at TA = 55C (in still air) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.85 W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input negative-voltage rating may be exceeded if the input clamp-current rating is observed.
recommended operating conditions (see Note 2)
MIN VCC VIH VIL VOH IIK IOH IOL t /v Supply voltage High level input voltage High-level Low-level Low level input voltage High-level output voltage Input clamp current High-level output current Low level output current Low-level Input transition rise or fall rate AO1 - AO8, APARO, ERRA, ERRB AO1 - AO8, APARO, ERRA, ERRB B1 - B8, BPAR Outputs enabled 0 B1 - B8, BPAR Other inputs B1 - B8, BPAR Other inputs B1 - B8, BPAR 4.5 1.6 2 1.47 0.8 2.1 -18 -3 24 100 10 70 NOM 5 MAX 5.5 UNIT V V V mA mA mA mA ns / V C
TA Operating free-air temperature NOTE 2: Unused or floating pins (input or I/O) must be held high or low.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN74BCT979 9-BIT REGISTERED BTL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
SCBS115A - OCTOBER 1990 - REVISED NOVEMBER 1993
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK IOH VOH LE, OE, SEL, ODD/EVEN, AI1 - AI8, APARI B1 - B8, BPAR AO1 - AO8 APARO, ERRA, ERRB AO8, APARO ERRA VCC = 4.5 V, VCC = 5.5 V, VCC = 4 5 V 4.5 TEST CONDITIONS II = -18 mA VOH = 2.1 mA IOH = -1 mA IOH = - 3 mA IOL = 24 mA IOL = 80 mA IOL = 100 mA VI = 5.5 V VI = 2.7 V VI = 2.1 V VI = 0.5 V VI = 0.3 V VO = 2.7 V VO = 0.5 V VO = 0 Outputs open - 60 17 VCC = 5.5 V, 69 21 VCC = 5 V V, VCC = 5 V, VCC = 5 V, B port VI = 2.5 V or 0.5 V 25 05 VO = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 8 8 5 6.5 1 2.5 2.4 0.75 0.75 3.4 3.3 0.35 0.5 1.1 1.15 100 20 100 - 20 -100 50 - 50 - 200 36 85 42 pF pF pF ns mA A A A A A mA V MIN TYP MAX -1.2 100 UNIT V A V
VOL II IIH IIL IOZH IOZL IOS ICC
AO1 - AO8, APARO, ERRA, ERRB LE, OE, SEL, ODD/EVEN, AI1 - AI8, APARI LE, OE, SEL, ODD/EVEN, AI1 - AI8, APARI B1 - B8, BPAR LE, OE, SEL, ODD/EVEN, AI1 - AI8, APARI B1 - B8, BPAR AO1 - AO8, APARO AO1 - AO8, APARO AO1 - AO8, APARO Outputs high Outputs low Outputs disabled LE, OE, SEL, ODD/EVEN AI1 - AI8, APARI B1 - B8, BPAR AO1 - AO8, APARO
VCC = 4.5 V VCC = 5.5 V, VCC = 5 5 V 5.5 VCC = 5 5 V 5.5 VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V,
Ci Cio Co
TT Output transition time All typical values are at VCC = 5 V, TA = 25C. For I/O ports, the parameters IIH and IIL include the off-state output current. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. Measured from 1.3 V to 1.8 V (see Figure 1).
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC = 5 V, TA = 25C MIN tw Pulse duration LEAB high LEBA high Data high AI1 - AI8, APARI before LEAB AI8 tsu Setup time B1 - B8, BPAR before LEBA B8 AI1 - AI8, APARI after LEAB AI8 th Hold time B1 - B8, BPAR after LEBA B8 Data low Data high Data low Data high Data low Data high Data low 5 4 4 3 8.5 7 1 2.5 0.5 0.5 MAX 5 4 4 3 8.5 7 1 2.5 0.5 0.5 ns ns ns MIN MAX UNIT
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74BCT979 9-BIT REGISTERED BTL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
SCBS115A - OCTOBER 1990 - REVISED NOVEMBER 1993
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Note 3)
PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPLH tPHL tPHL tPLH tPLH tPHL tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL FROM (INPUT) AI AI B B APARI BPAR AI APARI AI APARI B BPAR B BPAR ODD/EVEN ODD/EVEN ODD/EVEN ODD/EVEN SEL SEL ERRB ERRA ERRB APARO BPAR APARO BPAR ERRB ERRA ERRA TO (OUTPUT) B BPAR AO APARO BPAR APARO VCC = 5 V, TA = 25C MIN 1.3 2.1 3.7 5.4 2.8 2.4 4.5 4.2 1.6 3.4 2.7 3 3 2.8 4.2 4 4.3 4.2 5.5 5.5 3.4 4.4 3.4 4.6 3.4 3.1 4 4.9 0.7 1.1 1.1 2.8 TYP 6.8 7.8 11.6 13.9 9 8.1 14.1 13.3 6 9.5 7.9 8.1 10.9 8.2 11.8 8.9 13.4 10.8 14.5 11.3 9.1 10.3 8.7 10 8.7 9 10.3 12.3 5.3 5 6.4 8.3 MAX 8.6 9.8 13.9 15.7 11.1 10 16.1 15.9 7.7 11.2 9.9 10 13 10.2 14 10.9 15.9 13.1 17 13.5 10.9 12.2 10.7 11.9 10.6 10.9 12.1 14.1 6.9 6.5 8.1 9.9 1.3 2.1 3.7 5.4 2.8 2.4 4.5 4.2 1.6 3.4 2.7 3 3 2.8 4.2 4 4.3 4.2 5.5 5.5 3.4 4.4 3.4 4.6 3.4 3.1 4 4.9 0.7 1.1 1.1 2.8 10.4 11.8 17.6 19.2 14.3 12.3 20.9 20.5 9.3 13.6 12.8 12.5 16.1 12.6 16.7 12.8 20.6 16.6 21.5 16.5 13.7 14.5 13.3 14.2 13.5 13.4 15.8 17.3 8.4 7.8 10.1 12.6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN MAX UNIT
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
7
SN74BCT979 9-BIT REGISTERED BTL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
SCBS115A - OCTOBER 1990 - REVISED NOVEMBER 1993
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Note 3) (continued)
PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ FROM (INPUT) LEAB LEAB LEAB LEAB LEBA LEBA LEBA LEBA TO (OUTPUT) B BPAR (parity feed through) BPAR (parity generated) ERRA AO APARO (parity feed through) APARO (parity generated) ERRB B BPAR AO AO APARO APARO VCC = 5 V, TA = 25C MIN 1.6 2.7 2.3 4.6 4.7 6.2 3.3 4.7 1.3 1.4 1.7 1.9 3.5 3.1 3.4 4.6 1.5 4.9 1.4 4.8 1.4 6 2.4 1.2 1.7 1.4 2.7 1.2 TYP 7.6 8.1 7.3 9.3 10.7 11.5 8.6 9.8 6.5 5.9 5.9 6 9.3 8.2 8.7 9 5.5 10.4 5.4 10.6 6 10.7 6.7 4.7 6.1 5.1 6.8 4.7 MAX 9.5 10 9.2 11 13 13.4 10.7 12 8.5 7.6 7.7 7.8 11.5 10.3 10.8 11 7 12.1 6.9 12.5 7.8 12.5 8.6 6.3 7.8 6.7 8.6 6.2 1.6 2.7 2.3 4.6 4.7 6.2 3.3 4.7 1.3 1.4 1.7 1.9 3.5 3.1 3.4 4.6 1.5 4.9 1.4 4.8 1.4 6 2.4 1.2 1.7 1.4 2.7 1.2 11.6 11.7 10.8 13.3 16.2 16 12.8 13.7 10 8.5 9.1 9 14.1 12.2 12.7 12.5 7.9 14.1 7.8 14.9 9.2 14.6 9.5 7.1 9.3 7.8 9.5 7.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN MAX UNIT
OEAB OEAB OEBA OEBA OEBA OEBA
NOTE 3: Load circuits and waveforms are shown in Section 1.
8
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SCBS115A

	To Download SCBS115A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .