View SCAS617A_999995.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SN74LVCH32244A 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCAS617A - OCTOBER 1998 - REVISED JUNE 1999
D D D D D D
Member of the Texas Instruments Widebus TM Family EPICTM ( Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Ioff Supports Partial-Power-Down-Mode Operation Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
D D D D
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Packaged in Plastic Fine-Pitch Ball Grid Array Package
description
This 32-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVCH32244A is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74LVCH32244A is characterized for operation from -40C to 85C.
FUNCTION TABLE (each 4-bit buffer) INPUTS OE L L H A H L X OUTPUT Y H L Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
SN74LVCH32244A 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCAS617A - OCTOBER 1998 - REVISED JUNE 1999
GKE PACKAGE (TOP VIEW)
6 5 4 3 2 1 A B C D E F G H J K L MN P R T
terminal assignments
6 5 4 3 2 1 1A2 1A1 2OE 1OE 1Y1 1Y2 A 1A4 1A3 GND GND 1Y3 1Y4 B 2A2 2A1 VCC VCC 2Y1 2Y2 C 2A4 2A3 GND GND 2Y3 2Y4 D 3A2 3A1 GND GND 3Y1 3Y2 E 3A4 3A3 VCC VCC 3Y3 3Y4 F 4A2 4A1 GND GND 4Y1 4Y2 G 4A3 4A4 3OE 4OE 4Y4 4Y3 H 5A2 5A1 6OE 5OE 5Y1 5Y2 J 5A4 5A3 GND GND 5Y3 5Y4 K 6A2 6A1 VCC VCC 6Y1 6Y2 L 6A4 6A3 GND GND 6Y3 6Y4 M 7A2 7A1 GND GND 7Y1 7Y2 N 7A4 7A3 VCC VCC 7Y3 7Y4 P 8A2 8A1 GND GND 8Y1 8Y2 R 8A3 8A4 7OE 8OE 8Y4 8Y3 T
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVCH32244A 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCAS617A - OCTOBER 1998 - REVISED JUNE 1999
logic diagram (positive logic)
1OE A3 3OE A2 H4
1A1
A5
1Y1
3A1
E5
E2
3Y1
1A2
A6
A1
1Y2
3A2
E6
E1
3Y2
1A3
B5
B2
1Y3
3A3
F5
F2
3Y3
1A4
B6
B1
1Y4
3A4
F6
F1
3Y4
2OE
A4
4OE C2
H3
2A1
C5
2Y1
4A1
G5
G2
4Y1
2A2
C6
C1
2Y2
4A2
G6
G1
4Y2
2A3
D5
D2
2Y3
4A3
H6
H1
4Y3
2A4
D6
D1
2Y4
4A4
H5
H2
4Y4
5OE
J3
7OE J2
T4
5A1
J5
5Y1
7A1
N5
N2
7Y1
5A2
J6
J1
5Y2
7A2
N6
N1
7Y2
5A3
K5
K2
5Y3
7A3
P5
P2
7Y3
5A4
K6
K1
5Y4
7A4
P6
P1
7Y4
6OE
J4
8OE L2
T3
6A1
L5
6Y1
8A1
R5
R2
8Y1
6A2
L6
L1
6Y2
8A2
R6
R1
8Y2
6A3
M5
M2
6Y3
8A3
T6
T1
8Y3
6A4
M6
M1
6Y4
8A4
T5
T2
8Y4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN74LVCH32244A 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCAS617A - OCTOBER 1998 - REVISED JUNE 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 High or low state 3-state VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 0 0 1.65 1.5 0.65 x VCC 1.7 2 0.35 x VCC 0.7 0.8 5.5 VCC 5.5 -4 -8 -12 -24 4 8 12 24 10 ns/V mA mA V V V V MAX 3.6 UNIT V
VIH
High-level input voltage
VIL VI VO
Low-level input voltage Input voltage Output voltage
IOH
High-level High level output current
IOL
Low-level Low level output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature -40 85 C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVCH32244A 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCAS617A - OCTOBER 1998 - REVISED JUNE 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = -100 A IOH = -4 mA VOH IOH = -8 mA IOH = -12 mA 12 IOH = -24 mA IOL = 100 A VOL IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA II VI = 0 to 5.5 V VI = 0.58 V VI = 1.07 V VI = 0.7 V II(hold) ( ) VI = 1.7 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V Ioff IOZ ICC ICC Ci VI or VO = 5.5 V VO = 0 to 5.5 V VI = VCC or GND 3.6 V VI 5.5 V One input at VCC - 0.6 V, VI = VCC or GND VO = VCC or GND IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 1.65 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3V 1.65 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3.6 V 1.65 1 65 V 23V 2.3 3V 3.6 V 0 3.6 V 3.6 36V 2.7 V to 3.6 V 3.3 V 5.5 25 -25 45 -45 75 -75 500 10 10 20 20 500 A A A A pF A MIN TYP MAX UNIT VCC-0.2 1.2 1.7 2.2 2.4 2.2 0.2 0.45 0.7 0.4 0.55 5 A V V
Co 3.3 V 6 pF All typical values are at VCC = 3.3 V, TA = 25C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. This applies in the disabled state only.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
PARAMETER tpd ten tdis tsk(o)# This information was not available at the time of publication. # Skew between any two outputs of the same package switching in the same direction FROM (INPUT) A OE OE TO (OUTPUT) Y Y Y VCC = 1.8 V 0.15 V MIN MAX VCC = 2.5 V 0.2 V MIN MAX VCC = 2.7 V MIN MAX 4.7 5.8 6.2 VCC = 3.3 V 0.3 V MIN 1.1 1 1.8 MAX 4.1 4.6 5.8 1.5 ns ns ns ns UNIT
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN74LVCH32244A 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCAS617A - OCTOBER 1998 - REVISED JUNE 1999
operating characteristics, TA = 25C
PARAMETER Cpd d Power dissipation capacitance per buffer/driver Outputs enabled Outputs disabled TEST CONDITIONS f = 10 MHz VCC = 1.8 V TYP VCC = 2.5 V TYP VCC = 3.3 V TYP 34 4 UNIT pF
This information was not available at the time of publication.
PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 0.15 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 1 k S1 Open GND 1 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVCH32244A 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCAS617A - OCTOBER 1998 - REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
7
SN74LVCH32244A 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCAS617A - OCTOBER 1998 - REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT
tw 2.7 V
Timing Input tsu Data Input 1.5 V
2.7 V 1.5 V 0V th 2.7 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
Input
1.5 V
1.5 V 0V
VOLTAGE WAVEFORMS PULSE DURATION
Output Control (low-level enabling) tPZL
2.7 V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V VOL + 0.3 V tPHZ VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL
2.7 V Input 1.5 V 1.5 V 0V tPLH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHL VOH 1.5 V VOL
Output Waveform 1 S1 at 6 V (see Note B) tPZH Output Waveform 2 S1 at GND (see Note B)
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1999, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SCAS617A

	To Download SCAS617A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .