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54ACT16540, 74ACT16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCAS186A - OCTOBER 1991 - REVISED APRIL 1996
D D D D D D D D D D
Members of the Texas Instruments WidebusTM Family Inputs Are TTL-Voltage Compatible Provide Extra Data Width Necessary for Wider Address/Data Paths Provide Inverted Data 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process 500-mA Typical Latch-Up Immunity at 125C Package Options Include Shrink Small-Outline 300-mil (DL) Package Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings
54ACT16540 . . . WD PACKAGE 74ACT16540 . . . DL PACKAGE (TOP VIEW)
description
These 16-bit buffers/bus drivers provide a high-performance bus interface for wide data paths. The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state.
1OE1 1Y1 1Y2 GND 1Y3 1Y4 VCC 1Y5 1Y6 GND 1Y7 1Y8 2Y1 2Y2 GND 2Y3 2Y4 VCC 2Y5 2Y6 GND 2Y7 2Y8 2OE1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1OE2 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE2
The 74ACT16540 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54ACT16540 is characterized for operation over the full military temperature range of -55C to 125C. The 74ACT16540 is characterized for operation from -40C to 85C.
FUNCTION TABLE (each 8-bit section) INPUTS OE1 L L H X OE2 L L X H A L H X X OUTPUT Y H L Z Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright (c) 1996, Texas Instruments Incorporated
* DALLAS, TEXAS 75265
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54ACT16540, 74ACT16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCAS186A - OCTOBER 1991 - REVISED APRIL 1996
logic symbol
1OE1 1OE2 2OE1 2OE2 24 25 & EN2 1 48 & EN1
logic diagram (positive logic)
1OE1 1OE2 1 48
1A1
47
2
1Y1
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8
47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1 2 1 1
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 To Seven Other Channels 2OE1 2OE2 2A1 24 25 To Seven Other Channels
36
13
2Y1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA Maximum power package dissipation at TA = 55C (in still air) (see Note 2): DL package . . . . . . . . . . 1.2 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
54ACT16540, 74ACT16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCAS186A - OCTOBER 1991 - REVISED APRIL 1996
recommended operating conditions (see Note 3)
54ACT16540 MIN VCC VIH VIL VI VO IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 -55 0 0 4.5 2 0.8 VCC VCC - 24 24 10 125 0 -40 0 0 NOM 5 MAX 5.5 74ACT16540 MIN 4.5 2 0.8 VCC VCC - 24 24 10 85 NOM 5 MAX 5.5 UNIT V V V V V mA mA ns/ V C
TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = - 50 A VOH IOH = - 24 mA IOH = - 75 mA IOL = 50 A VOL IOL = 24 mA IOL = 75 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, IO = 0 VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5V 5V 4 13 0.1 0.5 8 0.9 0.1 0.1 0.36 0.36 TA = 25C MIN TYP MAX 4.4 5.4 3.94 4.94 54ACT16540 MIN 4.4 5.4 3.8 4.8 3.85 0.1 0.1 0.44 0.44 1.65 1 5 80 1 MAX 74ACT16540 MIN 4.4 5.4 3.8 4.8 3.85 0.1 0.1 0.44 0.44 1.65 1 5 80 1 A A A mA pF pF V V MAX UNIT
II IOZ ICC ICC Ci Co
One input at 3.4 V, Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
54ACT16540, 74ACT16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCAS186A - OCTOBER 1991 - REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) A TO (OUTPUT) Y Y Y MIN 2.1 3.9 2.7 3.6 5.4 5.4 TA = 25C TYP MAX 5.1 6.8 6.2 7.5 9.2 8.6 6.8 8.5 8 9.5 10.9 10.3 54ACT16540 MIN 2.1 3.9 2.7 3.6 5.4 5.4 MAX 7.5 9.5 8.9 10.5 11.9 11.1 74ACT16540 MIN 2.1 3.9 2.7 3.6 5.4 5.4 MAX 7.5 9.5 8.9 10.5 11.9 11.1 UNIT ns ns ns
OE OE
operating characteristics, VCC = 5 V, TA = 25C
PARAMETER Cpd d Power dissipation capacitance per buffer Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF pF, f = 1 MHz TYP 42 8.5 UNIT pF
PARAMETER MEASUREMENT INFORMATION
2 x VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT 3V Input tPLH In-Phase Output tPHL Out-of-Phase Output 50% VCC 50% VCC 1.5 V 1.5 V 0V tPHL VOH 50% VCC VOL tPLH VOH 50% VCC VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH Output Control (low-level enabling) 3V 1.5 V tPZL tPLZ 50% VCC tPHZ 80% VCC VOH 20% VCC 1.5 V 0V
[ VCC
VOL
50% VCC
[0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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Copyright (c) 1998, Texas Instruments Incorporated

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