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S25FL Family (Serial Peripheral Interface)
64 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
ADVANCE INFORMATION
Notice to Readers: The Advance Information status indicates that this document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Publication Number S25FL064A_00
Revision A
Amendment 0
Issue Date April 26, 2005
Advance
Information
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice."
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications."
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"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
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S25FL Family (Serial Peripheral Interface)
S25FL064A_00_A0 April 26,
S25FL Family (Serial Peripheral Interface) S25FL064A
64 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
Data Sheet
ADVANCE INFORMATION
Distinctive Characteristics
Architectural Advantages
Single power supply operation -- Full voltage range: 2.7 to 3.6 V read and program operations Memory Architecture -- 128 sectors with 512 Kb each Program -- Page Program (up to 256 bytes) in 1.5 ms (typical) -- Program cycles are on a page by page basis Erase -- 1.5 s typical sector erase time -- Bulk Erase Cycling Endurance -- 100,000 cycles per sector typical Data Retention -- 20 years typical Device ID -- JEDEC standard two-byte electronic signature -- RES instruction one-byte electronic signature for backward compatibility Process Technology -- Manufactured on 0.20 m MirrorBitTM process technology Package Option -- Industry Standard Pinouts -- 16-pin SO package (300 mils)
Performance Characteristics
Speed -- 50 MHz clock rate (maximum) Power Saving -- Standby Mode 50 A (max) -- Deep Power Down Mode 1 A (typical)
Memory Protection Features
Memory Protection -- W# pin works in conjunction with Status Register Bits to protect specified memory areas -- Status Register Block Protection bits (BP2, BP1, BP0) in status register configure parts of memory as readonly
Software Features
SPI Bus Compatible Serial Interface
Publication Number S25FL064A_00
Revision A
Amendment 0
Issue Date April 26, 2005
Advance
Information
General Description
The S25FL064A device is a 3.0 Volt (2.7 V to 3.6 V) single power supply Flash memory device. S25FL064A consists of 128 sectors, each with 512 Kb memory. Data appears on SI input pin when inputting data into the memory and on the SO output pin when outputting data from the memory. The devices are designed to be programmed in-system with the standard system 3.0 Volt VCC supply. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory supports Sector Erase and Bulk Erase instructions. Each device requires only a 3.0 Volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program operations. This device does not require VPP supply.
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Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . Input/Output Descriptions . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 4 5 6 7
Figure 11. Read Identification (RDID) Instruction Sequence and Data-Out Sequence...................................... 23 Table 6. Read Identification (RDID) Data-Out Sequence ........ 24
Page Program (PP) ............................................................................... 24
Figure 12. Page Program (PP) Instruction Sequence.............. 25
Table 1. S25FL Valid Combinations Table .............................. 7
Signal Description ................................................................................... 8 SPI Modes .................................................................................................. 8
Figure 1. Bus Master and Memory Devices on the SPI Bus ....... 9 Figure 2. SPI Modes Supported............................................ 9
Sector Erase (SE) ...................................................................................25
Figure 13. Sector Erase (SE) Instruction Sequence ............... 26
Bulk Erase (BE) ...................................................................................... 26
Figure 14. Bulk Erase (BE) Instruction Sequence .................. 27
Operating Features . . . . . . . . . . . . . . . . . . . . . . . . 10 Protection Modes ................................................................................... 11
Table 2. Protected Area Sizes (S25FL064A). .........................11
Deep Power Down (DP) ....................................................................27
Figure 15. Deep Power Down (DP) Instruction Sequence ....... 28
Release from Deep Power Down (RES) ....................................... 28
Figure 16. Release from Deep Power Down Instruction Sequence........................................................................ 29
Hold Condition Modes ......................................................................... 11
Figure 3. Hold Condition Activation...................................... 12
Memory Organization . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Sector Address Table - S25FL064A ..........................13
Release from Deep Power Down and Read Electronic Signature (RES) ...................................................................................... 29
Figure 17. Release from Deep Power Down and Read Electronic Signature (RES) Instruction Sequence .................. 30 Figure 18. Power-Up Timing............................................... 31 Table 7. Power-Up Timing ................................................. 31
Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Instruction Set .....................................................17
Write Enable (WREN) ......................................................................... 17
Figure 4. Write Enable (WREN) Instruction Sequence............. 17
Write Disable (WRDI) ........................................................................ 18
Figure 5. Write Disable (WRDI) Instruction Sequence ............ 18
Read Status Register (RDSR) ............................................................. 19
Figure 6. Read Status Register (RDSR) Instruction Sequence ........................................................................ 19 Figure 7. Status Register Format......................................... 19
Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . 32 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 33 CMOS Compatible ...............................................................................33
Table 8. DC Characteristics ................................................ 33
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 19. AC Measurements I/O Waveform......................... 34 Table 9. Test Specifications ............................................... 34 Table 10. AC Characteristics .............................................. 35 Figure 20. SPI Mode 0 (0,0) Input Timing ............................ 36 Figure 21. SPI Mode 0 (0,0) Output Timing.......................... 36 Figure 22. HOLD# Timing.................................................. 37 Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1 ....................................................... 37
Write Status Register (WRSR) ......................................................... 20
Figure 8. Write Status Register (WRSR) Instruction Sequence ........................................................................ 20 Table 5. Protection Modes ..................................................21
Read Data Bytes (READ) .................................................................... 21
Figure 9. Read Data Bytes (READ) Instruction Sequence ........ 22
Read Data Bytes at Higher Speed (FAST_READ) ...................... 22
Figure 10. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence ........................................................ 23
Read Identification (RDID) ................................................................ 23
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 38 S016 Wide--16-pin Plastic Small Outline 300 mils Body Width Package .......................................................................................38 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 39
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Block Diagram
SRAM
PS
Array - L Logic
X D E C
Array - R
RD
DATA PATH
IO CS#
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HOLD#
SCK
GND
SI
VCC
SO
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Connection Diagrams
16-pin Plastic Small Outline Package (SO)
HOLD# VCC NC NC NC NC CS# SO
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
SCK SI NC NC NC NC GND W#
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Input/Output Descriptions
SCK SI SO CS# W# HOLD# VCC GND = = = = = = = = Serial Clock Input Serial Data Input Serial Data Output Chip Select Input Write Protect Input Hold Input Supply Voltage Input Ground Input
Logic Symbol
VCC
SI SCK CS# W# HOLD#
SO
GND
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Ordering Information
The ordering part number is formed by a valid combination of the following: S25FL 064 A 0L M A 1 00 1
PACKING TYPE
0 = Tray ((Note 2) 1 = Tube (Standard; (Note 1) 3 = 13" Tape and Reel (Note 2)
MODEL NUMBER (Additional Ordering Options)
00 = No additional ordering options
TEMPERATURE RANGE
I = Industrial (-40C to + 85C)
PACKAGE MATERIALS
A = Standard F = Lead (Pb)-free (Note 2)
PACKAGE TYPE
M = 16- pin Plastic Small Outline Package
SPEED
0L = 50MHz
DEVICE TECHNOLOGY
A = 0.20 m MirrorBitTM Process Technology
DENSITY
064 = 64Mb
DEVICE FAMILY
S25FL SpansionTM Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory
Table 1. S25FL Valid Combinations Table
S25FL Valid Combinations Base Speed Ordering Part Option Number
S25FL064A 0L
Package & Temperature
MAI, MFI NAI, NFI (Note 2)
Model Packing Number Type
00 0, 1, 3 (Note 1)
Package Marking (Note 3)
FL064A + (Temp) (Note 4)
Notes: 1. Type 1 is standard. Specify other options as required. 2. Contact your local sales office for availability. 3. Package marking omits leading S25 and speed, package, and leading digit of model number from ordering part number. 4. A for standard package (non-Pb free). F for Pb-free package.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device.
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Signal Description
Signal Data Output (SO): This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (SCK). Serial Data Input (SI): This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (SCK). Serial Clock (SCK): This input signal provides the timing of the serial interface. Instructions, addresses, and data present at the Serial Data input (SI) are latched on the rising edge of Serial Clock (SCK). Data on Serial Data Output (SO) changes after the falling edge of Serial Clock (SCK). Chip Select (CS#): When this input signal is High, the device is deselected and Serial Data Output (SO) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device is in Standby mode. Driving Chip Select (CS#) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (CS#) is required prior to the start of any instruction. Hold (HOLD#): The Hold (HOLD#) signal is used to pause any serial communications with the device without deselecting the device. During the Hold instruction, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SCK) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (CS#) driven Low. Write Protect (W#): The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register).
SPI Modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: CPOL = 0, CPHA = 0 CPOL = 1, CPHA = 1 For these two modes, input data is latched in on the rising edge of Serial Clock (SCK), and output data is available from the falling edge of Serial Clock (SCK). The difference between the two modes, as shown in Figure 2, on page 9 is the clock polarity when the bus master is in Standby and not transferring data: SCK remains at 0 for (CPOL = 0, CPHA = 0) SCK remains at 1 for (CPOL = 1, CPHA = 1)
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SO
SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) Bus Master
SI SCK SCK SO SI SCK SO SI SCK SO SI
SPI Memory Device CS3 CS2 CS1
CS# W# HOLD#
SPI Memory Device
SPI Memory Device
CS#
W# HOLD#
CS#
W# HOLD#
Figure 1. Bus Master and Memory Devices on the SPI Bus
Note: The Write Protect (W#) and Hold (HOLD#) signals should be driven, High or Low as appropriate.
CS# CPOL 0 1 CPHA 0 1 SCK SCK SI SO MSB MSB
Figure 2.
SPI Modes Supported
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Operating Features
All data into and out of the device is shifted in 8-bit chunks.
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle. To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory.
Sector Erase, or Bulk Erase
The Page Program (PP) instruction allows bits to be programmed from 1 to 0. Before this can be applied, the bytes of the memory need to be first erased to all 1's (FFh) before any programming. This can be achieved in two ways: 1) a sector at a time using the Sector Erase (SE) instruction, or 2) throughout the entire memory, using the Bulk Erase (BE) instruction.
Polling During a Write, Program, or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst-case delay. The Write in Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle, or Erase cycle is complete. Active Power and Standby Power Modes When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes into the Standby Power mode. The device consumption drops to ISB. This can be used as an extra Deep Power Down on mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program, or Erase instructions.
Status Register
The Status Register contains a number of status and control bits, as shown in Figure 7, on page 19 that can be read or set (as appropriate) by specific instructions WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP2, BP1, BP0 bits: The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W#) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W#) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits.
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Protection Modes
The SPI memory device boasts the following data protection mechanisms: All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: -- Power-up -- Write Disable (WRDI) instruction completion -- Write Status Register (WRSR) instruction completion -- Page Program (PP) instruction completion -- Sector Erase (SE) instruction completion -- Bulk Erase (BE) instruction completion The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect (W#) signal works in cooperation with the Status Register Write Disable (SRWD) bit to enable write-protection. This is the Hardware Protected Mode (HPM). Program, Erase and Write Status Register instructions are checked to verify that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.
Table 2. Protected Area Sizes (S25FL064A).
Protected Area None Upper 64th (2 sectors) Upper 32nd (4 sectors) Upper sixteenth (8 sectors) Upper eighth (16 sectors) Upper quarter (32 sectors) Upper half (64 sectors) All (128 sectors) Status Register Contents BP2 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 Memory Content Protected Area None 7E0000h-7FFFFFh 7C0000h-7FFFFFh 780000h-7FFFFFh 700000h-7FFFFFh 600000h-7FFFFFh 400000h-7FFFFFh 000000h-7FFFFFh Unprotected Area 000000h-7FFFFFh 000000h-7DFFFFh 000000h-7BFFFFh 000000h-77FFFFh 000000h-6FFFFFh 000000h-5FFFFFh 000000h-3FFFFFh None
Hold Condition Modes
The Hold (HOLD#) signal is used to pause any serial communications with the device without resetting the clocking sequence. Hold (HOLD#) signal gates the clock input to the device. However, taking this signal Low does not terminate any Write Status Register, Program or Erase Cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition starts on the falling edge of the Hold (HOLD#) signal, provided that this coincides with Serial Clock (SCK) being Low (as shown in Figure 3, on page 12). The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides with Serial Clock (SCK) being Low.
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If the falling edge does not coincide with Serial Clock (SCK) being Low, the Hold condition starts after Serial Clock (SCK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (SCK) being Low, the Hold condition ends after Serial Clock (SCK) next goes Low (Figure 3). During the Hold condition, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SCK) are Don't Care. Normally, the device remains selected, with Chip Select (CS#) driven Low, for the entire duration of the Hold condition. This ensures that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD#) High, and then to drive Chip Select (CS#) Low. This prevents the device from going back to the Hold condition.
SCK HOLD#
Hold Condition (standard use)
Hold Condition (non-standard use)
Figure 3. Hold Condition Activation
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Memory Organization
The memory is organized as: S25FL064A: 128 sectors of 512 Kbit each Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk erasable (bits are erased from 0 to 1).
Table 3.
Sector Address Table - S25FL064A (Sheet 1 of 3)
Address Range
7F0000h 7E0000h 7D0000h 7C0000h 7B0000h 7A0000h 790000h 780000h 770000h 760000h 750000h 740000h 730000h 720000h 710000h 700000h 6F0000h 6E0000h 6D0000h 6C0000h 6B0000h 6A0000h 690000h 680000h 670000h 660000h 650000h 640000h 630000h 620000h 610000h 600000h 5F0000h 5E0000h 5D0000h 5C0000h 5B0000h 7FFFFFh 7EFFFFh 7DFFFFh 7CFFFFh 7BFFFFh 7AFFFFh 79FFFFh 78FFFFh 77FFFFh 76FFFFh 75FFFFh 74FFFFh 73FFFFh 72FFFFh 71FFFFh 70FFFFh 6FFFFFh 6EFFFFh 6DFFFFh 6CFFFFh 6BFFFFh 6AFFFFh 69FFFFh 68FFFFh 67FFFFh 66FFFFh 65FFFFh 64FFFFh 63FFFFh 62FFFFh 61FFFFh 60FFFFh 5FFFFFh 5EFFFFh 5DFFFFh 5CFFFFh 5BFFFFh
Sector
SA127 SA126 SA125 SA124 SA123 SA122 SA121 SA120 SA119 SA118 SA117 SA116 SA115 SA114 SA113 SA112 SA111 SA110 SA109 SA108 SA107 SA106 SA105 SA104 SA103 SA102 SA101 SA100 SA99 SA98 SA97 SA96 SA95 SA94 SA93 SA92 SA91
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Table 3. Sector Address Table - S25FL064A (Sheet 2 of 3)
SA90 SA89 SA88 SA87 SA86 SA85 SA84 SA83 SA82 SA81 SA80 SA79 SA78 SA77 SA76 SA75 SA74 SA73 SA72 SA71 SA70 SA69 SA68 SA67 SA66 SA65 SA64 SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 SA54 SA53 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 5A0000h 590000h 580000h 570000h 560000h 550000h 540000h 530000h 520000h 510000h 500000h 4F0000h 4E0000h 4D0000h 4C0000h 4B0000h 4A0000h 490000h 480000h 470000h 460000h 450000h 440000h 430000h 420000h 410000h 400000h 3F0000h 3E0000h 3D0000h 3C0000h 3B0000h 3A0000h 390000h 380000h 370000h 360000h 350000h 340000h 330000h 320000h 310000h 300000h 2F0000h 2E0000h 2D0000h 5AFFFFh 59FFFFh 58FFFFh 57FFFFh 56FFFFh 55FFFFh 54FFFFh 53FFFFh 52FFFFh 51FFFFh 50FFFFh 4FFFFFh 4EFFFFh 4DFFFFh 4CFFFFh 4BFFFFh 4AFFFFh 49FFFFh 48FFFFh 47FFFFh 46FFFFh 45FFFFh 44FFFFh 43FFFFh 42FFFFh 41FFFFh 40FFFFh 3FFFFFh 3EFFFFh 3DFFFFh 3CFFFFh 3BFFFFh 3AFFFFh 39FFFFh 38FFFFh 37FFFFh 36FFFFh 35FFFFh 34FFFFh 33FFFFh 32FFFFh 31FFFFh 30FFFFh 2FFFFFh 2EFFFFh 2DFFFFh
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Table 3. Sector Address Table - S25FL064A (Sheet 3 of 3)
SA44 SA43 SA42 SA41 SA40 SA39 SA38 SA37 SA36 SA35 SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 2C0000h 2B0000h 2A0000h 290000h 280000h 270000h 260000h 250000h 240000h 230000h 220000h 210000h 200000h 1F0000h 1E0000h 1D0000h 1C0000h 1B0000h 1A0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h 0D0000h 0C0000h 0B0000h 0A0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h 000000h 2CFFFFh 2BFFFFh 2AFFFFh 29FFFFh 28FFFFh 27FFFFh 26FFFFh 25FFFFh 24FFFFh 23FFFFh 22FFFFh 21FFFFh 20FFFFh 1FFFFFh 1EFFFFh 1DFFFFh 1CFFFFh 1BFFFFh 1AFFFFh 19FFFFh 18FFFFh 17FFFFh 16FFFFh 15FFFFh 14FFFFh 13FFFFh 12FFFFh 11FFFFh 10FFFFh 0FFFFFh 0EFFFFh 0DFFFFh 0CFFFFh 0BFFFFh 0AFFFFh 09FFFFh 08FFFFh 07FFFFh 06FFFFh 05FFFFh 04FFFFh 03FFFFh 02FFFFh 01FFFFh 00FFFFh
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Instructions
All instructions, addresses, and data are shifted in and out of the device, starting with the most significant bit. Serial Data Input (SI) is sampled on the first rising edge of Serial Clock (SCK) after Chip Select (CS#) is driven Low. Then, the onebyte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (SI), each bit being latched on the rising edges of Serial Clock (SCK). The instruction set is listed in Table 4 on page 17. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence is shifted in. In the case of a Read Data Bytes (READ), Read Status Register (RDSR), Read Data Bytes at higher speed (FAST_READ) and Read Identification (RDID) instructions, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out to terminate the transaction. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), or Write Disable (WRDI) instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected
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Table 4.
Instruction WREN WRDI RDSR WRSR READ Description Write Enable Write Disable
Instruction Set
One-Byte Address Dummy Instruction Code Bytes Byte Data Bytes 06H (0000 0110) 04H (0000 0100) 0 0 0 0 3 3 0 3 0 0 0 0 0 0 1 0 0 0 0 0 0 3 0 0 1 to Infinity 1 1 to Infinity 1 to Infinity 1 to 3 0 0 1 to 256 0 0 1 to Infinity
Status Register Operations
Read from Status Register 05H (0000 0101) Write to Status Register 01H (0000 0001) Read Operations Read Data Bytes 03H (0000 0011) 0BH (0000 1011) 9FH (1001 1111) Erase Operations D8H (1101 1000) C7H (1100 0111) Program Operations
Read Data Bytes FAST_READ at Higher Speed RDID SE BE PP DP Read Identification Sector Erase Bulk (Chip) Erase
Page Program 02H (0000 0010) 3 Deep Power Down Savings Mode Operations Deep Power Down Release from Deep Power Down B9H (1011 1001) ABH (1010 1011) ABH (1010 1011) 0 0 0
RES
Release from Deep Power Down and Read Electronic Signature
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 4) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the instruction code, and then driving Chip Select (CS#) High.
CS# 01 SCK Instruction SI High Impedance SO 234567
Figure 4. Write Enable (WREN) Instruction Sequence
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Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 5) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (CS#) Low, sending the instruction code, and then driving Chip Select (CS#) High. The Write Enable Latch (WEL) bit is reset under the following conditions: Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion
CS# 01234567 SCK Instruction SI High Impedance SO
Figure 5.
Write Disable (WRDI) Instruction Sequence
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Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase, or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 6.
CS# 01 SCK Instruction SI High Impedance SO Status Register Out Status Register Out 2 3 4 5 6 7 8 9 10 11 12 13 14 15
76543210765432107 MSB MSB
Figure 6. Read Status Register (RDSR) Instruction Sequence
b7 SRWD 0 0 BP2 BP1 BP0 WEL
b0 WIP
Status Register Write Disable
Block Protect Bits Write Enable Latch Bit Write In Progress Bit
Figure 7. Status Register Format
The status and control bits of the Status Register are as follows: SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W#) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W#) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. BP2, BP1, BP0 bits: The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (Table 2 on page 11) becomes protected against Page Program (PP), and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode is not set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0.
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WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1, the internal Write Enable Latch is set; when set to 0, the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. This bit is a read only bit and is read by executing a RDSR instruction. If this bit is 1, such a cycle is in progress, if it is 0, no such cycle is in progress.
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it is accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction is decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code (Figure 8) and the data byte on Serial Data Input (SI). The Write Status Register (WRSR) instruction has no effect on bits b6, b1 and b0 of the Status Register. Bit b6 is always read as 0. Chip Select (CS#) must be driven High after the eighth bit of the data byte is latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) is reset. The WRSR instruction enables the user to select one of nine levels of protection. The S25FL064A is divided into eight array segments. The top one twenty-eighth, sixty-fourth, thirty-second, sixteenth, eighth, quarter, half or all of the memory segments can be protected (as defined in Table 1 on page 7). The data within a selected segment is therefore read-only. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W#) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W#) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.
CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Status Register In
SI High Impedance SO MSB
Figure 8. Write Status Register (WRSR) Instruction Sequence
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Table 5.
W# Signal 1 1 0 0 SRWD Bit 1 0 0 1 Mode Software Protected (SPM) Hardware Protected (HPM)
Protection Modes
Protected Area (See Note) Unprotected Area (See Note)
Write Protection of the Status Register
Status Register is Writable (if the Protected against Page Ready to accept Page WREN instruction set the WEL bit) Program and Erase Program and Sector The values in the SRWD, BP2, BP1 (SE, BE) Erase Instructions and BP0 bits can be changed Status Register is Hardware write Protected against Page Ready to accept Page protected Program and Erase Program and Sector The values in the SRWD, BP2, BP1 (SE, BE) Erase Instructions and BP0 bits cannot be changed
Note:As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2 on page 11.
The protection features of the device are summarized in Table 5. When the Status Register Write Disable (SRWD) bit is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit was previously set by a Write Enable (WREN) instruction, regardless of whether Write Protect (W#) is driven High or Low. When the Status Register Write Disable (SRWD) bit is set to 1, two cases need to be considered, depending on the state of Write Protect (W#): If Write Protect (W#) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit was previously set by a Write Enable (WREN) instruction. If Write Protect (W#) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit was previously set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution.) As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: By setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W#) Low. By driving Write Protect (W#) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered, is to pull Write Protect (W#) High. If Write Protect (W#) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated and only the Software Protected Mode (SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used.
Read Data Bytes (READ)
The READ instruction reads the memory at the specified SCK frequency (fSCK) with a maximum speed of 25 MHz.
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The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23A0), each bit being latched-in during the rising edge of Serial Clock (SCK). Then the memory contents, at that address, are shifted out on Serial Data Output (SO), each bit being shifted out, at a frequency fSCK, during the falling edge of Serial Clock (SCK). The instruction sequence is shown in Figure 9. The first byte addressed can be at any location. The address automatically increments to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 00000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while a Program, Erase, or Write cycle is in progress, is rejected without having any effect on the cycle that is in progress.
CS# 0 1 2 3 4 5 6 7 8 9 10 SCK
Instruction 24-Bit Address
28 23 30 31 32 33 34 35 36 37 38 39
SI
High Impedance
23 22 21
MSB
3210
Data Out 1 Data Out 2
SO
765432
MSB
107
Figure 9. Read Data Bytes (READ) Instruction Sequence
Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction reads the memory at the specified SCK frequency (fSCK) with a maximum speed of 50 MHz. The device is first selected by driving Chip Select (CS#) Low. The instruction code for (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latchedin during the rising edge of Serial Clock (SCK). Then the memory contents, at that address, are shifted out on Serial Data Output (SO), each bit being shifted out, at a maximum frequency FSCK, during the falling edge of Serial Clock (SCK). The instruction sequence is shown in Figure 10, on page 23. The first byte addressed can be at any location. The address automatically increments to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 00000h, allowing the read sequence to be continued indefinitely.
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The (FAST_READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any (FAST_READ) instruction, while an Erase, Program, or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
Instruction 23 22 21 24-Bit Address 3 2 1 0 7 6 Dummy Byte 5 4 3 2 1 0 DATA OUT 1 DATA OUT 2 1 0 7 MSB
SI SO
High Impedance
7 MSB
6
5
4
3
2
Figure 10.
Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence
Read Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of the device identification. The manufacturer identification byte is assigned by JEDEC, and has a value of 01h for SpansionTM products. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (02h), and the memory capacity of the device in the second byte (16h). Any Read Identification (RDID) instruction executed while an Erase, Program, or Write Status Register cycle is in progress is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (CS#) Low. Then, the 8-bit instruction code for the instruction is shifted in, with each bit being latched in on SI during the rising edge of SCK. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output (SO), with each bit being shifted out during the falling edge of Serial Clock (SCK). The instruction sequence is shown in Figure 11.
CS#
SCK
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
Instruction SI Manufacturer Identification SO High Impedance MSB Device Identification 15 14 13 3 2 1 0
Figure 11. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
Driving CS# high after the Device Identification is read at least once terminates the READ_ID instruction. The Read Identification (RDID) instruction can also be terminated by driving CS# High at any time during data output.
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When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
Table 6. Read Identification (RDID) Data-Out Sequence
Manufacturer Identification 01h Device Identification Memory Type 02h Memory Capacity 16h
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction is decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (SI). Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 12, on page 25. If more than 256 bytes are sent to the device, the addressing wraps to the beginning of the same page, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If fewer than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. Chip Select (CS#) must be driven High after the eighth bit of the last data byte is latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
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A Page Program (PP) instruction applied to a page that is protected by the Block Protect (BP2, BP1, BP0) bits (Table 2 on page 11) is not executed.
CS#
0 1 2 3 4 5 6 7 8 9 10
SCK
28 29 30 31 32 33 34 35 36 37 38 39
Instruction
24-Bit Address
Data Byte 1
SI
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
2072
7 MSB
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK
Data Byte 2
Data Byte 3
SI
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
MSB
Figure 12. Page Program (PP) Instruction Sequence
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction is decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (SI). Any address inside the Sector (Table 2 on page 11) is a valid address for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 13, on page 26. Chip Select (CS#) must be driven High after the eighth bit of the last address byte is latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to any memory area that is protected by the Block Protect (BP2, BP1, BP0) bits (Table 2 on page 11) is not executed.
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Data Byte 256 5 4 3 2 1 0
CS#
25
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CS#
0 SCK
1
2
3
4
5
6
7
8
9
10
28
29
30
31
Instruction
24 Bit Address
SI
23 22 MSB
21
3
2
1
0
Figure 13.
Sector Erase (SE) Instruction Sequence
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets to 1 (FFh) all bits inside the entire memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction is decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, on Serial Data Input (SI). No address is required for the Bulk Erase (BE) instruction. Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14, on page 27. Chip Select (CS#) must be driven High after the eighth bit of the last address byte is latched in, otherwise the Bulk Erase (BE) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
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A Bulk Erase (BE) instruction is executed only if all the Block Protect (BP2, BP1, BP0) bits (see Table 2 on page 11) are set to 0. The Bulk Erase (BE) instruction is ignored if one or more sectors are protected.
CS#
0
1
2
3
4
5
6
7
SCK
Instruction
SI
Figure 14. Bulk Erase (BE) Instruction Sequence
Deep Power Down (DP)
The Deep Power Down (DP) instruction puts the device in the lowest current mode of 1 A typical. It is recommended that the standard Standby mode be used for the lowest power current draw, as well as the Deep Power Down (DP) as an extra software protection mechanism when this device is not in active use. In this mode, the device ignores all Write, Program and Erase instructions. Chip Select (CS#) must be driven Low for the entire duration of the sequence. The Deep Power Down (DP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code on Serial Data Input (SI). Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15, on page 28. Driving Chip Select (CS#) High after the eighth bit of the instruction code is latched, places the device in Deep Power Down mode. The Deep Power Down mode can only be entered by executing the Deep Power Down (DP) instruction to reduce the standby current (from ISB to IDP as specified in Table 8 on page 33). As soon as Chip Select (CS#) is driven high, it requires a delay of tDP currently in progress before Deep Power Down mode is entered. Once the device enters the Deep Power Down mode, all instructions are ignored except the Release from Deep Power Down (RES) and Read Electronic Signature. This releases the device from the Deep Power Down mode. The Release from Deep Power Down and Read Electronic Signature (RES) instruction also allows the Electronic Signature of the device to be output on Serial Data Output (SO). The Deep Power Down mode automatically stops at Power-down, and the device always powers up in the Standby mode.
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Any Deep Power Down (DP) instruction, while an Erase, Program, or WRSR cycle is in progress, is rejected without having any effect on the cycle in progress.
CS#
tDP 0 SCK Instruction 1 2 3 4 5 6 7
SI
Standby Mode
Deep Power Down Mode
Figure 15. Deep Power Down (DP) Instruction Sequence
Release from Deep Power Down (RES)
The Release from Deep Power Down (RES) instruction provides the only way to exit the Deep Power Down mode. Once the device enters the Deep Power Down mode, all instructions are ignored except the Release from Deep Power Down (RES) instruction. Executing this instruction takes the device out of Deep Power Down mode. The Release from Deep Power Down (RES) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code on Serial Data Input (SI). Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16, on page 29. Driving Chip Select (CS#) High after the 8-bit instruction byte is received by the device, but before the whole of the 8-bit Electronic Signature is transmitted for the first time, still insures that the device is placed into Standby mode. If the device was previously in the Deep Power Down mode, though, the transition to the Stand-by Power mode is delayed by tRES, and Chip Select (CS#) must remain High for at least tRES(max), as specified in Table 10 on page 35. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode, and execute instructions.
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CS#
0 SCK
1
2
3
4
5
6
7
Instruction
t
RES
SI
Deep Power Down Mode
Standby Mode
Figure 16.
Release from Deep Power Down Instruction Sequence
Release from Deep Power Down and Read Electronic Signature (RES)
Once the device enters Deep Power Down mode, all instructions are ignored except the RES instruction. The RES instruction can also be used to read the oldstyle 8-bit Electronic Signature of the device on the SO pin. The RES instruction always provides access to the device's Electronic Signature (except while an Erase, Program, or WRSR cycle is in progress), and can be applied even if DP mode was not entered. Any RES instruction executed while an Erase, Program, or WRSR cycle is in progress, is not decoded and has no effect on the cycle in progress. The device features an 8-bit Electronic Signature, whose value for the S25FL064A is 16h. This is read using the RES instruction. The device is first selected by driving Chip Select (CS#) Low. The instruction code is followed by three dummy bytes, each bit being latched-in on Serial Data Input (SI) during the rising edge of Serial Clock (SCK). Then, the 8-bit Electronic Signature, stored in the memory, is shifted out on Serial Data Output (SO), each bit being shifted out during the falling edge of Serial Clock (SCK). The instruction sequence is shown in Figure 17, on page 30. The Release from Deep Power Down and Read Electronic Signature (RES) is terminated by driving Chip Select (CS#) High after the Electronic Signature is read at least once. Sending additional clock cycles on Serial Clock (SCK), while Chip Select (CS#) is driven Low, causes the Electronic Signature to be output repeatedly.
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When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power Down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power Down mode, though, the transition to the Standby mode is delayed by tRES, and Chip Select (CS#) must remain High for at lease tRES(max), as specified in Table 10 on page 35. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode, and execute instructions.
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
SCK
Instruction 3 Dummy Bytes
23 22 21 MSB 32 1 0 Electronic ID out 7 MSB Deep Power Down Mode Standby Mode 6 5 4 3 2 1 0
tRES
SI SO
High Impedance
Figure 17. Release from Deep Power Down and Read Electronic Signature (RES) Instruction Sequence
Power-up and Power-down
The device must not be selected at power-up or power-down (that is, CS# must follow the voltage applied on VCC) until VCC reaches the correct value as follows: VCC (min) at power-up, and then for a further delay of tPU (Table 7 on page 31) VSS at power-down A simple pull-up resistor on Chip Select (CS#) can usually be used to insure safe and proper power-up and power-down. The device ignores all instructions until a time delay of tPU (Table 7 on page 31) has elapsed after the moment that VCC rises above the minimum VCC threshold. However, correct operation of the device is not guaranteed if by this time VCC is still below VCC (min). No Write Status Register, Program or Erase instructions should be sent until tPU after VCC reaches the minimum VCC threshold. At power-up, the device is in Standby mode (not Deep Power Down mode) and the WEL bit is reset. Normal precautions must be taken for supply rail decoupling to stabilize the VCC feed. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins (this capacitor is generally of the order of 0.1 F).
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At power-down, when VCC drops from the operating voltage to below the minimum VCC threshold, all operations are disabled and the device does not respond to any instructions. (The designer needs to be aware that if a power-down occurs while a Write, Program or Erase cycle is in progress, data corruption can result.)
Vcc Vcc
(max)
Vcc
(min)
tPU
Full Device Access
Time
Figure 18. Power-Up Timing
Table 7. Power-Up Timing
Symbol VCC(min) tPU VCC (minimum) VCC (min) to device operation Parameter Min 2.7 10 Max Unit V ms
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Initial Delivery State
The device is delivered with all bits set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0).
Maximum Rating
Stressing the device above the rating listed in the Absolute Maximum Ratings section below may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
Ambient Storage Temperature . . . . . . . . . . . . . . . . . . . . . -65C to +150C Voltage with Respect to Ground: All Inputs and I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4.5 V
Operating Ranges
Ambient Operating Temperature (TA)
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
Positive Power Supply
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 3.6 V
Note: Operating ranges define those limits between which functionality of the device is guaranteed.
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DC Characteristics
This section summarizes the DC and AC Characteristics of the device. Designers should check that the operating conditions in their circuit match the measurement conditions specified in the Test Specifications in Table 9 on page 34, when relying on the quoted parameters.
CMOS Compatible
Table 8.
Parameter Description VCC ICC1 ICC2 ICC3 ICC4 ICC5 ISB IDP ILI ILO VIL VIH VOL VOH Supply Voltage SCK = 0.1 VCC/0.9VCC Active Read Current SCK = 0.1 VCC/0.9VCC Active Page Program Current CS# = VCC Active WRSR Current Active Sector Erase Current Active Bulk Erase Current Standby Current Deep Power Down Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA, VCC = VCC min IOH = -0.1 mA VCC - 0.2 CS# = VCC CS# = CS# = VCC VCC 25 MHz VCC = 3.0V 50 MHz
DC Characteristics
Min 2.7 Typ. 3 8 10 Max 3.6 10 13 26 28 26 26 50 1 10 1 1 -0.3 0.7 VCC 0.3 VCC VCC + 0.5 0.4 Unit V mA mA mA mA mA mA A A A A V V V V
Test Conditions (See Note)
VCC = 3.0 V CS# = VCC VCC = 3.0 V CS# = VCC VIN = GND to VCC VIN = GND to VCC
Note:Typical values are at TA = 25C and 3.0 V.
April 26, 2005 S25FL064A_00_A0
S25FL Family (Serial Peripheral Interface) S25FL064A
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Test Conditions
Input Levels 0.8 VCC Input and Output Timing Reference levels 0.7 VCC 0.5 VCC 0.3 VCC
0.2 VCC
Figure 19. AC Measurements I/O Waveform Table 9.
Symbol CL
Test Specifications
Min 30 5 0.2 VCC to 0.8 VCC 0.3 VCC to 0.7 VCC 0.5 VCC Max Unit pF ns V V V
Parameter Load Capacitance Input Rise and Fall Times Input Pulse Voltage Input Timing Reference Voltage Output Timing Reference Voltage
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S25FL Family (Serial Peripheral Interface) S25FL064A
S25FL064A_00_A0 April 26, 2005
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AC Characteristics
Table 10. AC Characteristics
Symbol (Notes) FSCK FSCK tCRT tCFT tWH tWL tCS Parameter SCK Clock Frequency READ instruction Typ Max Min (Notes) (Notes) Unit D.C. 25 50 MHz MHz V/ns V/ns ns ns ns ns ns ns ns ns ns 9 ns ns ns ns 5 5 10 10 10 15 15 60 3 30 1.5 (1) 1.5 (1) 3 (2) 3 (2) ns ns ns ns ns ns ns ms s s ms sec
SCK Clock Frequency for: D.C. FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR Clock Rise Time (Slew Rate) Clock Fall Time (Slew Rate) SCK High Time SCK Low Time CS# High Time 0.1 0.1 9 9 100 5 5 5 5 5 5 0 0 5 5
tCSS (3) CS# Setup Time tCSH (3) CS# HOLD Time tHD (3) HOLD# Setup Time (relative to SCK) tCD (3) HOLD# Hold Time (relative to SCK) tHC tCH tV tHO HOLD# Setup Time (relative to SCK) HOLD# Hold Time (relative to SCK) Output Valid Output Hold Time
tHD:DAT Data in Hold Time tSU:DAT Data in Setup Time tR tF Input Rise Time Input Fall Time
tLZ (3) HOLD# to Output Low Z tHZ (3) HOLD# to Output High Z tDIS (3) Output Disable Time tWPS (3) Write Protect Setup Time tWPH (3) Write Protect Hold Time tW tDP tRES tPP tSE tBE Write Status Register Time CS# High to Deep Power Down Mode Release DP Mode Page Programming Time Sector Erase Time Bulk Erase Time
192 (1) 384 (2) sec
Notes: 1. Typical program and erase times assume the following conditions: 25C, VCC = 3.0V; 10, 000 cycles; checkerboard data pattern 2. Under worst-case conditions of 90C; VCC = 2.7V; 100,000 cycles 3. Not 100% tested
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S25FL Family (Serial Peripheral Interface) S25FL064A
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AC Characteristics
tCS
CS#
tCSH
tCSS
tCSH
tCSS
SCK
tCFT tSU:DAT tHD:DAT tCRT
SI MSB IN LSB IN
High Impedance SO
Figure 20.
SPI Mode 0 (0,0) Input Timing
CS#
tWH
SCK
tV tV tHO tHO tWL tDIS
SO
LSB OUT
Figure 21.
SPI Mode 0 (0,0) Output Timing
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S25FL Family (Serial Peripheral Interface) S25FL064A
S25FL064A_00_A0 April 26, 2005
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Information
AC Characteristics
CS#
tCH
tHD
tHC
SCK
tCD tHZ tLZ
SO
SI
HOLD#
Figure 22. HOLD# Timing
W#
tWPS
tWPH
CS#
SCK
SI
SO
High Impedance
Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1
April 26, 2005 S25FL064A_00_A0
S25FL Family (Serial Peripheral Interface) S25FL064A
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Physical Dimensions
S016 Wide--16-pin Plastic Small Outline 300 mils Body Width Package
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S25FL Family (Serial Peripheral Interface) S25FL064A
S25FL064A_00_A0 April 26, 2005
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Information
Revision Summary
Revision A0 (April 26, 2005)
Initial Release.
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c)2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies
April 26, 2005 S25FL064A_00_A0
S25FL Family (Serial Peripheral Interface) S25FL064A
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