QL901M QuickMIPSTM Data Sheet
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QuickMIPS Embedded Standard Product (ESP) Family
Device Highlights
CPU Core
* 32-bit MIPS 4Kc processor runs up to 133 MHz (173 Dhrystone MIPS) * 1.3 Dhrystone MIPS per MHz * MDU supports MAC instructions for DSP functions * 16 KB of instruction cache (4-way set associative) * 16 KB of data cache (4-way set associative), lockable on a per line basis
Two Ethernet Controllers
* Two 10/100 MACs * Provides MII connection to external transceivers/devices
Two UARTs
* One with modem control signals * Both with IRDA-compliant signals
Four General Purpose 16-bit Timer/Counters
* 16-bit prescaler to increase timer/counter delay * Four modes of operation: decrement, increment, interval, and Pulse Width Modulation (PWM) * Operation from the System Bus clock or a clock source supplied from the Programmable Fabric
SDRAM Memory Controller
* Support for PC-100 type SDRAMs, up to 256 MB total * Two chip selects * Operates at one-half CPU pipeline speed * Support for x16 and x32 external memory bus configurations
System SRAM
* 16 KB accessible by all System Bus masters Figure 1: QL901M Block Diagram
I/O Peripheral Controller
* Direct support for SRAM, EPROM and Flash * 8-bit, 16-bit and 32-bit device widths supported * Eight independent chip selects
18 ECU Blocks (8x8 Multiply, 16-bit carry/add)
ViaLink FPGA Fabric
36 RAM Blocks (128x18, 256x9, 512x4, 1024x2)
PCI Controller
* 32-bit v2.2 compatible * Up to 66 MHz operation * Supports host and satellite configurations * Dedicated DMA channels for transmit and receive bus transactions * Support for external bus master arbitration (through FPGA library provided by QuickLogic)
Low Speed Peripherals 16 Bit Timer
(X4)
AHB Master
AHB Slave
APB Slave (3)
16K SRAM
32 Bit System Bus (AMBA)
ICU
UART
(X2)
10/100 Ethernet MII
10/100 Ethernet MII
PCI Controller
32 Bit MIPS 4Kc
16K 16K Dcache Icache
Memory Controller
PCI 32/66
SDRAM SRAM
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QL901M QuickMIPSTM Data Sheet Rev. F
High Performance 32-bit System Bus (AMBA Bus)
* Operates at one-half of CPU pipeline speed * One 32-bit AHB master port/one 32-bit AHB slave port to programmable Fabric * Three 32-bit APB slave ports in the programmable Fabric
Flexible Programmable Fabric
* 2016 logic cells (536 K system gates) * 252 I/O pins * 2.5 V Vcc, 2.5/3.3 V drive capable I/O * 4,284 dedicated flip-flops * IEEE 1149.1 boundary scan testing compliant
Dual-Port SRAM Modules
* Thirty-six 2,304 bit Dual-Port High Performance SRAM Blocks * 82,944 embedded RAM bits * RAM/ROM/FIFO Wizard for automatic configuration * Configurable and cascadable
Programmable I/O
* High performance I/O cell with Tco <3 ns * Programmable Slew Rate Control * Programmable I/O Standards: LVTTL, LVCMOS, PCI, GTL+, SSTL2, and SSTL3 Independent I/O Banks capable of supporting multiple standards in one device I/O Register Configurations: Input, Output, Output Enable (OE)
Advanced Clock Network
* Multiple dedicated Low Skew Clock Networks * High drive input-only networks * Quadrant-based segmentable clock networks * Two User-programmable Phase Locked Loop (PLL) circuits
Embedded Computational Units (ECUs)
Eighteen hardwired DSP building blocks with integrated Multiply, Add, and Accumulate functions.
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QL901M QuickMIPSTM Data Sheet Rev. F
Security Features
The QuickLogic products come with secure ViaLink technology that protects intellectual property from design theft and reverse engineering. No external configuration memory is needed for the Fabric. The device is instant-on at power-up.
QuickWorks Design Software
The QuickWorks package provides the most complete ESP and Field Programmable Gate Array (FPGA) software solution from design entry to logic synthesis, to place and route, and simulation. The package provides a solution for designers who use third party tools from Cadence, Mentor, Synopsys, and other thirdparty tools for design entry, synthesis, or simulation.
Process Data
The QL901M is fabricated on a 0.25 , six layer metal CMOS process. The core voltage is 2.5 V VCC supply and the I/Os are up to 3.3 V compliant. The QL901M is available in commercial and industrial temperature grades.
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QL901M QuickMIPSTM Data Sheet Rev. F
QL901M Architectural Overview
The QL901M chip can be thought of as having two distinct sides, an Application Specific Standard Product (ASSP) side and a Programmable Fabric side. The ASSP side contains the standard cell circuitry of the device such as the MIPS 4Kc CPU and the Ethernet MACs, and the Fabric side contains all of the programmable logic elements (e.g., logic cells and dual-port RAMs) of the device.
ASSP Side
This section discusses the various circuits in the ASSP portion of the QL901M device.
CPU Core
The MIPS32 4Kc processor core is a high-performance, low-power, 32-bit MIPS RISC core capable of speeds up to 133 MHz. The 4Kc core contains a fully-associative translation lookaside buffer (TLB) based Memory Management Unit (MMU) and a pipelined MDU. The core executes the MIPS32 instruction set architecture (ISA). It supports all application code in the MIPS I, II, III, and IV instruction sets. It also supports kernel code for the R4000 processor and above. The MIPS32 ISA contains special multiply-accumulate, conditional move, prefetch, wait, and zero/one detect instructions. The MMU contains a three-entry instruction TLB (ITLB), a three-entry data TLB (DTLB), and a 16 dual-entry joint TLB (JTLB) with variable page sizes. The 4Kc multiply-divide unit (MDU) supports a maximum issue rate of one 32x16 multiply (MUL/MULT/MULTU), multiply-add (MADD/MADDU), or multiply-subtract (MSUB/MSUBU) operation per clock, or one 32x32 MUL, MADD, or MSUB every other clock. Instruction and Data Caches The instruction and data caches are both 16 Kbytes in size. Each cache is organized as four-way set associative. The data cache has lockout capability per cache line. On a cache miss, loads are blocked only until the first critical word becomes available. The pipeline resumes execution while the remaining words are being written to the cache. Both caches are virtually indexed and physically tagged. Virtual indexing allows the cache to be indexed in the same clock in which the address is generated rather than waiting for the virtual-to physical address translation in the MMU. EJTAG Interface The basic Enhanced JTAG (EJTAG) features provide CPU run control with stop, single stepping and re-start, and software breakpoints through the SDBBP instruction. In addition, instruction and data virtual address hardware breakpoints, and connection to an external EJTAG probe through the Test Access Port (TAP) is included.
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QL901M QuickMIPSTM Data Sheet Rev. F
ASSP PLL
On the ASSP side of the QL901M there is a single clock input that provides an input clock reference for the MIPS core, the System Bus, and all ASSP peripherals (other than the PCI Controller, which is independently driven by the PCI_CLK input). This clock input (PL_CLOCKIN) is the input to a PLL that is fixed at a two times clock multiplication rate. For example, if the clock rate applied to PL_CLOCKIN is 50 MHz, the resultant clock that drives the MIPS core is 100 MHz. Table 1 shows the maximum input clock rates for PL_CLOCKIN based upon the ASSP speed grade of the given QL901M device. Table 1: Maximum Input Frequency for PL_CLOCKIN and MIPS Core Frequency Based on QL901M ASSP Speed Grade
QuickMIPS Device Part Number Prefix QL901M-100 QL901M-133 Maximum Input Frequency for PL_CLOCKIN 50 MHz 66 MHz Resultant Maximum MIPS Core Frequency 100 MHz 133 MHz
SDRAM Memory Controller
The QL901M SDRAM Memory Controller (SDMC) provides all the necessary logic to connect to a wide variety of industry standard SDRAMs for use by the CPU, Ethernet Controllers, PCI Controller, and Programmable Fabric. The SDMC supports a minimum SDRAM size of 16 Mbytes and a maximum SDRAM size of 256 Mbytes. The SDRAM Controller controls the SDRAM on the external bus. On receiving an access request, the SDRAM Controller decides on the appropriate commands to send to the SDRAM memory. The DRAM Bank Controller sequences all of the commands required to complete a read or write request to an SDRAM memory location with timing controlled by the CAS Delay and RAS Delay values. The bus interface is a slave on the System Bus; it contains the control register block. The bus interface produces read, write, refresh and mode register write requests to the SDRAM control engine, and software supplied configuration information. Data is transferred to and from the SDRAM as unbroken quad words. This data packet size is convenient for cache line fills and buffered writes. For accesses smaller than a quad word, extra read data is ignored by the SDRAM Controller; for writes, the SD_DQM(3:0) pins are used to force the SDRAMs to ignore invalid data. For access sizes larger than a quad word, multiple quad word accesses are issued to the SDRAM control engine.
I/O Peripheral Controller
This section describes access to I/O and memory devices on the external M Bus (with the exception of SDRAM). The I/O Peripheral Controller (Figure 2) generates strobes and signals that can be used to interface the M Bus with common asynchronous peripheral devices. The QL901M Peripheral Controller Unit (PCU) provides decoded strobe signals to control external peripherals such as SRAM, flash, real time clock (RTC) and memory mapped I/O devices. It supports 8-bit, 16-bit, and 32-bit widths with programmable wait states and bus turnaround time based on memory speed. The PCU provides the following functionality: * Decoding of memory access in the local CPUs memory map to generate chip selects or strobes. * Control of wait states for decoded regions. A total of eight chip select signals are available. Chip select seven is used as the boot ROM chip select.
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QL901M QuickMIPSTM Data Sheet Rev. F
The M Bus is a shared resource between the SDRAM Controller and I/O Controller. The M Bus is assigned to one of these two controllers by an internal arbiter. There is one turn-around cycle when switching from one controller to the other. Figure 2: SDRAM and I/O Controllers
System Bus
SDRAM Controller
SD_DQM[3:0] SD_CS[1:0] SD_RAS SD_CAS SD_WE SD_CKE[1:0] SD_CLKOUT SD_CLKIN ADDR[14:0] DATA[31:0]
M Bus M Bus Controller MUX
ADDR[23:0] DATA[31:0]
ADDR[23:0] DATA[31:0]
I/O Controller
BLS[3:0] OE WE CS[7:0]
PCI Controller
The QuickMIPS PCI Interface is a 32-bit, 66 MHz, Revision 2.2 compliant interface as specified by the PCI Local Bus Specification. The PCI Controller is a bridge between the on-chip System Bus and the external PCI bus. There are two main modes of operation of the PCI function, each utilizing several resources: * PCI Target PCI Target to PCI configuration registers PCI Target to extended registers (DMA and message/mailbox) * PCI Master System-to-PCI and PCI-to-System DMA
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QL901M QuickMIPSTM Data Sheet Rev. F
Ethernet Controllers
The QL901M has two Ethernet Media Access Controllers (MACs) embedded in the ASSP portion of the device. The Ethernet Controllers incorporate the essential protocol requirements for operation of Ethernet/IEEE 802.3 compliant nodes, and provide interfaces between the host subsystem and the Media Independent Interface (MII). The 10/100 MAC can operate in 10 Mbps or 100 Mbps mode based on the transmit and receive clocks provided (2.5/25 MHz). The controllers contain transmit and receive FIFOs and embedded DMA control. Figure 3 shows a block diagram of the QL901M Ethernet Controller. Figure 3: Ethernet Controller Block Diagram
Fabric
MII 10/100 MAC
TX FIFO
RX FIFO
DMA Controller
System Bus
The DMA Controller is responsible for exchanging data between the FIFOs and the system memory. DMA operation is controllable through a set of control and status registers. EachThe 10/100 MAC operates in half-duplex mode and full-duplex modes. When operating in the halfduplex mode, the 10/100 MAC core is fully compliant to Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard) and ANSI/IEEE 802.3. When operating in the full-duplex mode, the 10/100 MAC core is compliant to the IEEE 802.3x standard for full-duplex operations. EachThe 10/100 MAC is also compatible with Home PNA 1.1. The 10/100 MAC core provides programmable enhanced features designed to minimize host supervision, bus utilization, and pre- or post-message processing. These features include the ability to disable retires after a collision, dynamic FCS generation on a frame-by-frame basis, automatic pad field insertion and deletion to enforce minimum frame size attributes, automatic retransmission and detection of collision frames. The 10/100 MAC core can sustain transmission or reception of minimal-sized back-to-back packets at full line speed with an inter-packet gap (IPG) of 9.6 s for 10-Mb/s and 0.96 s for 100-Mb/s. Data to/from the MAC is buffered in transmit/receive FIFOs. In the case of data received by the Ethernet MAC, the data is drained from the receive FIFO by the DMA Controller and stored to the specified target (typically the data is stored in SDRAM). For Ethernet transmit, the DMA Controller reads data from memory (SDRAM typically) and pushes it into the transmit FIFO. DMA operation is controllable through a set of control and status registers.
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QL901M QuickMIPSTM Data Sheet Rev. F
System SRAM
The QL901M contains 16 K bytes of SRAM internal to the ASSP portion of the device. The SRAM (an AHB slave) can be accessed by any AHB master. Furthermore, the 4Kc core can use this internal SRAM for data or instruction storage. The SRAM supports 32-bit, 16-bit, or single byte accesses.
Interrupt Controller
This section describes the function of the QL901M Interrupt Controller Unit (ICU). Figure 4 shows a block diagram of the Interrupt Controller. Figure 4: Simplified Interrupt Controller Block Diagram
Configuration Options Interrupts from On-Chip Peripherals/Fabric
PLL and Clock Divider (PL)
Clocks and Reset
Global Logic (GL)
Interrupts to CPU
MIPS 4Kc CPU Core
System Bus
The QL901M has 9 on-chip peripheral interrupts and 7 external interrupts (including on NMI), for a total of 16 interrupt sources. These 16 interrupt sources are combined into 7 interrupts by the interrupt controller and fed to the CPU core. External interrupts must be asserted for at least two clock periods in order to be recognized as an interrupt. All interrupts are level triggered. Each interrupt has an Emulation Enable Register bit and an Emulation Interrupt Value Register bit in the Interrupt Controller. The primary use for the Emulation registers is for testing purposes. The interrupt enable bits are stored in the GL_EMUL_EN register. The emulation interrupt value for each possible interrupt is stored in the GL_INT_EMUL register. Each interrupt has an enable bit in the Global Individual Interrupt Enable (GL_IND_INT_EN) register in the Interrupt Controller. The Global CPU Interrupt Enable register (GL_CPU_INT_EN) enables masking of the interrupt groups after they have been grouped together. The Interrupt Controller has no programmability for priority. That is, there is no hardware priority encoder. Priority is provided as a function of software.
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QL901M QuickMIPSTM Data Sheet Rev. F
High Performance 32-Bit System Bus (AMBA Bus)
The purpose of this section is to describe the AMBA1 bus operation for the purposes of implementing user circuits in the Programmable Fabric. All circuits in the ASSP portion of the QL901M chip communicate with the Programmable Fabric primarily through the AMBA bus interfaces (Advanced Microcontroller Bus Architecture from ARM). Circuits implemented in the Programmable Fabric must be designed according to the AMBA Specification, Revision 2.0. The devices within the QL901M are interconnected through the Advanced High-performance Bus (AHB) or the Advanced Peripheral Bus (APB). Refer to the AMBA Specification, Revision 2.0, for more detailed information about the AHB and APB. Advanced High-Performance Bus (AHB) The AHB is the high-performance variant of the AMBA specification. It supports multiple bus masters and provides high bandwidth operation. The AHB implementation in the QL901M is 32 bits wide. All signals are synchronous to the rising clock edge of the bus clock (hclk). The key features of the QL901M AHB include: * Burst transfers * Single-cycle bus master handover * 32-bit bus runs at half the CPU clock frequency * Multiple bus masters * Arbitration through an AHB arbiter * Address decoding through an AHB decoder Table 2 lists the master and slave devices that connect to the AHB. Table 2: Master and Slave Devices on the AHB
AHB Masters MIPS 4Kc CPU PCI Ethernet Controller 1 Ethernet Controller 2 32-bit Master Interface to Programmable Fabric AHB Slaves System SRAM PCI Ethernet Controller 1 Ethernet Controller 2 32-bit Slave Interface to Programmable Fabric SDRAM and I/O Peripheral Controllers Interrupt Controller AHB to APB Bridge
The QL901M AHB supports multiple bus masters as well as bus slaves. Only one bus master can use the bus at a given time. The bus master provides address and control information when performing read and write operations. In response to the read or write operation from the bus master within a given address range, a bus slave provides information regarding the status of the data transfer (success, failure, or wait). The AHB arbiter ensures that only one bus master is initiating data transfers. The AHB decoder decodes the address of each transfer and provides a select signal for the slave that is involved in the transfer.
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QL901M QuickMIPSTM Data Sheet Rev. F
AHB Arbitration The internal arbiter of the QL901M employs fixed arbitration priority with preemption. Consequently, when a low priority master is in control of the bus and a higher priority master requests access, the lower priority device will lose its grant and then give up the bus after the next data transfer. This preemption only happens when the designated AHB master is performing bursts of undefined lengths. If the AHB master is performing a burst of a defined (fixed) length, the burst will complete without interruption and will not be interrupted by the arbiter. The priority of AHB masters is as follows (highest to lowest): 1. MIPS 4Kc CPU 2. Ethernet Controller 1 3. Ethernet Controller 2 4. PCI Controller 5. Programmable Fabric Advanced Peripheral Bus (APB) The APB is a simplified bus that is ideal for implementing device control registers and other non-burst transfers. The APB is a 32-bit wide bus that runs at the same frequency as AHB. The APB only accommodates slaves, does not support burst transfers, and does not support advanced slave response operations such as retries or wait state insertion. The APB on the QL901M is supported through an AHB-to-APB bridge. Three separately decoded APB regions are available for APB devices implemented in the Fabric. Table 3 lists the slave devices on the APB. Table 3: Slave Devices on the APB
APB Slaves Two UARTs Four 16-bit Timers/Counters Three 32-bit slave interfaces to Programmable Fabric
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QL901M QuickMIPSTM Data Sheet Rev. F
UARTs
The QL901M chip contains two UARTs. Each UART provides a full-duplex asynchronous receiver and transmitter and has programmable Baud rates. The UARTs contain an IrDA Serial Infrared (SIR) Encoder/ Decoder (ENDEC). One UART also has modem control signals. The serial output is software selectable between IrDA and generic serial modes. Figure 5 shows a block diagram of the UART. Figure 5: UART Block Diagram
Transmit FIFO System Bus Interface
Receive FIFO
Reveiver
Rx Data
Register Block
Baud Rate Generator
Transmitter Tx Data
System Clock FIFO Status / Interrupt Generation Interrupt
SIR ENDEC SIR Receive Decoder SIR Transmit Decoder
The key features of the UARTs are as follows: * Programmable Baud rate generation of up to 1/16 System Bus clock rate * FIFO enable or disable * 5, 6, 7, or 8 data bits * 1 or 2 stop bits * Odd and even, stick or no parity * Parity, framing, and overrun error detection * Line break generation and detection * Loopback * Interrupt generation
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QL901M QuickMIPSTM Data Sheet Rev. F
* IrDA SIR ENDEC block providing: Programmable use of IrDA SIR or UART input/output Support of IrDA SIR ENDEC functions for data rates up to 115.2 kilobits/second half-duplex Support of normal 3/16 and low-power (1.41 to 2.23s) bit durations Programmable internal clock generator allowing division of reference clock by 1 to 512 for low-power mode bit duration The System Bus (APB interface) generates read and write decodes for accesses to status/control registers and transmit/receive FIFO memories. The Register Block stores data written or to be read across the APB interface. The Baud Rate Generator contains free-running counters that generate a clock that is 16 times the transmit/receive bit rate. The transmit FIFO is an 8-bit wide, 16-entry deep FIFO memory buffer. CPU data written across the APB interface is stored in the FIFO until read out by the transmit logic. The transmit FIFO can be disabled to act like a one-byte holding register. The receive FIFO is a 12-bit wide, 16-entry deep FIFO memory buffer. Received data and corresponding error bits, are stored in the receive FIFO by the receive logic until read out by the CPU across the APB interface. The receive FIFO can be disabled to act like a one-byte holding register. The transmitter performs parallel-to-serial conversion on the data read from the transmit FIFO. Control logic outputs the serial bit stream beginning with a start bit, data bits, Least Significant Bit (LSB), a parity bit, and then stop bits according to the programmed configuration in control registers. The receiver performs serialto-parallel conversion on the received bitstream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line break detection are also performed, and the data with associated overrun, parity, framing, and break error bits is written to the receive FIFO. The Interrupt Generator outputs a single, combined interrupt to the QL901M Interrupt Controller. The SIR Transmit Encoder modulates the Non-Return-to-Zero (NRZ) transmit bitstream output from the QL901M chip. The IrDA SIR physical layer specifies use of a Return To Zero, Inverted (RZI) modulation scheme that represents logic 0 as an infrared light pulse. The modulated output pulse stream is transmitted to an external output driver and infrared Light Emitting Diode (LED). The SIR Receive Decoder demodulates the return-to-zero bit stream from the infrared detector and outputs the received NRZ serial bitstream to the QL901M UART received data input. The decoder input is normally HIGH (marking state) in the idle state. The transmit encoder output has the opposite polarity to the decoder input.
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QL901M QuickMIPSTM Data Sheet Rev. F
General Purpose 16-bit Timer/Counters
The QL901M chip has four independent 16-bit timer/counter modules. The configuration registers for these modules are accessible through the System Bus (APB). The System Bus clock (hclk), or an external clock supplied from the Fabric, drive the clock inputs on the timer/counter modules. These counters operate in one of four modes: decrement, increment, interval, or Pulse Width Modulation (PWM). Each timer/counter module has the capability to generate system interrupts on various events. One timer/counter is configured, by default, as a watchdog timer after a system reset. This watchdog timer has its own system interrupt output. Figure 6 shows a functional block diagram of the timer module. Figure 6: Timer Functional Block Diagram
Programmable ViaLink Fabric
System Bus tm_extclk[4:1] tm_overflow[4:2] tm_fbenable
ICU
7 Interrupts
32-bit MIPS 4Kc CPU 16K Dcache 16K Icache
Timer Int
WD Int
Control Registers
tm_enable
TM_ENABLE
Counter 4
3 4
Counter 3
Counter 2
Counter 1
tm_overflow[1]
TM_OVERFLOW
16-bit Timer/Counters
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QL901M QuickMIPSTM Data Sheet Rev. F
The key features of each timer/counter module are as follows: * Up to 66 MHz operation. * 32-bit data path on the System Bus. * 16-bit timer/counter. * 16-bit pre-scaler to increase timer/counter delay. * Four modes of operation: decrement, increment, interval and PWM. * Operation from the System Bus clock (hclk) or an external clock from the Fabric. * Two external hardware timer enable signals can be used to start/stop the timer/counter. One of these signals can be supplied from the Fabric and the other is a dedicated input pin on the chip. * Three match interrupts, one interval interrupt and one overflow interrupt. * Six control registers to control various counter functions, including enable/disable, load, and reset. The timer/counters are controlled by a set of control registers. Each timer/counter module has six control registers. By contrast, one interrupt register is used to control and convey the status of the interrupts from all the modules. One counter (Counter 4) is configured, by default, to be used as a watchdog timer after the system reset. This watchdog timer has its own system interrupt output, and it can be reconfigured by software for use as a standard timer/counter.
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QL901M QuickMIPSTM Data Sheet Rev. F
Fabric Side
This section discusses the various circuit elements in the Fabric portion of the QL901M device.
Logic Cells
The QL901M logic cell structure presented in Figure 7 is a dual register, multiplexor-based logic cell. It is designed for wide fan-in and multiple, simultaneous output functions. Both registers share CLK, SET, and RESET inputs. The second register has a two-to-one multiplexer controlling its input. The register can be loaded from the NZ output or directly from a dedicated input. NOTE: The input PP is not an "input" in the classical sense. It is a static input to the logic cell and selects which path (NZ or PS) is used as an input to the Q2Z register. All other inputs are dynamic and can be connected to multiple routing channels. The complete logic cell consists of two 6-input AND gates, four two-input AND gates, seven two-to-one multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell has a fan-in of 30 (including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six outputs (four combinatorial and two registered). The high logic capacity and fan-in of the logic cell accommodates many user functions with a single level of logic delay while other architectures require two or more levels of delay. Figure 7: QL901M LogicCell
QS A1 A2 A3 A4 A5 A6 OS OP B1 B2 C1 C2 MP MS D1 D2 E1 E2 NP NS F1 F2 F3 F4 F5 F6 PS PP QC QR
AZ
OZ
DQ
QZ
NZ
DQ
Q2Z
FZ
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QL901M QuickMIPSTM Data Sheet Rev. F
Dual-Port SRAM Modules
The QL901M includes 36 dual-port 2,304-bit RAM modules (shown in Figure 8) for implementing RAM, ROM, and FIFO functions. Each module is user-configurable into four different block organizations and can be cascaded vertically to increase their effective depth or horizontally to increase their effective width as shown in Figure 9. Figure 8: 2,304-bit RAM Module
MODE[1:0] WA[9:0] WD[17:0] WE WCLK ASYNCRD RA[9:0] RD[17:0] RE RCLK
2,304-bit Module
Using two mode pins, designers can configure each module into 128 x 18 (Mode 0), 256 x 9 (Mode1), 512 x 4 (Mode 2), or 1024 x 2 (Mode 3). Figure 9: Cascaded RAM Modules
WDATA WADDR
RAM Module (2,304 bits)
RDATA
RADDR
RAM Module (2,304 bits) WDATA RDATA
The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE ports support synchronous operation. Each port has 18 data lines and 10 address lines, allowing word lengths of up to 18 bits and address spaces of up to 1,024 words. Depending on the mode selected, however, some higher order data or address lines may not be used.
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QL901M QuickMIPSTM Data Sheet Rev. F
The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for asynchronous READ operation (ASYNCRD input high). Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. A similar technique can be used to create depths greater than 512 words. In this case address signals higher than the ninth bit are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals. The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with data from an external PROM (typically for ROM functions). Dual-Port SRAM Module Signals The dual-port RAM module signal descriptions are shown in Table 4. Table 4: Dual-Port RAM Module Signal Descriptions
Signal Name WCLK WE I/O I I Description Write Clock. Clock input for the write port of the RAM module. All write port input signals are synchronous with this clock. Write Enable. Sampled on the rising edge of WCLK, when WE is high, data is written into the RAM module at the specified write address. Write Address. Sampled on the rising edge of WCLK, this is the write address for the data to be written into the RAM module. WA(9:0) is ignored when WE is low. Note that some higher order bits of WA(9:0) may not be used depending on the selected mode for the RAM module (see MODE(1:0) signal description). Write Data. Sampled on the rising edge of WCLK, this is the data to be written into the RAM module. WD(17:0) is ignored when WE is low. Note that some higher order bits of WD(17:0) may not be used depending on the selected mode for the RAM module (see MODE(1:0) signal description). Read Clock. This is the clock input for the read port of the RAM module. If ASYNCRD is low, all read port I/O signals are synchronous with this clock. If ASYNCRD is high, RCLK is ignored. Read Enable. Sampled on the rising edge of RCLK, when RE is high, data is read from the RAM module at the specified read address. If ASYNCRD is high, this RE is ignored. Read Address. This is the read address for data to be read from the RAM module. If ASYNCRD is low, RA(9:0) is sampled only on the rising edge of RCLK while RE is high. If ASYNCRD is high, RA(9:0) is continuously sampled by the RAM module and RE has no effect. Note that some higher order bits of RA(9:0) may not be used depending on the selected mode for the RAM module (see MODE(1:0) signal description).
WA(9:0)
I
WD(17:0)
I
RCLK RE
I I
RA(9:0)
I
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 4: Dual-Port RAM Module Signal Descriptions (Continued)
Signal Name I/O Description Read Data. This is the read output data from the RAM module. If the RAM module is in synchronous read mode (ASYNCRD low), valid read data is output immediately following the rising edge of RCLK which sampled RE as high. If the RAM module is in asynchronous read mode (ASYNCRD high), valid read data is output immediately after any change in the read address. Note that some higher order bits of RD(17:0) may not be used depending on the selected mode for the RAM module (see MODE(1:0) signal description). Asynchronous Read Input. This signal, when high, indicates to the RAM block that the read port should operate asynchronously. When low, all read port I/O signals are synchronous with RCLK. This signal can only be tied to `1' or `0' inside the Fabric. Mode for RAM Module. These bits configure the width and depth of the RAM module (for both the read and write ports) and can only be tied to `1' or `0' inside the Fabric. The possible RAM module modes are: MODE(1:0) = "00" : 128 x 18 (locations x data bits) MODE(1:0) = "01" : 256 x 9 (locations x data bits) MODE(1:0) = "10" : 512 x 4 (locations x data bits) MODE(1:0) = "11" : 1024 x 2 (locations x data bits)
RD(17:0)
O
ASYNCRD
I
MODE(1:0)
I
Embedded Computational Units (ECUs)
Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively-- these functions require high logic cell usage while garnering only moderate performance results. The QL901M architecture allows for functionality above and beyond that achievable using programmable logic devices. By embedding a dynamically reconfigurable computational unit, the QL901M device can address various arithmetic functions efficiently. This approach offers greater performance than traditional programmable logic implementations. The embedded block is implemented at the transistor level as shown in Figure 10. Figure 10: ECU Block Diagram
S3 S2 S1 CIN SIGN2 SIGN1
A[15:8] A[7:0]
3-4 Decoder
D C B A
00 01 Q[16:0]
8-bit Multiplier
16-bit Adder
DQ
10
A[15:0] B[15:0]
CLK RESET
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QL901M QuickMIPSTM Data Sheet Rev. F
ECU Signals Table 5 defines the ECU I/O Signals. For more information on the operation of the ECU, see QuickLogic Application Note 52 at http://www.quicklogic.com/images/appnote52.pdf. Table 5: ECU I/O Signals
Signal Name CLK RESET S1 S2 S3 CIN SIGN1 SIGN2 A(15:0) I/O I I I I I I I I Description Clock Input. Input clock for the ECU output register. Reset Input. Active high reset input for the ECU output register. ECU Control S1. One of three instruction signals that define the configuration mode of the ECU (see Table 6). ECU Control S2. One of three instruction signals that define the configuration mode of the ECU (see Table 6). ECU Control S3. One of three instruction signals that define the configuration mode of the ECU (see Table 6). Carry Input. 1-bit Carry In for 16-bit adder operations. Sign Input for Multiplier A Input. When SIGN1 = `1', A(7:0) is treated as signed or two's complement binary. When SIGN1 = `0' A(7:0) is treated as unsigned binary. Sign Input for Multiplier B Input. When SIGN2 = `1', B(15:8) is treated as signed or two's complement binary. When SIGN2 = `0' B(15:8) is treated as unsigned binary. Augend Input. 16-bit augend input of the 16-bit adder when the ECU is in any of the adder configuration modes. I Multiplicand Input. 8-bit multiplicand input when the ECU is in any of the multiplier configuration modes. Multiplier Input. 8-bit multiplier input when the ECU is in any of the multiplier configuration modes. I O Addend Input. 16-bit addend input when ECU is in any of the adder configuration modes. ECU Output. This is the 17-bit output of the ECU. The interpretation of the value of Q(16:0) depends on the setting of S1, S2, S3, SIGN1, and SIGN2.
A(15:8)
A(7:0) B(15:0) Q(16:0)
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QL901M QuickMIPSTM Data Sheet Rev. F
The QL901M ECU blocks are placed next to the SRAM circuitry for efficient memory/instruction fetch and addressing for DSP algorithmic implementations. Up to eighteen 8-bit MAC functions can be implemented per cycle for a total of 1.8 billion MACs/s when clocked at 100 MHz. Additional multiply-accumulate functions can be implemented in the programmable logic. The instruction modes for the ECU block are dynamically re-programmable through the programmable logic as shown in Table 6. Table 6: ECU Mode Select Criteria
Instruction S1 0 0 0 0 1 1 1 1 S2 0 0 1 1 0 0 1 1 S3 0 1 0 1 0 1 0 1 Operation Multiply Multiply-Add Accumulate Add Multiply (registered)a Multiply- Add (registered) Multiply - Accumulate Add (registered)
a. B (15:0) set to zero.
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QL901M QuickMIPSTM Data Sheet Rev. F
Fabric PLLs
Instead of requiring extra components, designers simply need to instantiate one of the pre-configured models (described in this section). The QuickLogic built-in PLLs support a wider range of frequencies than many other PLLs. Also, QuickLogic PLLs can be cascaded to support different ranges of frequency multiplications or divisions, driving the device at a faster or slower rate than the incoming clock frequency. Most importantly, they achieve a very short clock-to-out time--generally less than 3 ns. This low clock-to-out time is achieved by the PLL subtracting the clock tree delay through the feedback path, effectively making the clock tree delay zero. The QL901M contains two fabric PLLs. PLL0 is in the upper left corner of the device (near the upper left quadrant) and PLL1 is in the upper right corner of the device (near the upper right quadrant). If a PLL is utilized, it must drive logic in its associated quadrant. The PLL can also drive the opposing quadrant as an option. The QuickWorks software handles PLL selection and placement of drive logic automatically. Designers also have the option to issue design constraints to QuickWorks, selecting specific PLLs and the location of driven logic. Figure 11 shows a block diagram of a QL901M PLL. Figure 11: PLL Block
Opposite Quadrant
PLL MUX 0
Clock Tree 1 '1' or '0'
PLL MUX FIN Frequency Divide _ .1 . . _2 . . _4 . + Filter vco 1 '1' PLL Bypass 0
Corresponding Quadrant
Clock Tree
Frequency Multiply .1 _ . . _2 . . _4 . FOUT
Fin represents a very stable high-frequency input clock and produces an accurate signal reference. This signal can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass through the PLL itself. Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external Fin signal and the local VCO form a control loop. The VCO is multiplied or divided down to the reference frequency, so that a phase detector (the crossed circle in Figure 11) can compare the two signals. If the phases of the external and local signals are not within the tolerance required, the phase detector sends a signal through the charge pump and loop filter (Figure 11). The charge pump generates an error voltage to bring the VCO back into alignment and the loop filter removes any high frequency noise before the error voltage enters the VCO. This new VCO signal enters the clock tree to drive the chip's circuitry.
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QL901M QuickMIPSTM Data Sheet Rev. F
Fout represents the clock signal that emerges from the output pad (the output signal PLLPAD_OUT is explained in Table 8). This clock signal is meaningful only when the PLL is configured for external use; otherwise, it remains in high Z state, as shown in the post-simulation waveform. For more specific information on the Phase Locked Loops, please refer to Application Note 58 at http://www.quicklogic.com/images/appnote58.pdf. Fabric PLL Modes of Operation QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output frequency-- Table 7 indicates the features of each mode. Table 7: PLL Mode Frequencies
PLL Model PLL_HF
b
Output Frequency Same as input frequency Same as input frequency 2 x input frequency 2 x input frequency 1/2 x input frequency 1/2 x input frequency 4 x input frequency 1/4 x input frequency
Input Frequency Rangea 66 MHz-150 MHz 25 MHz-133 MHz 50 MHz-125 MHz 16 MHz-50 MHz 100 MHz-250 MHz 50 MHz-100 MHz 16 MHz-40 MHz 100 MHz-300 MHz
Output Frequency Range 66 MHz-150 MHz 25 MHz-133 MHz 100 MHz-250 MHz 32 MHz-100 MHz 50 MHz-125 MHz 25 MHz-50 MHz 64 MHz-160 MHz 25 MHz-75 MHz
PLL_LF PLL_MULT2HF PLL_MULT2LF PLL_DIV2HF PLL_DIV2LF PLL_MULT4 PLL_DIV4
a. The input frequency can range from 12.5 MHz to 500 MHz, while output frequency ranges from 25 MHz to 250 MHz. When you add PLLs to your top-level design, be sure that the PLL mode matches your desired input and output frequencies. b. HF stands for high frequency and LF stands for low frequency.
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QL901M QuickMIPSTM Data Sheet Rev. F
Fabric PLL Signals Table 8 summarizes the key signals in QuickLogic PLLs. Table 8: PLL Signals
Signal Name PLLIN
a
Description Input clock signal Active High Reset If PLLRST is asserted, then CLKNET_OUT and PLLOUT are reset to 0. This signal must be asserted and then released in order for the LOCK_DETECT to work. PLL output This signal selects whether the PLL will drive the internal clock network or be used off-chip. This is a static signal, not a dynamic signal.
PLLRST
ONn_OFFCHIP
Tied to GND = outgoing signal drives internal gates. Tied to VCC = outgoing signal used off-chip.
CLKNET_OUT
Out to internal gates This signal bypasses the PLL logic before driving the internal gates. Note that this signal cannot be used in the same quadrant where the PLL signal is used (PLLCLK_OUT). Out from PLL to internal gates This signal can drive the internal gates after going through the PLL. For this to work, ONn_OFFCHIP must be tied to GND. Out to off-chip This outgoing signal is used off-chip. For this to work, ONn_OFFCHIP signal must be tied to VCC. Active High Lock detection signal NOTE: For simulation purposes, this signal gets asserted after 10 clock cycles. However, it can take a maximum of 200 clock cycles to sync with the input clock upon release of the RESET signal.
PLLCLK_OUT PLLOUT
LOCK_DETECT
a. Because PLLIN and PLLRST signals have INPAD, and PLLOUT has OUTPAD, you do not have to add additional pads to your design.
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QL901M QuickMIPSTM Data Sheet Rev. F
Advanced Clock Networks
The QL901M device has a large number of extremely advanced and highly flexible clock networks. These consist of three basic types of networks; a Global Network and a Dedicated Network (for low-skew applications), and an I/O Control/Hi-Drive Network (for high-fanout, multi-load applications). Global and Dedicated Low-Skew Networks The Global and Dedicated Networks are low-skew networks typically used to drive clock signals throughout the entire device. In addition, the Global Network can also be used to globally drive other high-fanout signals with low skew (e.g., flip-flop set or reset signals). Both networks are segmented, separated on a per-quadrant basis. (Unlike the QuickLogic Eclipse architecture, the QL901M has only two quadrants.) Figure 12 shows a simplified view of the low-skew clock network architecture in the QL901M device. Figure 12: Low Skew Clock Architecture
Upper Left Upper Right
Global and Dedicated Networks
CLK Pin
Table 9 shows the number of Global and Dedicated Networks available per quadrant in the QL901M. Table 9: Number of QL901M Low-Skew Clock Networks
Clock Network Type Global Dedicated Total Quadrant Upper Left 8 (5 are Quad-Nets) 1 9 Upper Right 8 (5 are Quad-Nets) 1 9 Total 16 2 18
As Table 9 shows, there are a total of nine low-skew networks per quadrant in the QL901M, making a total of eighteen in the entire device. Each quadrant contains eight Global Networks and one Dedicated Network.
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QL901M QuickMIPSTM Data Sheet Rev. F
The Global Network and Dedicated Network differ slightly in performance and flexibility. The Dedicated Network offers superb low-skew and minimal pin to logic element delay performance, but can only drive the clock inputs of specific Fabric elements. The Global Network offers more flexibility to drive a variety of inputs in the Fabric as well as internal ASSP port inputs, but at a slight increase in skew and delay. Table 10 outlines all allowable input destinations for each clock network type. Table 10: Allowable Inputs Destinations for Global and Dedicated Networks
Element Inputs That Can be Driven by the Global Clock Network QC A2 Logic Cells F1 QS QR WCLK RAM Modules RCLK RE WE ECUs CLK RESET IQC IQR I/O Cells EQE IQE IE ASSP Interface All Inputs IQC WCLK RCLK QC Inputs That Can be Driven by the Dedicated Clock Network
Each quadrant consists of an element called the PLLMUX that drives the Global Networks and the Dedicated Network in the quadrant. The PLLMUX selects between external CLK input pins and clock signals that are driven from other elements internal to the device such as the Fabric PLL and the ASSP System Bus clock (hclk). Figure 13 shows a simplified schematic diagram of the CLK input pins, the PLLMUX elements and the associated clock networks.
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QL901M QuickMIPSTM Data Sheet Rev. F
Figure 13: Low Skew Clock Structure Schematic Based Upon PLLMUX Elements (1 of 2 Quadrants)
PLL MUX hclk Logic Element CLK(2) Input Pin Global Clock Network
XX
tPGCK tBGCK
Global Clock Network
PLL MUX PLLCLK_OUT(1)
Logic Element CLK(3)/PLLIN(1) Input Pin
XX
tPGCK tBGCK
Global Clock Network
PLL MUX No Connection
Logic Element CLK(5) Input Pin
XX
tPGCK tBGCK
Dedicated Clock Network
PLL MUX PLLCLK_OUT(0)
Logic Element CLK(4)/DEDCLK/ PLLIN(0) Input Pin
XX
tPDEDCLK
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QL901M QuickMIPSTM Data Sheet Rev. F
If either of the Fabric PLL outputs or hclk are utilized in the corresponding quadrant of the Fabric design, the QuickWorks software automatically configures the corresponding PLLMUX to select the internal clock input. Each quadrant consists of four PLLMUX elements of which one input is tied to a specific CLK input pin as shown in Table 11. Table 11: PLLMUX Input Signals and Output Type (Per Quadrant)
Input Pin CLK(2) CLK(3) CLK(4)/DEDCLK CLK(5) Internal Signals hclk PLLCLK_OUT(1) PLLCLK_OUT(0) Output Type Global clock network Global clock network Dedicated clock network Global clock network
As Table 11 indicates, once a PLLMUX is used to drive an internal signal onto the Global or Dedicated Networks, the corresponding CLK input pin is blocked from entering that quadrant. NOTE: If either of the Fabric PLL outputs or hclk are utilized in the Fabric design, and external clock pins are also utilized, the designer should choose clock input pins on the device that do not conflict with these corresponding PLLMUX elements. Quad-Net Network (Subset of the Global Network) In each quadrant, the remaining five Global Networks are also referred to as Quad-Net Networks. Quad-Nets are networks that can be driven by input CLK pins or by signals that are generated internally to the Fabric. Quad-Nets are driven by an element in the Fabric called the HSCKMUX. Figure 14 shows a simplified schematic diagram of the CLK input pins, the HSCKMUX elements and the associated Quad-Net networks.
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QL901M QuickMIPSTM Data Sheet Rev. F
Figure 14: Low Skew Clock Structure Schematic Based Upon HSCKMUX Elements (1 of 2 Quadrants)
HSCKMUX Any Fabric Signal Logic Element CLK(0) Input Pin Global Clock Network (Quad-Net)
XX
tPGCK
HSCKMUX Any Fabric Signal Logic Element CLK(1) Input Pin
tBGCK
Global Clock Network (Quad-Net)
XX
tPGCK tBGCK
HSCKMUX Any Fabric Signal
Global Clock Network (Quad-Net)
Logic Element CLK(6) Input Pin
XX
tPGCK tBGCK
Global Clock Network (Quad-Net)
HSCKMUX Any Fabric Signal
Logic Element CLK(7) Input Pin
XX
tPGCK tBGCK
Global Clock Network (Quad-Net)
HSCKMUX Any Fabric Signal
Logic Element CLK(8) Input Pin
XX
tPGCK tBGCK
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QL901M QuickMIPSTM Data Sheet Rev. F
By instantiating the gclkbuff_25um macro with a given Fabric signal as its input, the designer can program an HSCKMUX to drive this signal on a Quad-Net (the QuickWorks tool automatically chooses which HSCKMUX to use). Each quadrant consists of five HSCKMUX elements of which one input is tied to a specific CLK input pin as shown in Table 12. Table 12: HSCKMUX Input Signals and Output Type (Per Quadrant)
Input Pin CLK(0) CLK(1) CLK(6) CLK(7) CLK(8) Internal Signals Any Signal Any Signal Any Signal Any Signal Any Signal Output Type Global clock network (Quad-Net) Global clock network (Quad-Net) Global clock network (Quad-Net) Global clock network (Quad-Net) Global clock network (Quad-Net)
As Table 12 indicates, once an HSCKMUX is used to drive an internal signal onto the Quad-Net Network, the corresponding CLK input pin is blocked from entering that quadrant. NOTE: If the sum of utilized clock input pins from Table 12 and the number of instantiated gclkbuff_25um macros is greater than five, the QuickWorks software may be unable to successfully resolve the conflicts between the CLK input pins and the internally generated clock input signals. This is dependant on several factors, but in most cases can be attributed to the size and complexity of the Fabric design. I/O Control/Hi-Drive Network The I/O Control/Hi-Drive Network is used primarily to drive high-fanout (typically other than clock or reset) signals throughout the device. Each bank of I/Os has two input-only pins entitled IOCTRL that can be programmed to drive the IQC (flip-flop clock), IQR (flip-flop reset), EQE & IQE (flip-flop enables), and IE (output enable) inputs of each I/O cell in that bank. These input-only pins also simultaneously serve as high drive inputs to any logic element input located in the adjacent quadrant. In addition, the I/O Control/Hi-Drive Network can be driven by the internal logic by instantiating the io_buff_25um macro. The QL901M has a total of eight IOCTRL input pins which are also shared with the io_buff_25um macros (i.e., if a io_buff_25um macro is utilized at a specific location, the corresponding IOCTRL input pin is ignored by the device. The performance of this network is presented in Table 32.
General Routing Network
QL901M devices are delivered with six types of routing resources as follows: short (sometimes called segmented) wires, dual wires, quad wires, express wires, distributed networks, and default wires. Short wires span the length of one logic cell, always in the vertical direction. Dual wires run horizontally and span the length of two logic cells. Short and dual wires are predominantly used for local connections. Default wires supply VCC and GND (Logic `1' and Logic `0') to each column of logic cells. Quad wires have passive link interconnect elements every fourth logic cell. As a result, these wires are typically used to implement intermediate length or medium fan-out nets. Express lines run the length of the programmable logic uninterrupted. Each of these lines has a higher capacitance than a quad, dual, or short wire, but less capacitance than shorter wires connected to run the length of the device. The resistance will also be lower because the express wires don't require the use of "pass" links. Express wires provide higher performance for long routes or high fan-out nets.
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QL901M QuickMIPSTM Data Sheet Rev. F
Distributed networks are described in Advanced Clock Networks on page 24. These wires span the programmable logic and are driven by "column clock" buffers. All clock network pin buffers (both Dedicated and Global) are hard wired to individual sets of column clock buffers.
Programmable I/O
The QL901M features a variety of distinct I/O pins to maximize performance, functionality, and flexibility with bi-directional I/O pins and input-only pins. All input and I/O pins are 2.5 V and 3.3 V compliant and comply with the specific I/O standard selected. For single-ended I/O standards, VCCIO(A:D) specifies the input tolerance and the output drive. For example, the VCCIO(A:D) pins must be tied to a 3.3 V supply to provide 3.3 V compliance. For voltage referenced I/O standards (e.g, SSTL), the voltage supplied to the INREF(A:D) pins in each bank specifies the input switch point. The QL901M can also support the LVDS and LVPECL I/O standards with the use of external resistors (see Table 13). Table 13: I/O Standards and Applications
I/O Standard LVTTL LVCMOS25 PCI GTL+ SSTL3 SSTL2 Reference Voltage n/a n/a n/a 1 1.5 1.25 Output Voltage 3.3 V 2.5 V 3.3 V n/a 3.3 V 2.5 V Application General Purpose General Purpose PCI Bus Applications Backplane SDRAM SDRAM
As designs become more complex and requirements more stringent, several application-specific I/O standards have emerged for specific applications. I/O standards for processors, memories, and a variety of bus applications have become commonplace and a requirement for many systems. In addition, I/O timing has become a greater issue with specific requirements for setup, hold, clock to out, and switching times. The QL901M has addressed these new system requirements and includes a new I/O cell which consists of programmable I/Os as well as a new cell structure consisting of three registers--Input, Output, and OE. The bi-directional I/O pin options can be programmed for input, output, or bi-directional operation. As shown in Figure 15, each bi-directional I/O pin is associated with an I/O cell which features an input register, an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one output multiplexers. The select lines of the two-to-one multiplexers are static and must be connected to either Vcc or GND.
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QL901M QuickMIPSTM Data Sheet Rev. F
Figure 15: QL901M I/O Cell
IZ IQE INPUT REGISTER IQQ
+
Q E R D
>
OSEL OQQ
OUTPUT REGISTER
OQI
PAD
D
Q R
IP
>
ESEL EQE OUTPUT ENABLE REGISTER IE
D
E R
Q
IQR IQC
>
For input functions, I/O pins can provide combinatorial, registered data, or both options simultaneously to the logic array. For combinatorial input operation, data is routed from I/O pins through the input buffer to the array logic. For registered input operation, I/O pins drive the D input of the input registers, allowing data to be captured with fast set-up times without consuming internal logic cell resources. The comparator and multiplexor in the input path allows for native support of I/O standards with reference points offset from traditional ground. For output functions, I/O pins can receive combinatorial or registered data from the logic array. For combinatorial output operation, data is routed from the logic array through a multiplexer to the I/O pin. For registered output operation, the array logic drives the D input of the output register which in turn drives the I/O pin through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be driven to the I/O pin. Using the output register will also decrease the Tco. Since the output register does not need to drive the routing the length of the output path is also reduced. The three-state output buffer controls the flow of data from the array logic to the I/O pin and allows the I/O pin to act as an input and/or output. The buffer's output enable can be individually controlled by the logic cell array or any pin (through the regular routing resources), or it can be bank-controlled through one of the global networks. The signal can also be either combinatorial or registered. This is identical to that of the flow for the output register. For combinatorial control operation data is routed from the logic array through a multiplexer to the three-state control. The IOCTRL pins can directly drive the OE and CLK signals for all I/O cells within the same bank. For registered control operation, the array logic drives the D input of the OE register which in turn drives the three-state control through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be driven to the three-state control. When I/O pins are unused, the OE controls can be permanently disabled, allowing the output register to be used for registered feedback into the logic array.
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QL901M QuickMIPSTM Data Sheet Rev. F
I/O cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular routing resources, from one of the global networks, or from two IOCTRL input pins per bank of I/Os. The CLK and RESET signals share common lines, while the clock enables for each register can be independently controlled. I/O interface support is programmable on a per bank basis. The QL901M contains four I/O banks. Figure 16 illustrates the I/O bank configurations. Each I/O bank is independent of other I/O banks and each I/O bank has its own VCCIO and INREF supply inputs. A mixture of different I/O standards can be used on the device; however, there is a limitation as to which I/O standards can be supported within a given bank. Only standards that share a common VCCIO and INREF can be shared within the same bank (e.g., PCI and LVTTL). Figure 16: Multiple I/O Banks
VCCIO(C) IOCTRL(C) INREF(C) VCCIO(B) IOCTRL(B) INREF(B)
VCCIO(D)
PLL
Embedded RAM Blocks Embeded Computational Units
PLL
VCCIO(A)
IOCTRL(D)
IOCTRL(A)
Fabric
INREF(D) INREF(A)
Embedded RAM Blocks
ASSP
Programmable Slew Rate Each I/O has programmable slew rate capability--the slew rate can be either fast or slow. The slower rate can be used to reduce the switching noise of each I/O. See Table 38 and Table 39 for specific information on the slew rates for the Fabric I/O pins. The option to change the slew rate is selectable through QuickWorks in the Tools/Configure Pins window in SpDE. Programmable Weak Pull-Down A programmable Weak Pull-Down resistor is available on each I/O. The I/O Weak Pull-Down eliminates the need for external pull down resistors for used I/Os. The spec for pull-down current is maximum of 150 A under worst case conditions. The option to use the programmable weak pull-down resistor is selectable through QuickWorks in the Tools/Configure Pins window in SpDE.
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QL901M QuickMIPSTM Data Sheet Rev. F
Figure 17: Programmable I/O Weak Pull-Down
PAD I/O Output Logic
Global Power-On Reset (POR)
The QL901M family of devices features a global power-on reset. This reset is hardwired to all registers and resets them to Logic `0' upon power-up of the device. In QuickLogic devices, the asynchronous Reset input to flip-flops has priority over the Set input; therefore, the Global POR will reset all flip-flops during power-up. If you want to set the flip-flops to Logic `1', you must assert the "Set" signal after the Global POR signal has been deasserted. This is accomplished by holding the "Set" signal high for at least 1 ms after the VCC supply has reached 2.5 V. Figure 18: Power-On Reset
VCC
Power-on Reset
Q
XXXXXXXXXXXX
0
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QL901M QuickMIPSTM Data Sheet Rev. F
Joint Test Access Group (JTAG)
Figure 19: JTAG Block Diagram
TCK TMS TRSTB
Tap Controller State Machine (16 States)
Instruction Decode & Control Logic
Instruction Register
RDI
Mux Boundary-Scan Register (Data Register)
Mux
TDO
Bypass Register
Internal Register
I/O Registers
User Defined Data Register
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, one problem being the accessibility of test points. JTAG formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) Controller works in concert with the Instruction Register (IR), which allow users to run three required tests along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. The 1149.1 standard requires the following three tests: * Extest Instruction. The Extest instruction performs a PCB interconnect test. This test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAPs Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (through the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction. This instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed through a data scan operation, allowing users to sample the functional data entering and leaving the device.
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QL901M QuickMIPSTM Data Sheet Rev. F
* Bypass Instruction. The Bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device. JTAG BSDL Support * BSDL-Boundary Scan Description Language * Machine-readable data for test equipment to generate testing vectors and software * BSDL files available for all device/ package combinations from QuickLogic * Extensive industry support available and ATVG (Automatic Test Vector Generation) Security Fuses There are two security links: one to disable reading logic from the array, and the second to disable JTAG access to the device. Programming these optional links completely disables access to the device from the outside world and provides an extra level of design security not possible in SRAM-based FPGAs. The option to program these fuses is selectable through QuickWorks in the Tools/Options/Device Programming window in SpDE. Flexibility Fuse The flexibility link enables Power-Up loading of the Embedded RAM blocks. If the link is programmed, the Power Up Loading state machine is activated during power-up of the device. The state machine communicates with an external EPROM through the JTAG pins to download memory contents into the on-chip RAM. If the link is not programmed, Power-Up Loading is not enabled and the JTAG pins function as they normally would. The option to program this bit is selectable through QuickWorks in the Tools/Options/Device Programming window in SpDE. For more information on Power-Up Loading refer to QuickLogic Application Note 55 at http://www.quicklogic.com/images/appnote55.pdf. NOTE: All JTAG inputs are clamped to the VCC rail, not VCCIO. Therefore, these pins can only be driven up to VCC + 0.3 V. These input pins are LVCMOS2 compliant only (2.5 V). All JTAG outputs are driven by the VCC rail, not VCCIO. Therefore, these output pins can only drive up to VCC. These output pins are LVCMOS2 compliant only (2.5 V).
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QL901M QuickMIPSTM Data Sheet Rev. F
Electrical Specifications
DC Characteristics
The DC Specifications are provided in Table 14 through Table 18. Table 14: Absolute Maximum Ratings
Parameter VCC Voltage VCCIO(A:D) Voltage INREF(A:D) Voltage Input Voltage Latch-up Immunity Value -0.5 V to 3.6 V -0.5 V to 4.6 V 2.7 V -0.5 V to VCCIO(A:D) + 0.5 V 100 mA Parameter DC Input Current ESD Pad Protection BGA Package Storage Temperature VCCIO Voltage Value 20 mA 2000 V -55 C to +125 C -0.5 V to 4.0 V
Table 15: Operating Range
Symbol VCC VCCIO VCCIO(A:D) TC K Parameter Supply Voltage for QL901M ASSP I/O Supply Voltage for QL901M Fabric I/O Bank Reference Voltages Case Temperature Delay Factor 100 MHz Speed Grade 133 MHz Speed Grade Industrial Min. 2.3 3.0 2.3 -40 0.43 0.46 Max. 2.7 3.6 3.6 85 1.80 1.26 Commercial Min. 2.3 3.0 2.3 0 0.46 0.46 Max. 2.7 3.6 3.6 70 1.76 1.23 V V V C n/a n/a Unit
Table 16: DC Characteristics
Symbol ICC Parameter D.C. Supply Current Conditions VI, VO = VCCIO, VCCIO(A:D) or GND Min. Max. TBD Units mA
Table 17: Fabric I/O DC Characteristics
Symbol II IOZ CI CCLOCK IOS Parameter I or I/O Input Leakage Current 3-State Output Leakage Current I/O Input Capacitance
a a
Conditions VI = VCCIO(A:D) or GND VI = VCCIO(A:D) or GND Vo = GND Vo = VCCIO(A:D)
Min. -10 -15 40
Max. 10 10 8 12 -180 210
Units A A pF pF mA mA
Clock Input Capacitance
Output Short Circuit Currentb
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 17: Fabric I/O DC Characteristics (Continued)
Symbol IREF IPD ICCIO Parameter D.C. Supply Current on INREF(A:D) Current on programmable Pull-down D.C. Supply Current on VCCIO(A:D) Conditions VCCIO(A:D) = 3.6 V VCCIO(A:D) = 2.5 V VCCIO(A:D) = 3.6 V VCCIO(A:D) = 2.5 V Min. -10 Max. 10 150 2 Units A A mA
a. Capacitance is sample tested only. b. Only one output at a time. Duration should not exceed 30 seconds.
Table 18: Fabric DC Input and Output Levelsa
INREF VMIN VMAX VMIN LVTTL LVCMOS2 GTL+ PCI SSTL2 SSTL3 n/a n/a n/a n/a -0.3 -0.3 VIL VMAX 0.8 0.7 INREF(A:D) - 0.2 VMIN 2.2 1.7 INREF(A:D) + 0.2 VIH VMAX VCCIO(A:D) + 0.3 VCCIO(A:D) + 0.3 VCCIO(A:D) + 0.3 VCCIO(A:D) + 0.5 VCCIO(A:D) + 0.3 VCCIO(A:D) + 0.3 VOL VMAX 0.4 0.7 0.6 VOH VMIN 2.4 1.7 n/a IOL IOH mA mA 2.0 -2.0 2.0 -2.0 40 n/a
0.88 1.12 -0.3 n/a n/a -0.3
0.3 x 0.5 x VCCIO(A:D) VCCIO(A:D) INREF(A:D) - 0.18 INREF(A:D) - 0.2 INREF(A:D) + 0.18 INREF(A:D) + 0.2
0.1 x 0.9 x 1.5 -0.5 VCCIO(A:D) VCCIO(A:D) 0.74 1.10 1.76 1.90 7.6 -7.6 8 -8
1.15 1.35 -0.3 1.3 1.7 -0.3
a. The data provided in Table 18 are JEDEC and PCI Specifications. QuickLogic devices either meet or exceed these requirements.
NOTE: All CLK, DEDCLK, PLLIN, PLLRST, and IOCTRL input pins are clamped to the VCC rail. Therefore, these pains can be driven up to VCC+0.3 V.
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QL901M QuickMIPSTM Data Sheet Rev. F
AC Characteristics
The AC Specifications in this section are shown at VCC = 1.8 V, TA = 25 C, Worst Case Corner, Fabric Speed Grade = -6 (-6 Fabric Speed Grade = 133 MHz CPU Speed, K = 1.07) unless otherwise indicated.
ASSP PLL
Table 19: ASSP PLL Timing Parameters
Jitter <200ps Standby Current (A) 157 A Frequency Range 40-66.6 MHz Minimum Lock Frequency 25 MHz Duty Cycle 60/40 Crystal Accuracy 200 PPM Lock Time 10 s
SDRAM Controller
Figure 20: SDRAM Waveforms SD_CLKIN Tco_sdram ADDR[23:0] SD_CS_n[3:0] SD_CKE[3:0] SD_DQM[3:0] SD_RAS_n SD_CAS_n SD_WE_n DATA(output)[31:0] Tsu_sdram DATA(input[31:0] Th_sdram
Table 20: SDRAM AC Timing Parametera Tco Tsu Th DATA, ADDR, SD_RAS_n, SD_CAS_n, SD_CS_n[3:0], SD_DQM[3:0], SD_WE_n, SD_CKE[3:0] DATA DATA 100 MHz Min 2 12 2 Max 8 133 MHz Min 2 9 2 Max 6 Units ns ns ns
a. All timing is measured with respect to the rising edge of SD_CLKIN. All measurements are based on I/Os with 35 pF load except for SD_CLKOUT, which has a load of 15 pF.
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QL901M QuickMIPSTM Data Sheet Rev. F
I/O Peripheral Controller
Figure 21: SRAM Read Waveforms
Internal_AHB_Clock CS_n ADDR[31:0] BLS_n[3:0] OEN_n WEN_n D0 D1 DATA[31:0] read data addr byte lane select
Table 21: SRAM AC Read Timing Requirements
Parameter D0 D1 Access time, address and byte lane output to read data valida Access time, output enable to read data valid 100 MHz Min. Max. TBD TBD 133 MHz Min. Max. TBD TBD Units ns ns
a. Measurement is based on SD_CLKIN feedback with 0 ns delay and SD_CLKOUT load of 15 pF. Allowed access time will be decreased by SD_CLKIN to SD_CLKOUT delay.
Figure 22: SRAM Write Waveforms
Internal_AHB_Clock CS_n ADDR[31:0] BLS_n[3:0] OEN_n D0 D1 WEN_n DATA[31:0] write data addr byte lane select
Table 22: SRAM AC Write Timing Characteristics
Parameter D0 D1 Write enable low pulse width Write output data valid before rising edge of write enablea 100 MHz Min. TBD TBD Max. 133 MHz Min. TBD TBD Max. Units hclk period ns
a. Measurement is based on SD_CLKIN feedback with 0 ns delay and SD_CLKOUT load of 15 pf. Setup time will be decreased by SD_CLKIN to SD_CLKOUT delay.
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QL901M QuickMIPSTM Data Sheet Rev. F
PCI Controller
Figure 23: PCI Waveforms
PCI_CLK Tval PCI_AD(output)[31:0] PCI_C_BE_n(output)[3:0] PCI_PAR(output) PCI_FRAME_n(output) PCI_IRDY_n(output) PCI_TRDY_n(output) PCI_STOP_n(output) PCI_DEVSEL_n(output) PCI_SERR_n PCI_PERR_n(output) Tval(ptp) PCI_REQ_n Tsu PCI_AD(input)[31:0] PCI_C_BE_n(input)[3:0] PCI_PAR(input) PCI_FRAME_n(input) PCI_IRDY_n(input) PCI_TRDY_n(input) PCI_STOP_n(input) PCI_DEVSEL_n(input) PCI_IDSEL PCI_PERR_n(input) PCI_LOCK_n Tsu(ptp) PCI_GNT_n Th
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 23: PCI AC Timing
Parametera tCYC tHIGH tLOW - tVAL tVAL (PTP) tON tOFF tSU tSU (PTP) tH tRST tRST-CLK PCI_CLK Cycle Time PCI_CLK High Time PCI_CLK Low Time PCI_CLK Slew Rate PCI_CLK to Signal Valid Delay PCI_CLK to Signal Valid Delay point-to-point signalsb Float to Active Delay Active to Float Delay Input Setup Time to PCI_CLK bused signals Input Setup Time to PCI_CLK point-to-point Input Hold Time from PCI_CLK Reset Active Time after power stable Reset Active Time after PCI_CLK stable PCI_RST_n high to first configuration access PCI_RST_n high to first PCI_FRAME_n assertion 66 MHz Min. 15 6 6 1.5 2 2 2 3 5 0 1 100 Max. 4 6 6 14 40 2 5 2 5 Min. 30 11 11 1 2 2 2 7 10, 12 0 1 100 33 MHz Max. 4 11 12 28 40 Units ns ns ns V/ns ns ns ns ns ns ns ns ms
s
ns clocks clocks
tRST-OFFc Reset Active to output float delay tRHFA tRHFF
a. All PCI pins are synchronous to the PCI clock except for PCI_RST_n and PCI_INTA_n. b. Point-to-point signals include PCI_REQ_n and PCI_GNT_n. c. All output drivers must be 3-stated when PCI_RST_n is active.
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QL901M QuickMIPSTM Data Sheet Rev. F
Ethernet Controllers
Figure 24: Ethernet MAC Transmit Interface Waveforms
t EN_C2Q t DATA_H tDATA_V
Table 24: Ethernet MAC Transmit Interface AC Timing
Parameter tEN_C2Q tDATA_V tDATA_H Time from the rising clock edge of TXCLK to the change in TXEN Time from the rising clock edge of TXCLK to all data signals having valid stable values Time in which the output data is still valid after the rising clock edge of TXCLK Min. 0.0 Max. 8.0 9.0 Units ns ns ns
Figure 25: Ethernet MAC Receive Interface Waveforms
tDV_H t ER_H tDATA_S
t DV_S t ER_S tDATA_H
Table 25: Ethernet MAC Receive Interface AC Timing
Parameter tDV_S tDV_H tER_S tER_H tDATA_S tDATA_H RXDV (receive data valid) to RXCLK setup time RXDV (receive data valid) from RXCLK hold time RXER (receive data error) to RXCLK setup time RXER (receive data error) from RXCLK hold time RXD (receive data) to RXCLK setup time RXD (receive data) from RXCLK hold time Min. 2.0 2.0 2.0 2.0 2.0 2.0 Max. Units ns ns ns ns ns ns
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QL901M QuickMIPSTM Data Sheet Rev. F
The timing of the MII Management Interface listed below depends on the system clock frequency. The numbers displayed are correct for a processor clock frequency of 100 MHz and an AMBA bus system clock frequency of 50 MHz. Note that for a system clock of 133 MHz, the mandatory MDC minimum clock cycle of 400 ns for some PHY devices will not be met. Figure 26: MII Management Interface Waveforms (1 of 2)
t MDC_CYC tMDC_H t MDC_L
tMDOZV
tMDOVH
t MDOVS
t MDOVZ
Table 26: MII Management Interface AC Timing (1 of 2)
Parameter tMDC_CYC tMDC_H tMDC_L tMDOZV tMDOVZ tMDOS tMDOVH MDC cycle time MDC high time MDC low time MDIO output high impedance to valid time from rising edge of MDC MDIO output valid to high impedance time from rising edge of MDC MDIO output valid before MDC rising edge MDIO output valid from MDC rising edge Min. 520 260 260 40 40 440 40 Max. Units ns ns ns ns ns ns ns
Figure 27: MII Management Interface Waveforms (2 of 2)
tMDIS
tMDIH
Table 27: MII Management Interface AC Timing (2 of 2)
Parameter tMDIS tMDIH MDIO setup time to MDC MDIO hold time to MDC Min. 25 0 Max. Units ns ns
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QL901M QuickMIPSTM Data Sheet Rev. F
Logic Cells
Figure 28: QL901M Logic Cell
QS A1 A2 A3 A4 A5 A6 OS OP B1 B2 C1 C2 MP MS D1 D2 E1 E2 NP NS F1 F2 F3 F4 F5 F6 PS PP QC QR
AZ
OZ
DQ
QZ
NZ
DQ
Q2Z
FZ
Figure 29: Logic Cell Flip-Flop
SET D CLK RESET Q
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QL901M QuickMIPSTM Data Sheet Rev. F
Figure 30: Logic Cell Flip-Flop Timings--First Waveform
CLK tCWHI (min) SET tCWLO (min)
RESET
Q tRESET tRW tSET
tSW
Figure 31: Logic Cell Flip-Flop Timings--Second Waveform
CLK
D
tSU
tHL
Q tCO
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 28: Logic Cells
Symbol Logic Cells tPD tSU tHL tCO tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay of the longest path: time taken by the combinatorial circuit to output Setup time: time the synchronous input of the flip-flop must be stable before the active clock edge Hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Clock-to-out delay: the amount of time taken by the flip-flop to output after the active clock edge. Clock High Time: required minimum time the clock stays high Clock Low Time: required minimum time that the clock stays low Set Delay: time between when the flip-flop is "set" (high and when the output is consequently "set" (high) Reset Delay: time between when the flip-flop is "reset" (low) and when the output is consequently "reset" (low) Set Width: time that the SET signal must remain high/low Reset Width: time that the RESET signal must remain high/low Value Min. 0.205 0.231 0 0.46 0.46 0.3 0.3 Max. 1.01 0.427 0.585 0.658 -
Dual-Port SRAM Modules
Figure 32: RAM Module
[9:0] [17:0]
WA WD WE WC LK
RE R C LK RA RD AS Y NC R D R AM Module [9:0] [17:0]
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QL901M QuickMIPSTM Data Sheet Rev. F
Figure 33: RAM Cell Synchronous Write Timing
WCLK
WA tSWA WD tSWD WE tSWE RD old data tWCRD tHWE new data tHWD tHWA
Table 29: RAM Cell Synchronous Write Timing
Symbol RAM Cell Synchronous Write Timing tSWA tHWA tSWD tHWD tSWE tHWE tWCRD WA setup time to WCLK: time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK WD setup time to WCLK: time the WRITE DATA must be stable before the active edge of the WRITE CLOCK WD hold time to WCLK: time the WRITE DATA must be stable after the active edge of the WRITE CLOCK WE setup time to WCLK: time the WRITE ENABLE must be stable before the active edge of the WRITE CLOCK WE hold time to WCLK: time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the time when the data is available at RD 0.675 ns 0 ns 0.654 ns 0 ns 0.276 ns 0 ns 2.796 ns Parameter Value Min. Max.
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QL901M QuickMIPSTM Data Sheet Rev. F
Figure 34: RAM Cell Synchronous and Asynchronous Read Timing
RCLK
RA
tSRA tHRA
RE
tSRE tHRE
new data
RD
old data
tRCRD rPDRD
Table 30: RAM Cell Synchronous and Asynchronous Read Timing
Symbol RAM Cell Synchronous Read Timing tSRA tHRA tSRE tHRE tRCRD RA setup time to RCLK: time the READ ADDRESS must be stable before the active edge of the READ CLOCK RA hold time to RCLK: time the READ ADDRESS must be stable after the active edge of the READ CLOCK RE setup time to WCLK: time the READ ENABLE must be stable before the active edge of the READ CLOCK RE hold time to WCLK: time the READ ENABLE must be stable after the active edge of the READ CLOCK RCLK to RD: time between the active READ CLOCK edge and the time when the data is available at RD RA to RD: time between when the READ ADDRESS is input and when the DATA is output 0.686 ns 0 ns 0.243 ns 0 ns 2.225 ns Parameter Value Min. Max.
RAM Cell Asynchronous Read Timing rPDRD 2.405 ns
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QL901M QuickMIPSTM Data Sheet Rev. F
ECUs
Figure 35: ECU Block Diagram
S3 S2 S1 CIN SIGN2 SIGN1
A[15:8] A[7:0]
3-4 Decoder
D C B A
00 01 Q[16:0]
8-bit Multiplier
16-bit Adder
DQ
10
A[15:0] B[15:0]
CLK RESET
Table 31: ECU Mode Select Criteria
Instruction S1 0 0 0 0 1 1 1 1 A2 0 0 1 1 0 0 1 1 S3 0 1 0 1 0 1 0 1 Operation Multiply Multiply-Add Accumulateb Add Multiply (registered)
c
ECU Performancea, -6 WCC tPD 6.6 ns max. 8.8 ns max. 3.1 ns max. tSU 3.9 ns min. 9.6 ns min. 9.6 ns min. 9.6 ns min. 3.9 ns min. tCO 1.2 ns max. 1.2 ns max. 1.2 ns max. 1.2 ns max. 1.2 ns max.
Multiply-Add (registered) Multiply-Accumulate Add (registered)
a. tPD, tSU, and tCO do not include routing paths in/out of the ECU block. b. Internal feedback path in ECU restricts max. clk frequency to 238 MHz. c. B (15:0) set to zero.
NOTE: Timing numbers in Table 31 represent -6 Worst Case Commercial conditions.
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QL901M QuickMIPSTM Data Sheet Rev. F
Clock Network
Table 32: I/O Control Network/Local High-Drive
Destination I/O (far) I/O (near) Skew From Pad (max.) 1.00 ns 0.63 ns 0.37 ns From Array (max.) 1.14 ns 0.78 ns 0.36 ns
Figure 36: Dedicated Clock Structure Schematic
Dedicated Clock Network
PLL MUX PLLCLK_OUT(0)
Logic Element CLK(4)/DEDCLK/ PLLIN(0) Input Pin
XX
tPDEDCLK
Table 33: Dedicated Clock Network Performance
Symbol tPDEDCLK tSKEWDEDCLK Parameters Delay from dedicated clock input pin to logic cell flip-flop Skew on dedicated clock network Value Min. Max. 1.73 ns TBD ns
NOTE: When using the Fabric PLL, tPDEDCLK is effectively zero due to delay adjustment by PLL.
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QL901M QuickMIPSTM Data Sheet Rev. F
Figure 37: Global Clock Structure Schematic
Global Clock Network
Internal Signal Logic Element CLK Input Pin
XX
tPGCK tBGCK
Table 34: Global Clock Network Performance
Symbol tPGCK tBGCK tSKEWGCK Parameter Global clock pin delay to quad net Global clock tree delay (quad net to logic cell flip-flop) Skew on global clock network Value Min. Max. 1.34 ns 0.56 ns TBD ns
NOTE: When using the Fabric PLL, tPGCK and tBGCK are effectively zero due to delay adjustment by PLL.
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QL901M QuickMIPSTM Data Sheet Rev. F
I/O Cells
Figure 38: QL901M Input Register Cell
tISU + tSID
QE R D
PAD
Table 35: Standard Input Delays
Symbol Standard Input Delays tSID (LVTTL) tSID (LVCMOS2) tSID (GTL+) tSID (SSTL3) tSID (SSTL2) Parameter To get the total input delay add this delay to tISUa LVTTL input delay: Low Voltage TTL for 3.3 V applications LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower applications GTL+ input delay: Gunning Transceiver Logic SSTL3 input delay: Stub Series Terminated Logic for 3.3 V SSTL2 input delay: Stub Series Terminated Logic for 2.5 V Min. Value Max. 0.34 ns 0.42 ns 0.68 ns 0.55 ns 0.61 ns
a. See Table 36 for tISU value.
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QL901M QuickMIPSTM Data Sheet Rev. F
Figure 39: QL901M Input Register Cell Timing
R
CLK
D
tIS U tIH L
Q
tIC O tIR S T
E
tIE S U tIE H
Table 36: Input Register Cell
Symbol Input Register Cell Only tISU tIHL tICO tIRST tIESU tIEH Input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge. Input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge. Input register clock-to-out: time taken by the flip-flop to output after the active clock edge. Input register reset delay: time between when the flip-flop is "reset"(low) and when the output is consequently "reset" (low). Input register clock enable setup time: time "enable" must be stable before the active clock edge. Input register clock enable hold time: time "enable" must be stable after the active clock edge. 3.308 ns 0 ns 0.830 ns 0 ns 3.526 ns 0.494 ns 0.464 ns 0.987 ns Parameter Value Min. Max.
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QL901M QuickMIPSTM Data Sheet Rev. F
Figure 40: QL901M Output Register Cell
PAD OUTPUT REGISTER
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QL901M QuickMIPSTM Data Sheet Rev. F
Figure 41: QL901M Output Register Cell Timing
H L H Z L H Z L
tOUTLH
H L H tPZH Z L H Z L
tOUTHL
tPZL tPHZ
tPLZ
Table 37: Output Register Cell
Symbol Output Register Cell Only tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ tCOP Output Delay low to high (90% of H) Output Delay high to low (10% of L) Output Delay tri-state to high (90% of H) Output Delay tri-state to low (10% of L) Output Delay high to tri-state Output Delay low to tri-state Clock-to-out delay: time taken by the flip-flop to output after the active clock edge. (Does not include clock tree delays.) 0.40 ns 0.55 ns 2.94 ns 2.34 ns 3.07 ns 2.53 ns 3.15 ns (fast slew) 10.2 ns (slow slew) Parameter Value Min. Max.
Table 38: Fabric Output Slew Rates @ VCCIO(A:D) = 3.3 V, 25 C
Fast Slew Rising Edge Falling Edge 2.8 V/ns 2.86 V/ns Slow Slew 1.0 V/ns 1.0 V/ns
Table 39: Fabric Output Slew Rates @ VCCIO(A:D) = 2.5 V, 25 C
Fast Slew Rising Edge Falling Edge 1.7 V/ns 1.9 V/ns Slow Slew 0.6 V/ns 0.6 V/ns
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QL901M QuickMIPSTM Data Sheet Rev. F
ASSP to Fabric Timing
Table 40 and Table 41 list the synchronous and asynchronous timing for the QL901M ASSP to Fabric interface ports and ASSP I/O pins. Note the following regarding the Fabric timing: * * * * fb_int is asynchronous and is synchronized inside the core. fb_bigendian is a static signal and reflects the value on the CPU_BIGENDIAN pin. pm_* and si_* signals are synchronous to the internal MIPS clock which is twice the hclk frequency. This internal clock is not driven to the Fabric. All AF_PCI_* signals are static.
Table 40: 100MHz and 133MHz QuickMIPS Interface Port Synchronous Timing (to hclk)
100MHz Signal Name hresetn Fabric AHB Slave Ports ahbs_hsel ahbs_haddr ahbs_htrans ahbs_hwrite ahbs_hsize ahbs_hburst ahbs_hprot ahbs_hwdata ahbs_hrdata ahbs_hready_out ahbs_hresp Fabric AHB Master Ports ahbm_haddr ahbm_htrans ahbm_hwrite ahbm_hsize ahbm_hburst ahbm_hprot
b
133MHz Setup Time (Tsu) X X X X X X X X X 4.47 7.18 7.81 8.98 8.52 7.81 7.96 8.11 - 7.81 X X X 5.56 X X X X X X X X X 0 0 0 0 0 0 0 0 - 0 X X X 0 X Hold Time (Thold) Clock-to-out Time (Tco) 3.84 8.07 7.94 8.53 6.26 7.14 6.86 7.26 9.83 X X X X X X X X X X 12.24 8.89 6.78 X 12.51
Setup Time (Tsu) Xa X X X X X X X X 5.94 9.55 10.39 11.94 11.33 10.39 10.58 10.79 - 10.39 X X X 7.40 X
Hold Time Clock-to-out (Thold) Time (Tco) X X X X X X X X X 0 0 0 0 0 0 0 0 - 0 X X X 0 X 5.11 10.73 10.56 11.35 8.32 9.50 9.12 9.66 13.07 X X X X X X X X X X 16.28 11.82 9.02 X 16.64
ahbm_hwdata ahbm_hrdata ahb_hready_in ahbm_hresp ahbm_hbusreq ahbm_hgrant
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 40: 100MHz and 133MHz QuickMIPS Interface Port Synchronous Timing (to hclk) (Continued)
100MHz Signal Name Fabric APB Slave Ports apbs_paddr apbs_pwdata apbs_penable apbs_pwrite apbs_psel0 apbs_psel1 apbs_psel2 apbs_prdata0 apbs_prdata1 apbs_prdata2 Timer Ports tm_fbenable tm_overflow2 tm_overflow3 tm_overflow4 0.23 X X X 0 X X X X 4.35 4.48 5.00 0.17 X X X 0 X X X X 3.27 3.37 3.76 X X X X X X X 7.44 6.79 6.97 X X X X X X X 0 0 0 4.52 4.66 2.87 4.13 3.80 3.43 3.25 X X X X X X X X X X 5.59 5.11 5.24 X X X X X X X 0 0 0 3.40 3.50 2.16 3.11 2.86 2.58 2.44 X X X Setup Time (Tsu) Hold Time Clock-to-out (Thold) Time (Tco) Setup Time (Tsu) 133MHz Hold Time (Thold) Clock-to-out Time (Tco)
a. "x" indicates that this timing delay does not apply to the signal. b. The ahbm_hprot signal is NOT used by any slave within the standard cell part of the chip. None of the masters besides the processor-AHB-bridge generates this signal. Therefore there is no setup or hold timing for ahbm_hprot.
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 41: QuickMIPS Interface Port Asynchronous Timing
Start Port ahbm_haddr ahbm_haddr ahbm_htrans ahbm_hwrite ahbm_hsize ahbm_hburst ahbm_hprot ahbm_hwdata ahbs_hrdata ahbs_hready_out ahbs_hresp ahbm_hbusreq ahbs_hresp apbs_prdata0 apbs_prdata1 apbs_prdata2 End Port ahbs_haddr ahbs_hsel ahbs_htrans ahbs_hwrite ahbs_hsize ahbs_hburst ahbs_hprot ahbs_hwdata ahbm_hrdata ahb_hready_in ahbm_hresp ahbm_hgrant ahbm_hgrant ahbm_hrdata ahbm_hrdata ahbm_hrdata Propagation Delay (Tprop) 100MHz 8.39 7.71 6.48 6.21 6.04 5.70 7.07 8.15 5.78 5.03 4.98 10.14 10.50 8.28 7.51 7.57 133MHz 6.31 5.80 4.87 4.67 4.54 4.29 5.32 6.13 4.35 3.78 3.74 7.62 7.89 6.23 5.65 5.69
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QL901M QuickMIPSTM Data Sheet Rev. F
Fabric Kv and Kt Graphs
Figure 42: Voltage Factor vs. Supply Voltage
Voltage Factor vs. Supply Voltage
1.1000 1.0800 1.0600 1.0400 Kv 1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7 2.75
Supply Voltage (V)
Figure 43: Temperature Factor vs. Operating Temperature
Temperature Factor vs. Operating Temperature
1.15 1.10 1.05
Kt
1.00 0.95 0.90 0.85 -60
-40
-20
0
20
40
60
80
Junction Temperature C
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59
QL901M QuickMIPSTM Data Sheet Rev. F
Package Thermal Characteristics
Thermal Resistance Equations:
JC JA
= (TJ - TC)/P = (TJ - TA)/P
PMAX = (TJMAX - TAMAX)/JA Parameter Description:
JC: JA:
TJ: TC: TA: P: PMAX: TJMAX: TAMAX:
Junction-to-case thermal resistance Junction-to-ambient thermal resistance Junction temperature Case temperature Ambient temperature Power dissipated by the device while operating The maximum power dissipation for the device Maximum junction temperature Maximum ambient temperature
NOTE: Maximum junction temperature (TJMAX) is 125C. To calculate the maximum power dissipation for a device package look up JA from Table 42, pick an appropriate TAMAX and use: PMAX = (125C - TAMAX)/JA
Table 42: Package Thermal Characteristics
Package Description Pin Count Package Type 680 PBGA
JA ( C/W) @ Various Flow Rates (m/sec)
0 22.0 0.5 20.0 1 19.0 2 18.0
JC ( C/W)
8.0
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QL901M QuickMIPSTM Data Sheet Rev. F
Power vs. Operating Frequency
The basic power equation which best models power consumption is given below: PTOTAL (mW) = 0.350 + fFabric [0.0031 LC + 0.0948 CKBF + 0.01 CLBF + 0.0263 CKLD + 0.543 RAM + 0.20 PLL + 0.0035 INP + 0.0257 OUTP] + 28.1 fasspio + 10.7 fmips Where
LC CKBF CLBF CKLD RAM PLL INP OUTP
fFabric fasspio fmips
= number of logic cells in the design = number of clock buffers = number of column clock buffers = number of loads connected to the column clock buffers = number of RAM blocks = number of PLLs = number of input pins = number of output pins = average switching frequency of Fabric = average switching frequency of ASSP I/O signals = CPU operational frequency
NOTE: To learn more about power consumption, please refer to Application Note 60 at http://www.quicklogic.com/images/appnote60.pdf.
Power-Up Sequencing
Figure 44: Power-Up Sequencing
VCCIO
Voltage
VCC (VCCIO -VCC)MAX VCC
400 us
Time
When powering up a device, the VCC/VCCIO rails must take 400 s or longer to reach the maximum value (refer to Figure 44). NOTE: Ramping VCC/VCCIO to the maximum voltage faster than 400 s can cause the device to behave improperly. For users with a limited power budget, keep (VCCIO -VCC)MAX 500 mV when ramping up the power supply.
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QL901M QuickMIPSTM Data Sheet Rev. F
Signal Descriptions
Pin Descriptions
Table 43: Pin Descriptions
Pin PCI Signals PCI Address and Data. PCI_AD(31:0) contain the multiplexed address and data. A bus transaction consists of a single address phase (or two address phases for 64-bit addresses) followed by one or more data phases. The QuickMIPS chip supports both read and write bursts. The address phase occurs in the first clock cycle when PCI_FRAME_n is asserted. During the address phase, PCI_AD(31:0) contain a 32-bit physical address. For I/O, this I/O is a byte address; for configuration and memory, it is a DWORD (32-bit) address. During data phases, PCI_AD(7:0) contain the least-significant byte, and PCI_AD(31:24) contain the most-significant byte. Write data is stable and valid when PCI_IRDY_n is asserted; read data is stable and valid when PCI_TRDY_n is asserted. Data is transferred when both PCI_IRDY_n and PCI_TRDY_n are asserted. Connect to GND if the PCI Controller is unused. Bus Command and Byte Enables. Bus commands and byte enables are multiplexed on PCI_C_BE_n(3:0). During the address phase of a transaction (PCI_FRAME_n is asserted), PCI_C_BE_n(3:0) define the bus command as shown in the following table (only valid combinations are shown). PCI_C_BE_n(3:0) 0000 0001 0010 0011 0110 0111 1010 1011 1100 1101 1110 1111 Bus Command Interrupt Acknowledge Special Cycle I/O Read I/O Write Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate I/O Function
PCI_AD(31:0)
PCI_C_BE_n(3:0)
I/O
During each data phase, PCI_C_BE_n(3:0) are byte enables. The byte enables are valid for the entire data phase and determine which byte lanes contain meaningful data. PCI_C_BE_n(0) applies to byte 0 (PCI_AD(7:0)) and PCI_C_BE_n(3) applies to byte 3 (PCI_AD(31:24)). Connect to GND if the PCI Controller is unused. PCI Device Select. When asserted low, PCI_DEVSEL_n indicates the driving device has decoded its address as the target of the current access. As an input, I/O PCI_DEVSEL_n indicates whether any device on the bus has responded. Connect to 3.3 V if the PCI Controller is unused.
PCI_DEVSEL_n
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 43: Pin Descriptions (Continued)
Pin I/O Function PCI Cycle Frame. The current master asserts PCI_FRAME_n to indicate the beginning and duration of a bus transaction. While PCI_FRAME_n is asserted, data transfers I/O continue. When PCI_FRAME_n is deasserted, the transaction is in the final data phase or has completed. Connect to 3.3 V if the PCI Controller is unused. PCI_GNT_n I PCI Grant. A low assertion of PCI_GNT_n indicates to the agent that access to the bus has been granted. PCI_GNT_n is ignored while PCI_RST_n is asserted. Connect to 3.3 V if the PCI Controller is unused. PCI_IDSEL I PCI Initialization Device Select. PCI_IDSEL is used as a chip select during configuration read and write transactions (PCI_C_BE_n(3:0) = 1010 or 1011). Connect to GND if the PCI Controller is unused. PCI Interrupt Acknowledge. PCI_INTA_n is a level-sensitive interrupt driven by the QuickMIPS chip. PCI_INTA_n is asserted and deasserted asynchronously to the PCI_CLK. This interrupt remains asserted until the interrupt is cleared. PCI_INTA_n O Because the PCI interrupt controller is not built into the QuickMIPS ESP core, this pin is output only. However, such an interrupt controller can be built into the Fabric. Leave unconnected if the PCI Controller is unused. PCI Initiator Ready. PCI_IRDY_n is used in conjunction with PCI_TRDY_n. The bus master (initiator) asserts PCI_IRDY_n to indicate when there is valid data on PCI_AD(31:0) during a write, or that it is ready to accept data on PCI_AD(31:0) during a read. PCI_IRDY_n I/O A data phase is completed when both PCI_IRDY_n and PCI_TRDY_n are asserted. During a write, a low assertion of PCI_IRDY_n indicates that valid data is present on PCI_AD(31:0). During a read, a low assertion of PCI_IRDY_n indicates the master is prepared to accept data. Wait cycles are inserted until both PCI_IRDY_n and PCI_TRDY_n are asserted together. Connect to 3.3 V if the PCI Controller is unused. PCI Parity. Parity is driven high or low to create even parity across PCI_AD(31:0) and PCI_C_BE_n(3:0). The master drives PCI_PAR for address and write data phases; the I/O target drives PCI_PAR for read data phases. Connect to 3.3 V if the PCI Controller is unused. PCI Parity Error. PCI_PERR_n indicates the occurrence of a data parity error during all PCI transactions except a Special Cycle. The QuickMIPS chip drives PCI_PERR_n low two clocks following the data when a data parity error is detected. The minimum duration of the deassertion of PCI_PERR_n is one clock for each data phase that a data parity I/O error is detected. (If sequential data phases each have a data parity error, the PCI_PERR_n signal is asserted for more than a single clock.) PCI_PERR_n is driven high for one clock before being 3-stated as with all sustained 3-state signals. Connect to 3.3 V if the PCI Controller is unused.
PCI_FRAME_n
PCI_PAR
PCI_PERR_n
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 43: Pin Descriptions (Continued)
Pin PCI_REQ_n I/O O Function PCI Request. Assertion of PCI_REQ_n indicates to the arbiter that this agent desires use of the bus. PCI_REQ_n is 3-stated while PCI_RST_n is asserted. Leave unconnected if the PCI Controller is unused. PCI Reset. Asserting PCI_RST_n low resets the internal state of the QuickMIPS PCI block. When PCI_RST_n is asserted, all PCI output signals are asynchronously 3-stated. PCI_REQ_n and PCI_GNT_n must both be 3-stated (they cannot be driven low or high during reset). The assertion/deassertion of PCI_RST_n can be asynchronous to PCI_CLK. Connect to GND if the PCI Controller is unused. PCI System Error. The QuickMIPS chip asserts PCI_SERR_n to indicate an address parity error, a data parity error on the Special Cycle command, or any other system error where the result is catastrophic. PCI_SERR_n is open drain and is actively driven for a single PCI clock. The assertion of PCI_SERR_n is synchronous to the clock and meets the setup and hold times of all bused signals. However, the restoring of PCI_SERR_n to the deasserted state is accomplished by a weak pull-up (same value as used for s/t/s), which is provided by the central resource not by the signaling agent. This pull-up can take two to three clock periods to fully restore PCI_SERR_n. Leave unconnected if the PCI Controller is unused. PCI_STOP_n I/O PCI Stop. PCI_STOP_n is asserted low to indicate the current target is requesting the master to stop the current transaction. Connect to 3.3 V if the PCI Controller is unused. PCI Target Ready. PCI_TRDY_n is used in conjunction with PCI_IRDY_n. The current bus slave (target) asserts PCI_TRDY_n to indicate when there is valid data on PCI_AD(31:0) during a read, or that it is ready to accept data on PCI_AD(31:0) during a write. PCI_TRDY_n I/O A data phase is completed when both PCI_TRDY_n and PCI_IRDY_n are asserted. During a read, a low assertion of PCI_TRDY_n indicates that valid data is present on PCI_AD(31:0). During a write, a low assertion indicates the target is prepared to accept data. Wait cycles are inserted until both PCI_IRDY_n and PCI_TRDY_n are asserted together. Connect to 3.3 V if the PCI Controller is unused. PCI_CLK I PCI Clock. All PCI signals (except PCI_RST_n and PCI_INTA_n) are sampled on the rising edge of PCI_CLK. PCI_CLK operates at speeds up to either 33 MHz or 66 MHz. Connect to GND if the PCI Controller is unused.
PCI_RST_n
I
PCI_SERR_n
O
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 43: Pin Descriptions (Continued)
Pin I/O Function Ethernet Receive Clock. RXCLK is a continuous clock that provides the timing reference for the transfer of the RXDV and RXD(3:0) signals from the Ethernet PHY Controller to the MAC core. The Ethernet PHY Controller chip sources RXCLK. RXCLK has a frequency equal to 25% of the data rate of the received signal on the Ethernet cable. Connect to GND if the Ethernet Controller is unused. Ethernet Transmit Clock. TXCLK is a continuous clock that provides a timing reference for the transfer of the TXEN and TXD signals from the MAC core to the Ethernet PHY Controller. The Ethernet PHY Controller chip sources TXCLK. The operating frequency of TXCLK is 25 MHz when operating at 100 Mbps and 2.5 MHz when operating at 10 Mbps. Connect to GND if the Ethernet Controller is unused. Ethernet Collision Detected. The external Ethernet PHY Controller chip asserts COL high upon detection of a collision on the medium. COL remains asserted while the collision condition persists. M1_COL, M2_COL I The transitions on the COL signal are not synchronous to either the TXCLK or the RXCLK. The QuickMIPS MAC core ignores the COL signal when operating in the full-duplex mode. Ethernet Carrier Sense. The external Ethernet PHY Controller chip asserts CRS high when either transmit or receive medium is non-idle. The PHY deasserts CRS low when both the transmit and receive medium are idle. The PHY must ensure that CRS remains asserted throughout the duration of a collision condition. The transitions on the CRS signal are not synchronous to either the TXCLK or the RXCLK. Ethernet Management Data Clock. MDC is sourced by the MAC core to the Ethernet PHY Controller as the timing reference for transfer of information on the MDI/MDO signals. MDC is an aperiodic signal that has no maximum high or low times. The minimum high and low times for MDC are 160 ns each, and the minimum period for MDC is 400 ns, regardless of the nominal period of TXCLK and RXCLK. Ethernet Management Data In/Out. This is the data input signal from the Ethernet PHY Controller. The PHY drives the Read Data synchronously with respect to the MDC clock during the read cycles. This is also the data output signal from the MAC core that drives the control information during the Read/Write cycles to the External PHY Controller. The MAC core drives the MDO signal synchronously with respect to the MDC. Ethernet Receive Data. RXD(3:0) transition synchronously with respect to RXCLK. The Ethernet PHY Controller chip drives RXD(3:0). For each RXCLK period in which RXDV is asserted, RXD(3:0) transfer four bits of recovered data from the PHY to the MAC core. RXD0 is the least-significant bit. While RXDV is deasserted low, RXD(3:0) has no effect on the MAC core. Ethernet Controller Signals
M1_RXCLK, M2_RXCLK
I
M1_TXCLK, M2_TXCLK
I
M1_CRS, M2_CRS
I
M1_MDC, M2_MDC
O
M1_MDIO, M2_MDIO
I
M1_RXD(3:0), M2_RXD(3:0)
I
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 43: Pin Descriptions (Continued)
Pin I/O Function Ethernet Receive Data Valid. The Ethernet PHY Controller asserts RXDV high to indicate to the MAC core that it is presenting the recovered and decoded data bits on RXD(3:0) and that the data on RXD(3:0) is synchronous to RXCLK. RXDV transitions synchronously with respect to RXCLK. RXDV remains asserted continuously from the first recovered nibble of the frame through the final recovered nibble, and is deasserted low prior to the first RXCLK that follows the final nibble. Ethernet Receive Error. The Ethernet PHY Controller chip asserts RXER high for one or more RXCLK periods to indicate to the MAC core that an error (a coding error or any error that the PHY is capable of detecting that is otherwise undetectable by the MAC) was detected somewhere in the frame presently being transferred from the PHY to the MAC core. RXER transitions synchronously with respect to RXCLK. While RXDV is deasserted low, RXER has no effect on the MAC core. Ethernet Transmit Data. The QuickMIPS MAC core drives TXD(3:0). TXD(3:0) transition synchronously with respect to TXCLK. For each TXCLK period in which TXEN is asserted, TXD(3:0) have the data to be accepted by the Ethernet PHY Controller chip. TXD0 is the least-significant bit. While TXEN is deasserted, ignore the data presented on TXD(3:0). Ethernet Transmit Enable. A high assertion on TXEN indicates that the MAC core is presenting nibbles on the MII for transmission. The QuickMIPS MAC core asserts TXEN with the first nibble of the preamble and holds TXEN asserted while all nibbles to be transmitted are presented to the MII. TXEN is deasserted low prior to the first TXCLK following the final nibble of the frame. TXEN is transitions synchronously with respect to TXCLK. SRAM Byte Enables. BLS_n(3:0) indicates the validity of the bytes on DATA(31:0) for external SRAM read and write accesses. BLS_n(3) corresponds to DATA(31:24) BLS_n(2) corresponds to DATA(23:16) BLS_n(1) corresponds to DATA(15:8) BLS_n(0) corresponds to DATA(7:0) Chip Selects. These signals are the active-low chip selects for the SRAM. Memory Address. This 24-bit bus contains the memory address for external SRAM and SDRAM accesses. Memory Data. This 32-bit bus contains the memory read/write data for SRAM and SDRAM accesses. SRAM Output Enable. OE_n is the active-low output enable to the external SRAM. SDRAM Column Address Strobe. SD_CAS_n is the active-low column address strobe for the external SDRAM. SDRAM Clock Enables. If low, these signals indicate to the externally connected SDRAM to enter the power-down state. SDRAM Input Clock. SD_CLKIN should be tied to SD_CLKOUT on the PCB. Internal to the QuickMIPS device, all SDRAM command, address and data signals are synchronized with SD_CLKIN. If a clock buffer is used to drive the SDRAM devices, this buffer should be a zero-delay type buffer, and SD_CLKIN should be tied to one of the buffer outputs.
M1_RXDV, M2_RXDV
I
M1_RXER, M2_RXER
I
M1_TXD(3:0), M2_TXD(3:0)
O
M1_TXEN, M2_TXEN
O
Memory Controller Interface Signals
BLS_n(3:0)
O
CS_n(7:0) ADDR(23:0) DATA(31:0) OE_n SD_CAS_n SD_CKE(1:0)
O O I/O O O O
SD_CLKIN
I
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 43: Pin Descriptions (Continued)
Pin SD_CLKOUT I/O O Function SDRAM Output Clock. SD_CLKOUT is the clock source for the externally connected SDRAMs. This signal may be connected to a zero-delay buffer to drive multiple SDRAM devices. SD_CLKOUT is equal in frequency to the internal System Bus clock and hclk. SDRAM Output Chip Select. SD_CS_n(1:0) are the active-low chip selects for the external SDRAMs. SDRAM Data Mask. SD_DQM(3:0) are the data masks for DATA(31:0) during SDRAM read and write accesses. SD_DQM(3) corresponds to DATA(31:24) SD_DQM(2) corresponds to DATA(23:16) SD_DQM(1) corresponds to DATA(15:8) SD_DQM(0) corresponds to DATA(7:0) SDRAM Row Address Strobe. SD_RAS_n is the active-low row address strobe for the external SDRAM. SDRAM Write Enable. SD_WE_n is the active-low write enable to the SDRAMs. SRAM Write Enable. WEN_n indicates whether transactions between the QuickMIPS chip and the external SRAM are reads (WEN_n is high) or writes (WEN_n is low). UART1 Clear To Send. A low on this signal indicates the external device is ready to transfer data. Connect to GND if the UART is unused. U1_DCD_n I UART1 Data Carrier Detect. A low on this signal indicates the data carrier has been detected. Connect to GND if the UART is unused. U1_DSR_n I UART1 Data Set Ready. A low on this signal indicates the modem or data set is ready to establish the link to the QuickMIPS UART. Connect to GND if the UART is unused. U1_DTR_n O UART1 Data Terminal Ready. The QuickMIPS chip asserts this output low to indicate it is ready to establish the external communication link. Leave unconnected if the UART is unused. UART1 Ring Indicator. This input is an active-low ring indicator. U1_RI_n I Connect to 3.3 V if the UART is unused. U1_RTS_n O UART1 Request to Send. The QuickMIPS chip asserts this signal low to inform the external device that the UART is ready to send data. Leave unconnected if the UART is unused. U1_RXD_SIRIN I UART1 Receive Serial Data/SIR Receive Serial Data. This input receives serial data from either the UART or the IrDA block. Connect to GND if the UART is unused. U1_TXD_SIROUT_n O UART1 Transmit Serial Data/SIR Transmit Serial Data. This output transmits serial data to either the UART or IrDA block. Leave unconnected if the UART is unused. * * * *
SD_CS_n(1:0)
O
SD_DQM(3:0)
O
SD_RAS_n SD_WE_n WEN_n UART Interface Signals U1_CTS_n
O O O
I
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 43: Pin Descriptions (Continued)
Pin U2_RXD_SIRIN I/O I Function UART2 Receive Serial Data/SIR Receive Serial Data. This input receives serial data from either the UART or the IrDA block. Connect to GND if the UART is unused. U2_TXD_SIROUT_n Test Interface Signals EJTAG_TCK I EJTAG Test Clock. This clock controls the updates to the TAP Controller and the shifts through the Instruction register or selected data registers. Both the rising and falling edges of EJTAG_TCK are used. EJTAG Test Data In. Serial test data is input on this pin and is shifted into the Instruction or data register. This input is sampled on the rising edge of EJTAG_TCK. EJTAG Test Data Out. The QuickMIPS chip outputs serial test data on this pin from the Instruction or data register. This signal changes on the falling edge of EJTAG_TCK. EJTAG Test Mode Select. This input is the control signal for the TAP Controller. It is sampled on the rising edge of EJTAG_TCK. EJTAG Test Reset. This signal is asserted asynchronously to reset the TAP Controller, Instruction register, and EJTAGBOOT indication. Debug Mode. This bit is asserted high when the MIPS 4Kc core is in Debug Mode. This output can be used to bring the chip out of low power mode. Debug Exception Request. Assertion high of this input indicates a debug exception request is pending. The request is cleared when debug mode is entered. Requests that occur while the chip is in debug mode are ignored. O UART2 Transmit Serial Data/SIR Transmit Serial Data. This output transmits serial data to either the UART or IrDA block. Leave unconnected if the UART is unused.
EJTAG_TDI EJTAG_TDO EJTAG_TMS EJTAG_TRST EJTAG_DEBUGM
I O I I O
EJTAG_DINT Fabric Interface Signals I/O(A)
I
Programmable Input/Output/3-State/Bidirectional Pin in Bank A. If an I/O is not I/O used, SpDE (QuickWorks Tool) provides the option of tying that pin to GND, VCC, or TriState during programming. Programmable Input/Output/3-State/Bidirectional Pin in Bank B. If an I/O is not I/O used, SpDE (QuickWorks Tool) provides the option of tying that pin to GND, VCC, or TriState during programming. Programmable Input/Output/3-State/Bidirectional Pin in Bank C. If an I/O is not I/O used, SpDE (QuickWorks Tool) provides the option of tying that pin to GND, VCC, or TriState during programming. Programmable Input/Output/3-State/Bidirectional Pin in Bank D. If an I/O is not I/O used, SpDE (QuickWorks Tool) provides the option of tying that pin to GND, VCC, or TriState during programming. Programmable Global Clock Pin. This pin provides access to a global network capable of driving the CLOCK, SET, RESET, F1, and A2 inputs to the Logic Cell, READ and WRITE CLOCKS, Read and Write Enables of the Embedded RAM Blocks, CLOCK of the ECUs, and Output Enables of the I/Os. In addition, this input also serves as the input clock reference to PLL1. This input pin is LVCMOS2 compliant only (2.5 V). Connect to 2.5 V or GND if unused.
I/O(B)
I/O(C)
I/O(D)
CLK(8:5), CLK(3)/PLLIN(1), CLK(2:0)
I
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 43: Pin Descriptions (Continued)
Pin I/O Function Low Skew Dedicated Clock. This pin provides access to a dedicated, distributed clock network capable of driving the CLOCK inputs of all sequential elements of the device (e.g., RAM, flip-flops). In addition, this input also serves as the input clock reference to PLL0. This input pin is LVCMOS2 compliant only (2.5 V). Connect to 2.5 V or GND if unused. Differential I/O Reference Voltage. INREF is the reference voltage pin for GTL+, SSTL2, and STTL3 standards. Follow the recommendations provided in Table 18 for the appropriate standard. Connect to GND when using TTL, PCI or LVCMOS. High Drive I/O Control Pins. This pin provides fast RESET, SET, CLOCK, and ENABLE access to the I/O cell flip-flops, providing fast clock-to-out and fast I/O response times. This pin can also double as a high-drive pin to the internal logic cells. There is an internal pull-down resistor to Ground on this pin. This input pin is LVCMOS2 compliant only (2.5 V). This pin should be tied to Ground if it is not used. If tied to Vcc, it will draw no more than 20 A per IOCTRL pin due to the pull-down resistor. Fabric JTAG Signals TDI/RSI I Test Data In for JTAG/RAM Init. Serial Data In. Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to 2.5 V if unused. TRSTB/RRO I Active low Reset for JTAG/RAM Init. Reset Out. Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused Test Mode Select for JTAG. Hold HIGH during normal operation. TMS I Connect to 2.5 V if not used for JTAG. Test Clock for JTAG. Hold HIGH or LOW during normal operation. TCK I Connect to 2.5 V or GND if not used for JTAG. TDO/RCO Timer Interface Signals Timer Overflow. When timer #1 is in PWM mode, it counts up to 0xFFFF and then back down to zero. This PWM output signal is asserted high when the value of the counter is less than or equal to the value programmed in timer #1's interval register. Conversely, this signal is asserted low when the counter is greater than the interval value. Timer Enable. This signal can be used to enable the timers internal to the QuickMIPS device. Internal timer setup registers determine how this signal is used by each timer block. O Test Data Out for JTAG/RAM Init. Clock Out. Connect to serial PROM clock for RAM initialization. Must be left unconnected if not used for JTAG or RAM initialization
CLK(4)/ DEDCLK/PLLIN(0)
I
INREF(A:D)
I
IOCTRL(A:D)
I
TM_OVERFLOW
O
TM_ENABLE
I
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 43: Pin Descriptions (Continued)
Pin Miscellaneous Signals Boot Memory Size. These signals indicate to the QuickMIPS device the width of the boot memory (the width of the memory device connected to CS_n(7)). BOOT(1:0) = 00: 8-bit width BOOT(1:0) = 01: 16-bit width BOOT(1:0) = 10: 32-bit width BOOT(1:0) = 11: Reserved Endian Setting. A High on this input indicates big-endian byte ordering; a Low on this input indicates little-endian byte ordering. CPU Interrupts. Asserting low any of these inputs causes an interrupt to the QuickMIPS chip. These inputs are active low, level sensitive, and must be held low for at least two CPU pipeline clocks for the CPU to recognize the interrupt. CPU_EXTINT_n(6) is a Non Maskable Interrupt (NMI). Connect to 3.3 V if unused. STM I QuickLogic Reserved Pin. Tie to GND on the PCB. Active Low CPU Reset. Asserting this signal low resets the entire ASSP portion of the QuickMIPS device (except for the PCI Controller, which has its own reset input). When low, PL_RESET_n causes a cold reset exception to the MIPS CPU and halts all internal system clocks. This signal should be asserted for at least five PL_CLOCKIN clock cycles. For reliable operation, the power supply must be stable and the clock must be running before this signal is deasserted. Active Low CPU Warm Reset. Asserting this signal low resets the entire ASSP portion of the QuickMIPS device (except for the PCI Controller, which has its own reset input). When low, PL_WARMRESET_n causes a warm reset exception to the MIPS CPU, but all system clocks continue to operate. This signal should be asserted for at least five PL_CLOCKIN clock cycles. For reliable operation, the power supply must be stable and the clock must be running before this signal is deasserted. Fabric PLL Active High Reset. If PLLRST is high, then the corresponding PLL outputs are driven to 0. This signal must be asserted and then released for the LOCK_DETECT signal to operate properly. This input pin is LVCMOS2 compliant only (2.5 V). Connect to 2.5 V if the Fabric PLL is not used. Fabric PLL Output Off Chip. This is the Fabric PLL output clock driven off chip. PLLOUT(1:0) ASSP PLL Signals PL_CLOCKIN I Input Clock Signal. This clock input is the reference clock used by the ASSP PLL. The frequency of the clock on this input is multiplied by two to drive the MIPS CPU. This input pin is LVCMOS2 compliant only (2.5 V). Active High PLL Enable Signal. This signal must be high to enable the ASSP-side PLL. If PL_ENABLE and PL_BYPASS are held low, the QL901M is put into a low power saving quiescent state. PLL Bypass. When high, the 2X multiplication of the input clock is not performed and the output clocks are equal to the input frequency. O Leave unconnected if unused. I/O Function
BOOT(1:0)
I
CPU_BIGENDIAN
I
CPU_EXTINT_n(6:0)
I
PL_RESET_n
I
PL_WARMRESET_n
I
Fabric PLL Signals
PLLRST(1:0)
I
PL_ENABLE
I
PL_BYPASS
I
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 43: Pin Descriptions (Continued)
Pin PL_CLKOUT I/O O Function Output Clock Signal from the ASSP PLL. This output operates at the same frequency that is driven to the MIPS CPU. Leave unconnected if unused. PL_LOCK O ASSP PLL Lock. The lock output indicates when the PLL is locked to the input clock and is producing valid output clocks. Leave unconnected if unused. Power and Ground Signals GND I Ground Pin. Tie to GND on the PCB. Voltage Supply Pin for Each of the Four I/O Banks. This pin provides the flexibility for the Fabric to interface with either a 2.5 V or 3.3 V device. Every I/O pin in the respective bank is tolerant of VCCIO(A:D) input signals and outputs VCCIO(A:D) level signals. This pin must be connected to either 2.5 V or 3.3 V. VCC GNDPLL(1:0) VCCPLL(1:0) GNDPLL VCCPLL VCCIO I I I I I I Supply Pin. Tie to 2.5 V supply. Fabric PLL Ground Pin. Tie to analog GND on the PCB. Fabric PLL Voltage Supply Pin. Tie to 2.5 V analog supply. ASSP PLL Ground Pin. Tie to analog GND on the PCB. ASSP PLL Voltage Supply Pin. Tie to 2.5 V analog supply. Voltage Supply Pin for ASSP I/O Signals. This pin must be tied to 3.3 V.
VCCIO(A:D)
I
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QL901M QuickMIPSTM Data Sheet Rev. F
ASSP Fabric Port Descriptions
Table 44: ASSP to Fabric Port Descriptions
Port I/Oa Function AMBA Bus Clock. All AMBA bus transactions are synchronous with this clock. Upon entering the Fabric, hclk is automatically placed on a global clock net. hclk is fixed at 1/2 the CPU clock rate. AMBA Bus Reset. When low, this signal indicates to the programmable Fabric that the ASSP side of the device is in the reset state. This signal should be used to reset the Fabric AHB Master, AHB Slave or APB Slave interfaces. AHB Ready Input. This signal is used by an AHB master and /or an AHB slave implemented in the Fabric. For an AHB master implemented in the Fabric: When high, this signal indicates to the AHB master that the accessed AHB slave is ready to continue the current transfer. For an AHB slave implemented in the Fabric: An AHB slave must only sample the address and control signals and ahbs_hsel when ahb_hready_in is high, indicating that the current transfer is completing. Under certain circumstances it is possible that ahbs_hsel will be asserted when ahb_hready_in is low, but the selected slave will have changed by the time the current transfer completes. AHB Master Interface Signals ahbm_haddr(31:0) I AHB Master Address. This bus contains the AHB address for the transfer initiated by the Fabric AHB master. AHB Master Burst Type. These signals indicate the length of the Fabric AHB master burst transfer. Possible burst sizes are: 000: SINGLE 001: INCR (length unspecified) 010: WRAP4 011: INCR4 100: WRAP8 101: INCR8 110: WRAP16 111: INCR16 AHB Master Bus Request. When high, this signal indicates to the AHB arbiter that the AHB master implemented in the Fabric is requesting ownership of the AHB. AHB Master Grant. When high, this signal indicates that the AHB master implemented in the Fabric is the current AHB master. AHB Master Protection. Protected transfers are not supported by the QuickMIPS device. The AHB master implemented in the Fabric should tie all bits of this bus low. AHB Master Read Data. The AHB master implemented in the Fabric receives data for AHB reads on this bus. Data is received from the selected AHB slave. AHB and APB Clock and Reset Signals hclk O
hresetn
O
AHB Master and AHB Slave Interface Signals
ahb_hready_in
O
ahbm_hburst(2:0)
I
ahbm_hbusreq
I
ahbm_hgrant
O
ahbm_hprot(3:0)
I
ahbm_hrdata(31:0)
O
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 44: ASSP to Fabric Port Descriptions (Continued)
Port I/Oa Function AHB Master Transfer Response. The AHB master implemented in the Fabric receives these signals from the accessed AHB slave. For a given transfer, the slave may respond with: 00: OKAY 01: ERROR 10: RETRY 11: SPLIT (not supported in QuickMIPS) AHB Master Transfer Size. The AHB master implemented in the Fabric drives these signals to indicate to the selected slave the size of the transfer taking place. Possible transfer sizes are: 000: 8 bits (byte) 001: 16 bits (halfword) 010: 32 bits (word) 011: 64 bits 100: 128 bits (4-word line) 101: 256 bits (8-word line) 110: 512 bits 111: 1024 bits AHB Master Transfer Type. The AHB master implemented in the Fabric drives these signals to indicate to the selected slave the type of transfer taking place. Possible transfer types are: 00: IDLE 01: BUSY 10: NONSEQUENTIAL 11: SEQUENTIAL AHB Master Write Data. The AHB master implemented in the Fabric drives data for AHB writes on this bus. Data is received by the selected AHB slave. AHB Master Write. The AHB master implemented in the Fabric drives this signal high during an AHB write operation and low during an AHB read. AHB Slave Address. This bus contains the AHB address for the transfer intended for the AHB Fabric slave. AHB Slave Burst Type. These signals indicate the length of the transfer intended for the AHB Fabric slave. Possible burst sizes are: 000: SINGLE 001: INCR (length unspecified) 010: WRAP4 011: INCR4 100: WRAP8 101: INCR8 110: WRAP16 111: INCR16 AHB Slave Protection. Protected transfers are not supported by the QuickMIPS device. The AHB slave implemented in the Fabric ignores these signals. AHB Slave Read Data. The AHB slave implemented in the Fabric drives data for AHB reads on this bus. Data is received by the initiating AHB master. AHB Slave Ready Output. When high, this signal indicates to the initiating AHB master that the AHB slave implemented in the Fabric is ready to continue the current transfer.
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ahbm_hresp(1:0)
O
ahbm_hsize(2:0)
I
ahbm_htrans(1:0)
I
ahbm_hwdata(31:0) ahbm_hwrite AHB Slave Interface Signals ahbs_haddr(31:0)
I I
O
ahbs_hburst(2:0)
O
ahbs_hprot(3:0) ahbs_hrdata;(31:0)
O I
ahbs_hready_out
I
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 44: ASSP to Fabric Port Descriptions (Continued)
Port I/Oa Function AHB Slave Transfer Response. The initiating AHB master receives these signals from the AHB slave implemented in the Fabric. For a given transfer, the slave responds with: 00: OKAY 01: ERROR 10: RETRY 11: SPLIT (not supported in QuickMIPS) AHB Slave Select. When high, this signal indicates to the AHB slave implemented in the Fabric that it is the selected slave for the current AHB transfer. AHB Slave Transfer Size. These signals indicate the size of the transfer intended for the AHB Fabric slave. Possible transfer sizes are: 000: 8 bits (byte) 001: 16 bits (halfword) 010: 32 bits (word) 011: 64 bits 100: 128 bits (4-word line) 101: 256 bits (8-word line) 110: 512 bits AHB Slave Transfer Type. These signals indicate the type of transfer intended for the AHB Fabric slave. Possible transfer types are: 00: IDLE 01: BUSY 10: NONSEQUENTIAL 11: SEQUENTIAL AHB Slave Write Data. The initiating AHB master drives data for AHB writes on this bus. Data is intended for the AHB slave in the Fabric. AHB Slave Write. During an AHB transfer, this signal is driven high during a write operation and low during a read. It is received by the AHB slave implemented in the Fabric. APB Slave Address. This bus contains the APB address for the transfer intended for an APB Fabric slave. APB Slave Enable. This signal, when high, indicates the second phase (data phase) of an APB transfer intended for an APB Fabric slave. APB Slave 0 Read Data. The APB slave 0 implemented in the Fabric drives data for APB reads on this bus. APB Slave 1 Read Data. The APB slave 1 implemented in the Fabric drives data for APB reads on this bus. APB Slave 2 Read Data. The APB slave 2 implemented in the Fabric drives data for APB reads on this bus. APB Slave 0 Select. This signal, when high, indicates that the current transfer is intended for APB slave 0 implemented in the Fabric. APB Slave 1 Select. This signal, when high, indicates that the current transfer is intended for APB slave 1 implemented in the Fabric. APB Slave 2 Select. This signal, when high, indicates that the current transfer is intended for APB slave 2 implemented in the Fabric.
ahbs_hresp(1:0)
I
ahbs_hsel
O
ahbs_hsize(2:0)
O
ahbs_htrans(1:0)
O
ahbs_hwdata(31:0)
O
ahbs_hwrite APB Slave Interface Signals apbs_paddr(15:2) apbs_penable apbs_prdata0(31:0) apbs_prdata1(31:0) apbs_prdata2(31:0) apbs_psel0 apbs_psel1 apbs_psel2
O
O O I I I O O O
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 44: ASSP to Fabric Port Descriptions (Continued)
Port apbs_pwdata(31:0) I/Oa O Function APB Slave Write Data. All APB slaves implemented in the Fabric receive data for APB write transactions from this bus. APB Slave Write. During an APB transfer, this signal is driven high during a write operation and low during a read. It is received by all APB slaves implemented in the Fabric. Timer 1 External Clock. This port allows a clock generated in the Fabric to drive Timer/Counter #1. Timer 2 External Clock. This port allows a clock generated in the Fabric to drive Timer/Counter #2. Timer 3 External Clock. This port allows a clock generated in the Fabric to drive Timer/Counter #3. Timer 4 External Clock. This port allows a clock generated in the Fabric to drive Timer/Counter #4. Timer Enable from Fabric. This signal, when high, indicates to the timer enable logic that the Fabric design has enabled the timer(s). Internal timer setup registers determine how this signal is used by each timer block. Timer 2 Overflow. When timer #2 is in PWM mode, it counts up to 0xFFFF and then back down to zero. This PWM output signal is asserted high when the value of the counter is less than or equal to the value programmed in timer #2 interval register. Conversely, this signal is asserted Low when the counter is greater than the interval value. Timer 3 Overflow. When timer #3 is in PWM mode, it counts up to 0xFFFF and then back down to zero. This PWM output signal is asserted high when the value of the counter is less than or equal to the value programmed in timer #3 interval register. Conversely, this signal is asserted Low when the counter is greater than the interval value. Timer 4 Overflow. When timer #4 is in PWM mode, it counts up to 0xFFFF and then back down to zero. This PWM output signal is asserted high when the value of the counter is less than or equal to the value programmed in timer #4 interval register. Conversely, this signal is asserted Low when the counter is greater than the interval value. Big Endian Indicator to Fabric. This signal, when high, indicates to the Fabric that the QuickMIPS device is in big endian mode. Interrupt from Fabric. This signal, when driven high by a design in the Fabric, causes an interrupt to the MIPS processor. This input is active high and level sensitive. Performance Monitor Data Cache Hit. This signal is asserted whenever there is a data cache hit. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Data Cache Miss. This signal is asserted whenever there is a data-cache miss. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Data TLB Hit. This signal is asserted whenever there is a hit in the data TLB. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor data TLB Miss. This signal is asserted whenever there is a miss in the data TLB. This signal is synchronous with CPU_PLL_CLKOUT.
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apbs_pwrite Timer/Counter Signals tm_extclk1 tm_extclk2 tm_extclk3 tm_extclk4
O
I I I I
tm_fbenable
I
tm_overflow2
O
tm_overflow3
O
tm_overflow4
O
MIPS CPU Signals fb_bigendian O
fb_int
I
pm_dcachehit pm_dcachemiss pm_dtlbhit pm_dtlbmiss
O O O O
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 44: ASSP to Fabric Port Descriptions (Continued)
Port pm_icachehit I/Oa O Function Performance Monitor Instruction Cache Hit. This signal is asserted whenever there is an instruction-cache hit. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Instruction Cache Miss. This signal is asserted whenever there is an instruction-cache miss. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Instruction Complete. This signal is asserted each time an instruction completes in the pipeline. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Instruction TLB Hit. This signal is asserted whenever there is an instruction TLB hit. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Instruction TLB Miss. This signal is asserted whenever there is an instruction TLB miss. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Joint TLB Hit. This signal is asserted whenever there is a joint TLB hit. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Joint TLB Miss. This signal is asserted whenever there is a joint TLB miss. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Write-Through Merge. This signal is asserted whenever there is a successful merge in the write-through buffer. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Write-Through Non-Merge. This signal is asserted whenever a non-merging store is written to the write-through buffer. This signal is synchronous with CPU_PLL_CLKOUT. Reduce Power Indicator to Fabric. This signal represents the state of the RP bit (27) in the MIPS CP0 Status register. Software can write this bit to indicate that the device can enter a reduced power mode. This signal is synchronous with CPU_PLL_CLKOUT. Sleep Indicator to Fabric. This signal is asserted by the MIPS core whenever the WAIT instruction is executed. The assertion of this signal indicates that the clock has stopped and that the core is waiting for an interrupt. This signal is synchronous with CPU_PLL_CLKOUT. PCI Configuration Done. This signal represents the initial value (after reset) of the Config Done bit in the PCI DMA registers. After reset, the value of this register may be overwritten through the AHB. The purpose for this register is to disable the PCI interface until the MIPS processor is ready. This may be useful when the readonly ID registers in the PCI configuration space will be over-written by the MIPS processor, which will require some time. While this register is 0, retries will be signaled on the PCI bus, thus signaling that the QuickMIPS device is not ready, and the PCI transaction should be tried again at a later time. Note that the PCI Specification limits the length of time that a device can retry a transaction, and states the amount of time after the PCI reset is deasserted when a PCI configuration cycle may occur. In an embedded system, however, a designer may choose to violate certain PCI specifications if he/she knows it will not have a detrimental impact on the system. This signal is tie-low or tie-high in the Fabric only.
pm_icachemiss
O
pm_instncomplete
O
pm_itlbhit
O
pm_itlbmiss
O
pm_jtlbhit pm_jtlbmiss
O O
pm_wtbmerge
O
pm_wtbnomerge
O
si_rp
O
si_sleep
O
PCI Configuration Settings
AF_PCI_CFGDONE
I
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 44: ASSP to Fabric Port Descriptions (Continued)
Port I/Oa Function PCI Class Code. These signals represent the initial value (after reset) of the Class Code bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. The Class Code register is used to identify the generic function of the device and, in some cases, a specific register-level programming interface. These signals are tie-low or tie-high in the Fabric only. PCI Device ID. These signals represent the initial value (after reset) of the Device ID bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. This field identifies the particular PCI device. This identifier is allocated by the vendor. These signals are tie-low or tie-high in the Fabric only. PCI Host. This signal represents the initial value (after reset) of the Host Mode bit in the PCI DMA registers. After reset, the value of this register may be overwritten through the AHB. This register controls whether the QuickMIPS device acts as the PCI system host or is a satellite device. A system host must configure itself as well as all the devices on the PCI bus, whereas a satellite device will be configured by another device (the host) of the PCI system. Note that while in host mode, the PCI configuration registers may only be accessed by the AHB, but while in satellite (non-host) mode, the PCI configuration registers may only be accessed by the PCI bus. This signal is tie-low or tie-high in the Fabric only. PCI Maximum Latency. These signals represent the initial value (after reset) of the Max Latency bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. This register is used for specifying how often the device needs to gain access to PCI bus. These signals are tie-low or tie-high in the Fabric only. PCI Minimum Grant. These signals represent the initial value (after reset) of the Min Grant bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. This register is used for specifying how long a burst period the device needs assuming a clock rate of 33 MHz.These signals are tie-low or tie-high in the Fabric only. PCI Revision ID. These signals represent the initial value (after reset) of the Revision ID bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. This register specifies a device specific revision identifier. The value is chosen by the vendor (zero is an acceptable value). This field should be viewed as a vendor defined extension to the Device ID. These signals are tie-low or tie-high in the Fabric only.
AF_PCI_CLASSCODE(23:0)
I
AF_PCI_DEVID(15:0)
I
AF_PCI_HOST
I
AF_PCI_MAXLAT(7:0)
I
AF_PCI_MINGNT(7:0)
I
AF_PCI_REVID(7:0)
I
(c) 2003 QuickLogic Corporation
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 44: ASSP to Fabric Port Descriptions (Continued)
Port I/Oa Function PCI Subsystem ID. These signals represent the initial value (after reset) of the Subsystem ID bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. These registers are used to uniquely identify the expansion board or subsystem where the PCI device resides. They provide a mechanism for expansion board vendors to distinguish their boards from one another even though the boards may have the same PCI controller on them. These signals are tie-low or tie-high in the Fabric only. PCI Subsystem Vendor ID. These signals represent the initial value (after reset) of the Subsystem Vendor ID bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. These registers are used to uniquely identify the expansion board or subsystem where the PCI device resides. They provide a mechanism for expansion board vendors to distinguish their boards from one another even though the boards may have the same PCI controller on them. These signals are tie-low or tie-high in the Fabric only. PCI Vendor ID. These signals represent the initial value (after reset) of the Vendor ID bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. This field identifies the manufacturer of the device. Valid vendor identifiers are allocated by the PCI SIG to ensure uniqueness. These signals are tie-low or tie-high in the Fabric only.
AF_PCI_SUBSYSID(15:0)
I
AF_PCI_SUBSYSVID(15:0)
I
AF_PCI_VENID(15:0)
I
a. Interface direction is specified with respect to the ASSP portion of the device. I designates an input to the ASSP and O designates an output from the ASSP.
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QL901M QuickMIPSTM Data Sheet Rev. F
680 BGA Pinout Table
Table 45: 680 PBGA Pinout Table
680 PBGA
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25
Function
GND GND I/O I/O I/O I/O INREF I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND CLK<5> I/O I/O I/O I/O I/O I/O I/O IOCTRL I/O I/O I/O I/O I/O GND GND GND GND I/O I/O I/O I/O I/O IOCTRL I/O I/O I/O I/O I/O I/O I/O I/O CLK<8> CLK<7> I/O I/O I/O I/O I/O I/O I/O
680 PBGA
B26 B27 B28 B29 B30 B31 B32 B33 B34 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16
Function
INREF I/O I/O I/O I/O I/O I/O GND GND GNDPLL<0> I/O GND I/O I/O I/O I/O I/O I/O IOCTRL I/O I/O I/O I/O I/O I/O TMS CLK<6> I/O I/O I/O I/O I/O I/O IOCTRL I/O I/O I/O I/O I/O I/O GND I/O I/O GND PLLOUT<1> I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
680 PBGA
D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 F1 F2 F3 F4 F5 F30 F31
Function
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O PLLRST<0> I/O I/O I/O I/O VCC VCC VCCIO I/O I/O I/O I/O VCC VCCIO VCC I/O I/O I/O I/O VCC VCCIO VCC I/O I/O I/O I/O VCCIO VCC VCC I/O I/O VCCPLL<1> PLLRST<1> GNDPLL<1> I/O I/O VCCPLL<0> I/O VCC VCC I/O
680 PBGA
F32 F33 F34 G1 G2 G3 G4 G5 G30 G31 G32 G33 G34 H1 H2 H3 H4 H5 H30 H31 H32 H33 H34 J1 J2 J3 J4 J5 J30 J31 J32 J33 J34 K1 K2 K3 K4 K5 K30 K31 K32 K33 K34 L1 L2 L3 L4 L5 L30 L31 L32 L33 L34 M1 M2 M3 M4 M5 M30
Function
GND I/O I/O I/O I/O I/O I/O VCC VCC PLLOUT<0> I/O I/O I/O I/O I/O I/O I/O VCCIO VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOCTRL INREF IOCTRL I/O I/O I/O
680 PBGA
M31 M32 M33 M34 N1 N2 N3 N4 N5 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N30 N31 N32 N33 N34 P1 P2 P3 P4 P5 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P30 P31 P32 P33 P34 R1 R2 R3 R4 R5 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22
Function
I/O IOCTRL I/O INREF I/O I/O I/O I/O VCC GND VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO GND VCC IOCTRL I/O I/O I/O I/O I/O I/O I/O VCCIO VCCIO GND GND GND GND GND GND GND GND VCCIO VCCIO I/O I/O I/O I/O I/O I/O I/O I/O VCC VCCIO GND GND GND GND GND GND GND GND VCCIO
680 PBGA
R30 R31 R32 R33 R34 T1 T2 T3 T4 T5 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T30 T31 T32 T33 T34 U1 U2 U3 U4 U5 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U30 U31 U32 U33 U34 V1 V2 V3 V4 V5 V13 V14 V15 V16 V17 V18 V19 V20 V21
Function
VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO GND GND GND GND GND GND GND GND VCCIO I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCCIO GND GND GND GND GND GND GND GND VCCIO I/O I/O I/O I/O GND GND I/O I/O I/O I/O VCCIO GND GND GND GND GND GND GND GND
(Sheet 1 of 2)
(c) 2003 QuickLogic Corporation
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QL901M QuickMIPSTM Data Sheet Rev. F
Table 45: 680 PBGA Pinout Table
680 PBGA
V22 V30 V31 V32 V33 V34 W1 W2 W3 W4 W5 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W30 W31 W32 W33 W34 Y1 Y2 Y3 Y4 Y5 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y30 Y31 Y32 Y33 Y34 AA1 AA2 AA3 AA4 AA5 AA13 AA14 AA15 AA16
Function
VCCIO I/O I/O I/O I/O GND I/O I/O I/O I/O GNDPLL VCCIO GND GND GND GND GND GND GND GND VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O PL_CLOCKIN VCCIO GND GND GND GND GND GND GND GND VCCIO CLK<4>/DEDCLK/ PLLIN<0> I/O I/O I/O I/O I/O CLK<0> CLK<1> VCCIO VCCPLL VCCIO GND GND GND
680 PBGA
AA17 AA18 AA19 AA20 AA21 AA22 AA30 AA31 AA32 AA33 AA34 AB1 AB2 AB3 AB4 AB5 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB30 AB31 AB32 AB33 AB34 AC1 AC2 AC3 AC4 AC5 AC30 AC31 AC32 AC33 AC34 AD1 AD2 AD3 AD4 AD5 AD30 AD31 AD32 AD33 AD34 AE1 AE2 AE3 AE4
Function
GND GND GND GND GND VCCIO VCCIO EJTAG_DEBUGM CLK<3>/PLLIN<1> I/O I/O TCK TDI GND STM VCC GND VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO GND VCC CS_n<0> GND TRSTB CLK<2> VCC TDO PL_CLKOUT PL_BYPASS BOOT<0> CS_n<5> CS_n<2> NC EJTAG_DINT VCC PL_LOCK PL_ENABLE PL_WARMRESET_n M2_MDIO M2_TXD<2> BLS_n<2> CS_n<7> CS_n<4> CS_n<1> NC PL_RESET_n BOOT<1> M2_TXD<3> M2_TXD<0>
680 PBGA
AE5 AE30 AE31 AE32 AE33 AE34 AF1 AF2 AF3 AF4 AF5 AF30 AF31 AF32 AF33 AF34 AG1 AG2 AG3 AG4 AG5 AG30 AG31 AG32 AG33 AG34 AH1 AH2 AH3 AH4 AH5 AH30 AH31 AH32 AH33 AH34 AJ1 AJ2 AJ3 AJ4 AJ5 AJ30 AJ31 AJ32 AJ33 AJ34 AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9
Function
M2_RXDV ADDR<2> OEN_n BLS_n<0> CS_n<6> CS_n<3> M2_TXEN M2_TXD<1> M2_RXER M2_RXD<2> M2_RXD<0> ADDR<7> ADDR<4> ADDR<0> BLS_n<1> WEN_n M2_MDC M2_TXCLK M2_RXD<1> M2_CRS VCCIO VCCIO ADDR<12> ADDR<5> ADDR<1> BLS_n<3> M2_RXD<3> M2_RXCLK M1_MDIO M1_MDC VCC VCC ADDR<16> ADDR<9> ADDR<6> ADDR<3> M2_COL M1_TXEN M1_TXD<1> M1_TXCLK M1_COL ADDR<21> ADDR<17> ADDR<13> ADDR<10> ADDR<8> M1_TXD<3> M1_TXD<2> M1_RXER M1_RXD<3> NC GND VCC VCCIO PCI_AD<23>
680 PBGA
AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34 AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30
Function
PCI_AD<17> PCI_FRAME_n PCI_PAR VCC VCCIO EJTAG_TRST EJTAG_TDO CPU_EXTINT _n<1> CPU_ BIGENDIAN U1_RI_n U1_DCD_n VCCIO VCC SD_CLKIN DATA<28> DATA<24> DATA<16> VCCIO VCC DATA<2> DATA<1> ADDR<22> ADDR<18> ADDR<14> ADDR<11> M1_TXD<0> M1_RXCLK M1_CRS GND M1_RXD<2> PCI_RST_n M1_RXD<0> PCI_IDSEL PCI_CLK PCI_AD<20> PCI_C_BE _n<2> PCI_STOP_n PCI_AD<14> PCI_AD<8> PCI_AD<7> PCI_AD<3> EJTAG_TMS CPU_EXTINT _n<4> U2_RXD_SIRIN U1_CTS_n SD_WE_n SD_CS_n<1> SD_DQM<3> DATA<31> DATA<25> DATA<19> DATA<11> DATA<6> DATA<7> DATA<3>
680 PBGA
AL31 AL32 AL33 AL34 AM1 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17
Function
GND ADDR<23> ADDR<20> ADDR<15> M1_RXDV NC GND M1_RXD<1> TM_OVERFLOW PCI_GNT_n PCI_AD<30> PCI_AD<26> PCI_AD<21> PCI_C_BE _n<3> PCI_DEVSEL_n PCI_SERR_n PCI_AD<15> PCI_AD<11> PCI_AD<5> PCI_AD<1> EJTAG_TDI CPU_EXTINT _n<5> CPU_EXTINT_n <0> U1_DTR_n NC SD_CKE<0> NC SD_DQM<2> SD_CLKOUT DATA<26> DATA<20> DATA<15> DATA<13> DATA<9> DATA<5> GND DATA<0> ADDR<19> GND GND TM_ENABLE PCI_REQ_n PCI_AD<31> PCI_AD<28> PCI_AD<25> PCI_AD<19> PCI_AD<16> PCI_TRDY_n PCI_PERR_n PCI_C_BE_n<0> PCI_AD<12> PCI_AD<9> PCI_AD<4> PCI_AD<0> EJTAG_TCK
680 PBGA
AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AP1 AP2 AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34
Function
CPU_EXTINT_n<6> CPU_EXTINT_n<2> U1_RTS_n U1_TXD _SIROUT_n NC SD_CAS_n NC SD_DQM<1> DATA<30> DATA<23> DATA<21> DATA<17> DATA<12> DATA<8> DATA<4> GND GND GND GND PCI_INTA_n PCI_AD<29> PCI_AD<27> PCI_AD<24> PCI_AD<22> PCI_AD<18> PCI_IRDY_n VCCIO PCI_C_BE_n<1> PCI_AD<13> PCI_AD<10> PCI_AD<6> PCI_AD<2> GND GND GND CPU_EXTINT_n<3> U2_TXD _SIROUT_n U1_DSR_n U1_RXD_SIRIN SD_CKE<1> SD_RAS_n SD_CS_n<0> SD_DQM<0> DATA<29> DATA<27> DATA<22> DATA<18> DATA<14> DATA<10> GND GND
(Sheet 2 of 2)
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(c) 2003 QuickLogic Corporation
QL901M QuickMIPSTM Data Sheet Rev. F
680 BGA Pinout Drawing
Figure 45: 680 BGA Pinout Diagram
(c) 2003 QuickLogic Corporation
www.quicklogic.com * *
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QL901M QuickMIPSTM Data Sheet Rev. F
Ordering Information
QL QuickLogic Device Part Number: 901M Processor Speed: 100 MHz 133 MHz Package Lead Count: PS680 = 680-ball BGA (1.0 mm) 901M -100 PS680 C Operating Range: C = Commercial I = Industrial
Contact Information
Telephone: (408) 990 4000 (US) (416) 497 8884 (Canada) +(44) 1932 57 9011 (Rest of Europe) +(49) 89 930 86 170 (Germany & Benelux) +(8621) 6867 0273 (Asia) +(81) 45 470 5525 (Japan) E-mail: Support: Web site: info@quicklogic.com http://www.quicklogic.com/support http://www.quicklogic.com/
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(c) 2003 QuickLogic Corporation
QL901M QuickMIPSTM Data Sheet Rev. F
Revision History
Revision A B C Date December 2001 December 2001 July 2003 Comments First release Donna Chin - updated PLL information Judd Heape and Kathleen Murchek Modifications to all sections including part number information. Judd Heape and Kathleen Murchek Modifications to all sections including DC characteristics, signal descriptions, device pinout, and Fabric PLL information. Judd Heape and Jesse Blount Changed Tjmax number from 150C to 125C in Package Thermal Characteristics section. Removed Preliminary. Judd Heape and Kathleen Murchek Added an AHB Master and AHB Slave Interface Signals section with an ahb_hready_in row to ASSP to Fabric Port Descriptions table.
D
July 2003
E
September 2003
F
December 2003
Copyright and Trademark Information
Copyright (c) 2003 QuickLogic Corporation. All Rights Reserved. The information contained in this document and the accompanying software programs are protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic and the QuickLogic logo, pASIC, ViaLink, DeskFab, and QuickWorks are registered trademarks of QuickLogic Corporation; Eclipse, QuickFC, QuickDSP, QuickDR, QuickSD, QuickTools, QuickCore, QuickPro, SpDE, WebASIC, and WebESP are trademarks of QuickLogic Corporation.
(c) 2003 QuickLogic Corporation
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