View PCM1739_998156.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
PCM
49% 173 9 FPO
PCM1739
For most current data sheet and other product information, visit www.burr-brown.com
24-Bit, 192kHz Sampling, Enhanced Multi-Level, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER
TM
FEATURES
q 24-BIT RESOLUTION q ANALOG PERFORMANCE (VCC = +5V): Dynamic Range: 106dB typ SNR: 105dB typ THD+N: 0.0015% typ Full-Scale Output: 3.1Vp-p typ q 4x/8x OVERSAMPLING DIGITAL FILTER: Passband: 0.454fS Stopband: 0.546fS Stopband Attenuation: -82dB Passband Ripple: 0.002dB q SAMPLING FREQUENCY: 10kHz to 192kHz q SYSTEM CLOCK: 128fS, 192fS, 256fS, 384fS, 512fS, or 768fS with Auto Detect q ACCEPTS 24- or 16-BIT AUDIO DATA q DATA FORMATS: Standard, I2S q MODE CONTROLS Digital De-Emphasis Soft Mute Zero Flags for Each Output q DUAL SUPPLY OPERATION: +5V Analog, +3.3V Digital q 5V TOLERANT DIGITAL INPUTS q SMALL 28-LEAD SSOP PACKAGE
APPLICATIONS
q A/V RECEIVERS q DVD AUDIO AND MOVIE PLAYERS q DVD ADD-ON CARDS FOR ENTERTAINMENT PCs q HDTV RECEIVERS q CAR AUDIO SYSTEMS q OTHER APPLICATIONS REQUIRING 24-BIT AUDIO
DESCRIPTION
The PCM1739 is a CMOS, monolithic, integrated circuit which includes stereo 24-bit audio Digital-toAnalog converters and support circuitry in a small 28-lead SSOP package. The data converters utilize Burr-Brown's enhanced multi-level delta-sigma architecture, which employs 4th-order noise shaping and 8-level amplitude quantization to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1739 accepts industry-standard audio data formats with 16- or 24-bit data, providing easy interfacing to audio DSP and decoder chips. Sampling rates up to 192kHz are supported.
International Airport Industrial Park * Mailing Address: PO Box 11400, Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 * Tel: (520) 746-1111 Twx: 910-952-1111 * Internet: http://www.burr-brown.com/ * Cable: BBRCORP * Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132
(c) 1999 Burr-Brown Corporation
PDS-1560A
Printed in U.S.A. November, 1999
SPECIFICATIONS
All specifications at TA = +25C, +VCC = +5V, +VDD = +3.3V, system clock = 384fS (fS = 44.1kHz) and 24-bit data, unless otherwise noted. PCM1739E PARAMETER RESOLUTION DATA FORMAT Audio Data Interface Formats Audio Data Bit Length Audio Data Format System Clock Frequency Sampling Frequency (fS) DIGITAL INPUT/OUTPUT Logic Family Input Logic Level VIH VIL Input Logic Current IIH IIL IIH(1) IIL(1) Output Logic Level VOH(2) VOL(2) VOH(3) VOL(3) DYNAMIC PERFORMANCE(4) THD+N, VOUT = 0dB User Selectable User Selectable CONDITIONS MIN TYP 24 Standard/I2S 16 or 24 Bits MSB-First, Binary Two's Complement 128, 192, 256, 384, 512, 768fS 10 200 TTL-Compatible 2.0 0.8 VIN = VDD VIN = 0V VIN = VDD VIN = 0V IOH = -2mA IOL = +2mA IOH = -4mA IOL = +4mA fS = 44.1kHz, 384fS fS = 96kHz, 256fS fS = 192kHz, 128fS fS = 44.1kHz fS = 96kHz fS = 192kHz EIAJ, A-Weighted, fS = 44.1kHz A-Weighted, fS = 96kHz A-Weighted, fS = 192kHz EIAJ, A-Weighted, fS = 44.1kHz A-Weighted, fS = 96kHz A-Weighted, fS = 192kHz fS = 44.1kHz fS = 96kHz fS = 192kHz 2.4 1.0 2.4 1.0 0.0015 0.0020 0.25 0.6 0.7 0.8 106 105 104 105 104 104 104 103 102 1.0 1.0 30 62% of VCC 50% of VCC 5 0.0035 0.0050 0.0060 0.8 1.0 1.2 0.1 -0.1 100 -0.1 VDC VDC A A A A VDC VDC VDC VDC % % % % % % dB dB dB dB dB dB dB dB dB % of FSR % of FSR mV Vp-p VDC k MAX UNITS Bits
kHz
65
VOUT = -60dB
Dynamic Range
Signal-to-Noise Ratio(5)
Channel Separation
102 100 98 100 100 100 100 98 96
DC ACCURACY Gain Error Gain Mismatch, Channel-to-Channel Bipolar Zero Error ANALOG OUTPUT Output Voltage Center Voltage Load Impedance DIGITAL FILTER PERFORMANCE Filter Characteristics Passband Stopband Passband Ripple Stopband Attenuation Delay Time De-Emphasis Error ANALOG FILTER PERFORMANCE Frequency Response Cut-Off Frequency
VOUT = 0.5VCC at BPZ Full Scale (-0dB) AC Load
3.0 3.0 60
0.002dB -3dB 0.546fs Stopband = 0.546fS Stopband = 0.567fS -75 -82 34/fS 0.1 At 20kHz At 44kHz -3dB -0.03 -0.20 190
0.454fS 0.490fS 0.002
Hz Hz Hz dB dB dB sec dB dB dB kHz
(R)
PCM1739
2
SPECIFICATIONS (Cont.)
All specifications at +25C, +VCC = +5V, +VDD = +3.3V, system clock = 384fS (fS = 44.1kHz) and 24-bit data, unless otherwise noted. PCM1739E PARAMETER POWER SUPPLY REQUIREMENTS Voltage Range VDD VCC Supply Current IDD(6) VDD = 3.3V fS = 44.1 kHz fS = 96kHz, 256fS fS = 192kHz, 128fS VCC = 5.0V fS = 44.1kHz fS = 96kHz, 256fS fS = 192kHz, 128fS VDD = 3.3V, VCC = 5.0V fS = 44.1kHz fS = 96kHz, 256fS fS = 192kHz, 128fS 0 -55 100 CONDITONS MIN TYP MAX UNITS
+3.0 +4.5
+3.3 +5.0
+3.6 +5.5
VDC VDC
8.5 16.5 19.5 13.0 14.0 14.5 93 124 137
12.0
mA mA mA mA mA mA mW mW mW C C C/W
ICC
18.0
Power Dissipation
130
TEMPERATURE RANGE Operation Storage Thermal Resistance JA
70 +125
NOTES: (1) Pins 8, 9, 26, 27, 28 (TEST1, IBIT, DEM0 DEM1, FORM). (2) Pins 23, 24 (ZEROL, ZEROR). (3) Pin 4 (CLKO). (4) Analog performance specs are tested with Shibasoku #725 THD Meter 400Hz HPF, 30kHz LPF on, average mode with 20kHz bandwidth limiting. The load connected to the analog output is 5k or larger, AC-coupled. (5) SNR is tested with Infinite Zero Detection off. (6) CLKO is disabled.
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage, VDD .............................................................. +4.0V VCC .............................................................. +6.5V Input Current (except power supply pins) ....................................... 10mA Supply Voltage Difference ................................................................ 0.1V GND Voltage Difference ................................................................... 0.1V Digital Input Voltage ........................................................... -0.2V to +5.5V Digital Output Voltage .............................................. -0.2V to (VDD + 0.2V) Power Dissipation .......................................................................... 650mW Operating Temperature Range ............................................. 0C to +70C Storage Temperature ...................................................... -55C to +125C Lead Temperature (soldering, 5s) ................................................ +260C Package Temperature (IR reflow, 10s) .......................................... +235C
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE PCM1739E " PACKAGE 28-Lead SSOP " PACKAGE DRAWING NUMBER 324 " SPECIFIED TEMPERATURE RANGE 0C to +70C " PACKAGE MARKING PCM1739E " ORDERING NUMBER(1) PCM1739E PCM1739E/2K TRANSPORT MEDIA Rails Tape and Reel
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of "PCM1739E/2K" will get a single 2000-piece Tape and Reel.
(R)
3
PCM1739
BLOCK DIAGRAM
PCM1739 BCK LRCK Audio Serial I/F 4x/8x Oversampling Digital Filter with Function Controller Mode Control I/F VOUTL DAC Output Amp and Low-Pass Filter VCOML
DATA Enhanced Multi-level Delta-Sigma Modulator
TEST IBIT RSTB FORM DEM1 DEM0 MUTE FILT
DAC
Output Amp and Low-Pass Filter
VOUTR VCOMR
System Clock System Clock Manager
SCLK
Zero Detect
Power Supply
VDD
VCCL
GNDA
GNDL
VSS
VCCA
VCCR
ZEROL
PIN ASSIGNMENTS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME LRCK DATA BCLK CLKO SCLK VSS VDD TEST1 IBIT VCCR GNDR VCOMR VOUTR GNDA VCCA VOUTL VCOML GNDL VCCL FILT MUTE RSTB ZEROL ZEROR NC DEM0 DEM1 FORM TYPE IN IN IN OUT IN -- -- IN IN -- -- -- OUT -- -- OUT -- -- -- IN IN IN OUT OUT -- IN IN IN DESCRIPTION Left/Right Word Clock(1) Data In for Left and Right Channels(1) Bit Clock(1) System Clock Output System Clock Input(1) Digital Ground Digital Supply, +3.3V. Test Pin. Must be connected to VDD(2). Audio Data Word Length Select(2) Analog Supply for Right Channel, +5V. Analog Ground for Right Channel Common for Right Channel Analog Output for Right Channel Analog Ground Analog Supply, +5V. Analog Ouput for Left Channel Common for Left Channel Analog Ground for Left Channel Analog Supply for Left Channel, +5V. 4x/8x Interpolation Filter Select(2) Digital Mute for Left and Right Channels(2) Reset, Active Low(1). Zero Flag for Left Channel Zero Flag for Right Channel No Connect De-Emphasis Filter Select 0(2) De-Emphasis Filter Select 1(2) Audio Data Format Select(2)
ZEROR
PIN CONFIGURATION
Top View SSOP
LRCK DATA BCLK CLKO SCLK VSS VDD TEST1 IBIT VCCR GNDR VCOMR VOUTR GNDA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 PCM1739E
GNDR
28 27 26 25 24 23 22 21 20 19 18 17 16 15
CLKO
FORM DEM1 DEM0 NC ZEROR ZEROL RSTB MUTE FILT VCCL GNDL VCOML VOUTL VCCA
NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger input, 5V tolerant.
(R)
PCM1739
4
TYPICAL PERFORMANCE CURVES
All specifications at TA = +25C, VDD = VCC = 5V, SYSCLK = 384fS (fS = 44.1kHz), and 20-bit input data, unless otherwise noted.
DIGITAL FILTER
Digital Filter (De-Emphasis Off, fS = 44.1kHz)
FREQUENCY RESPONSE 0 -20 -40
PASSBAND RIPPLE 0.003 0.002 Amplitude (dB) 0.001 0 -0.001 -0.002
Amplitude (dB)
-60 -80 -100 -120 -140 -160
-0.003
0 0.5 1 1.5 2 2.5 3 3.5 4
0
0.1
0.2
0.3
0.4
0.5
Frequency (x fS)
Frequency (x fS)
DIGITAL FILTER
De-Emphasis Error
0 -2 -4 -6 -8 -10 0
DE-EMPHASIS FREQUENCY RESPONSE (fS = 32kHz)
0.5 0.3 0.1 -0.1 -0.3 -0.5 0 2
DE-EMPHASIS ERROR (fS = 32kHz)
Level (dB)
2
4
6
8
10
12
14
Level (dB)
4
6
8
10
12
14
Frequency (kHz) DE-EMPHASIS FREQUENCY RESPONSE (fS = 44.1kHz)
Level (dB)
Frequency (kHz) DE-EMPHASIS ERROR (fS = 44.1kHz)
0 -2 -4 -6 -8 -10 0
0.5 0.3 0.1 -0.1 -0.3 -0.5 0 2
Level (dB)
2
4
6
8
10
12
14
16
18
20
4
6
8
10
12
14
16
18
20
Frequency (kHz) DE-EMPHASIS FREQUENCY RESPONSE (fS = 48kHz)
Level (dB)
Frequency (kHz) DE-EMPHASIS ERR0R (fS = 48kHz)
0 -2 -4 -6 -8 -10 0
0.5 0.3 0.1 -0.1 -0.3 -0.5 0 2 4
Level (dB)
2
4
6
8
10
12
14
16
18
20
22
6
8
10
12
14
16
18
20
22
Frequency (kHz)
Frequency (kHz)
(R)
5
PCM1739
TYPICAL PERFORMANCE CURVES (Cont.)
All specifications at TA = +25C, VDD = VCC = 5V, SYSCLK = 384fS (fS = 44.1kHz), and 20-bit input data, unless otherwise noted.
ANALOG DYNAMIC PERFORMANCE
Supply Voltage Characteristics
TOTAL HARMONIC DISTORTION + NOISE vs VCC (VDD = 3.3V) 10 192kHz, 128fS 1
THD+N (%)
Dynamic Range (dB)
110 108
DYNAMIC RANGE vs VCC (VDD = 3.3V)
-60dB 44.1kHz, 384fS
44.1kHz, 384fS
106 104 102 100 98 192kHz, 128fS
0.1
0.01
192kHz, 128fS 0dB 44.1kHz, 384fS
0.001
0.0001 4.0 4.5 5.0 VCC (V) 5.5 6.0
96 4.0 4.5 5.0 VCC (V) 5.5 6.0
110 108 106
SNR (dB)
SIGNAL-TO-NOISE RATIO vs VCC (VDD = 3.3V)
CHANNEL SEPARATION vs VCC 110 108
44.1kHz, 384fS
Channel Separation (dB)
106 104 102 100 98 96
44.1kHz, 384fS
104 102 100 98 96 4.0 4.5 5.0 VCC (V) 5.5 6.0 192kHz, 128fS
192kHz, 128fS
4.0
4.5
5.0 VCC (V)
5.5
6.0
Temperature Characteristics
TOTAL HARMONIC DISTORTION + NOISE vs TEMPERATURE 10 192kHz, 128fS 1
Dynamic Range (dB)
110 108
-60dB 44.1kHz, 384fS
DYNAMIC RANGE vs TEMPERATURE (VDD = 3.3V)
44.1kHz, 384fS
106 104 102 100 98 192kHz, 128fS
THD+N (%)
0.1
0.01
192kHz, 128fS 0dB
0.001 44.1kHz, 384fS 0.0001 4.0 4.5 5.0 VCC (V) 5.5 6.0
96 -25 0 25 50 75 100 Temperature (C)
(R)
PCM1739
6
TYPICAL PERFORMANCE CURVES (Cont.)
All specifications at TA = +25C, VDD = VCC = 5V, SYSCLK = 384fS (fS = 44.1kHz), and 20-bit input data, unless otherwise noted.
Temperature Characteristics (cont.)
SIGNAL-TO-NOISE RATIO vs TEMPERATURE (VDD = 3.3V) 110 108 106
SNR (dB)
110 108
CHANNEL SEPARATION vs TEMPERATURE (VDD = 3.3V)
Channel Separation (dB)
44.1kHz, 384fS
106 104 102 100 98 96
44.1kHz, 384fS
104 102 100 98 96 -25 0 25 50 75 100 Temperature (C) 192kHz, 128fS
192kHz, 128fS
-25
0
25
50
75
100
Temperature (C)
(R)
7
PCM1739
SYSTEM CLOCK AND RESET FUNCTIONS
SYSTEM CLOCK INPUT The PCM1739 requires a system clock for operating the digital interpolation filters and multi-level delta-sigma modulators. The system clock is applied at the SCLK input (pin 5). Table I shows examples of system clock frequencies for common audio sampling rates. Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. Burr-Brown's PLL1700 multi-clock generator is an excellent choice for providing the PCM1739 system clock. SYSTEM CLOCK OUTPUT A buffered version of the system clock input is available at the CLKO output (pin 4). CLKO operates at the same frequency as the system clock, SCLK.
POWER-ON AND EXTERNAL RESET FUNCTIONS The PCM1739 includes a power-on reset function. Figure 2 shows the operation of this function. The system clock input at SCLK should be active for at least one clock period prior to VDD = 2.0V. With the system clock active and VDD > 2.0V, the power-on reset function will be enabled. The initialization sequence requires 1024 system clocks from the time VDD > 2.0V. The PCM1739 also includes an external reset capability using the RSTB input (pin 22). This allows an external controller or master reset circuit to force the PCM1739 to initialize to its reset default state. For normal operation, RSTB should be set to a logic `1'. Figure 3 shows the external reset operation and timing. The RSTB pin is set to logic `0' for a minimum of 20ns. The RSTB pin is then set to a logic `1' state, which starts the initialization sequence, which lasts for 1024 system clock periods. The external reset is especially useful in applications where there is a delay between PCM1739 power up and system clock activation. In this case, the RSTB pin should be held at a logic `0' level until the system clock has been activated.
SYSTEM CLOCK FREQUENCY, fSCLK, (MHZ) SAMPLING FREQUENCY (fS) 16kHz 32kHz 44.1kHz 48kHz 88.2kHz 96kHz 176.4kHz 192kHz 128fS 2.0480 4.0960 5.6448 6.1440 -- 12.2880 24.5792 24.5760 192fS 3.0720 6.1440 8.4672 9.2160 -- 18.4320 33.8688 36.8640 256fS 4.0960 8.1920 11.2896 12.2880 22.5792 24.5760 See Note 2 See Note 2 384fS 6.1440 12.2880 16.9344 18.4320 33.8688 36.8640 See Note 2 See Note 2 512fS 8.1920 16.3840 22.5792 24.5760 45.1584 49.1520 See Note 2 See Note 2 768fS 12.2880 24.5760 33.8688 36.8640 See Note 1 See Note 1 See Note 2 See Note 2
NOTES: (1) The 768fS system clock rate is not supported for fS > 64kHz. (2) This system clock rate is not supported for the given sampling frequencies.
TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
tSCLK "H" SCLK "L" tSCLK System Clock Pulse Width High tSCLKH System Clock Pulse Width Low tSCLKL fSCLK : 7ns min : 7ns min 0.8V 2.0V
FIGURE 1. System Clock Input Timing.
(R)
PCM1739
8
2.4V
VCC = VDD
2.0V 1.6V
Reset Reset Removal Internal Reset 1024 system clocks System Clock (SCLK)
FIGURE 2. Power-On Reset Timing.
RSTB tRST(1) Reset Reset Removal Internal Reset 1024 system clocks System Clock (SCLK) NOTE: (1) tRST = 20ns min.
FIGURE 3. External Reset Timing.
AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1739 is comprised of a 3-wire synchronous serial port. It includes LRCK (pin 1), BCLK (pin 3), and DATA (pin 2). BCLK is the serial audio bit clock, and is used to clock the serial data present on DATA into the audio interface's serial shift registers. Serial data is clocked into the PCM1739 on the rising edge of BCLK. LRCK is the serial audio left/right word clock. It is used to latch serial data into the serial audio interface's internal registers. Both LRCK and BCLK must be synchronous to the system clock. Ideally, it is recommended that LRCK and BCLK be derived from the system clock input or output, SCLK or CLKO. The left/right clock, LRCK, is operated at the sampling frequency (fS). The bit clock, BCK, may be operated at 48 or 64 times the sampling frequency. AUDIO DATA FORMATS AND TIMING The PCM1739 supports industry-standard audio data formats, including Standard and I2S. The audio data word length may be either 24 or 16 bits. Data format and word length are selected using the FORM and IBIT pins, as described in the Mode Controls section of this data sheet. All formats require Binary Two's Complement, MSB-first audio data. The data formats are shown in Figure 4, while Figure 5 shows a detailed timing diagram for the serial audio interface.
MODE CONTROLS
This section describes the mode control pins used to configure the operating mode of the PCM1739. AUDIO DATA FORMAT The data format used by the audio serial interface is selected using the FORM input (pin 28). The formats available include Standard and I2S. Table II shows the FORM pin configuration.
FORM L H DATA FORMAT Standard I2S
TABLE II. Audio Data Format Selection.
AUDIO DATA WORD LENGTH
The data word length used by the audio serial interface is selected using the IBIT input (pin 9). The word length may be either 24 or 16 bits. Table III shows the IBIT pin configuration.
IBIT L H DATA WORD LENGTH 24 Bits 16 Bits
TABLE III. Audio Data Word Length Selection.
(R)
9
PCM1739
(R)
(1) Standard Data Format; Lch = HIGH, Rch = LOW
1/fS Lch LRCK Rch
FIGURE 4. Audio Data Input Formats.
PCM1739
14 15 16 1 MSB LSB 2 3 14 15 16 1 MSB 2 3 22 23 24 1 1 MSB 2 3 MSB LSB 2 3 4 5 22 23 24 4 5 1/fS LRCK Lch Rch DATA 1 2 3 MSB 22 23 24 LSB 1 MSB 2 3 22 23 24 LSB 1 2
BCLK (= 48fS or 64fS) 14 15 16 LSB
16-Bit Right-Justified DATA
24-Bit Right-Justified DATA
22 23 24 LSB
10
(2) 16- or 24-Bit I2S Data Format; Lch = LOW, Rch = HIGH
BCLK (= 48fS or 64fS)
LRCK tBCH BCLK tBCY DATA tDS tDH tBL tBCL tLB
50% of VDD
50% of VDD
50% of VDD
SYMBOL tBCY tBCH tBCL tBL tLB tDS tDH
PARAMETER BCK Pulse Cycle Time BCK High Level Time BCK Low Level Time BCK Rising Edge to LRCK Edge LRCK Falling Edge to BCK Rising Edge DIN Set Up Time DIN Hold Time
MIN 50 50 30 30 30 20
MAX 48 or 64fS
(1)
UNITS ns ns ns ns ns ns
FIGURE 5. Audio Interface Timing. 4x/8x DIGITAL INTERPOLATION The PCM1739's digital filter may be configured for either 4x or 8x oversampling. The 8x oversampling setting is utilized for sampling frequencies up to 96kHz, while 4x oversampling is utilized for 192kHz operation. The FILT input (pin 20) is used to select the oversampling rate of the digital filter. Table IV shows the FILT pin configuration.
FILT L H OVERSAMPLING RATE 8x 4x ( Required for 192kHz operation)
sis function is required for proper playback of early audio compact disks (CDs), which were mastered with signal emphasis for higher frequencies in the audio band. This was done to improve the poor high frequency performance of early CD players. Plots of the de-emphasis filter and error functions for 32kHz, 44.1kHz, and 48kHz are shown in the Typical Performance Curves section of this data sheet. The DEM0 (pin 26) and DEM1 (pin 27) inputs of the PCM1739 are used to enable and disable the digital deemphasis function. Table VI shows the DEM0 and DEM1 pin configurations.
DEM1 DEM0 L H L H DE-EMPHASIS FUNCTION OFF 32kHz De-Emphasis Filter 44.1kHz De-Emphasis Filter 48kHz De-Emphasis Filter
TABLE IV. Digital Filter Oversampling Rate Selection. SOFT MUTE The Soft Mute function provides for quiet muting of the DAC outputs, VOUTL (pin 16) and VOUTR (pin 13). This is done by ramping an internal digital attenuator from unity gain to digital mute (all 0's input to the digital filter). The MUTE input (pin 21) is used to enable and disable the Soft Mute function. Table V shows the MUTE pin configuration.
MUTE L H SOFT MUTE STATUS Disabled Enabled
L L H H
TABLE VI. Digital De-Emphasis.
ANALOG OUTPUTS
The PCM1739 includes two independent output channels; VOUTL (pin 16) and VOUTR (pin 13). These are unbalanced outputs, each capable of driving 3.1Vp-p typical into a 5k, AC-coupled load (VCC = +5V). The internal output amplifiers for VOUTL and VOUTR are DC biased to a DC commonmode (or bipolar zero) voltage, equal to VCC/2. The output amplifiers include an RC continuous time filter, which helps to reduce the out-of-band noise energy present at the DAC outputs due to the noise shaping characteristics of the PCM1739's delta-sigma D/A converters. The fre-
TABLE V. Soft Mute Selection. DIGITAL DE-EMPHASIS The PCM1739 provides a De-emphasis function for sampling rates equal to 32kHz, 44.1kHz or 48kHz. It is incorporated into the digital filter of the PCM1739. The De-empha-
(R)
11
PCM1739
quency response of this filter is shown in Figure 6. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for most applications. An external lowpass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post filter circuits is provided in the Applications Information section of this data sheet.
VCOML AND VCOMR OUTPUTS Two unbuffered, DC common-mode voltage output pins, VCOML (pin 17) and VCOMR (pin 12), are brought out for decoupling purposes. These pins are normally biased to a DC voltage level equal to VCC/2. These pins may be used to bias external circuits, but they must be connected to high impedance nodes. Figure 7 shows examples of the proper use of the VCOML and VCOMR pins for external biasing applications. ZERO FLAG OUTPUTS The PCM1739 includes circuitry for detecting an all zero data condition for the data input pin, DATA. Zero detection for each output channel is independent from the other. If the data for a given channel remains at a `0' level for 1024 sample periods (or LRCK clock periods), a Zero Detect condition exists for the that channel. Given that a Zero Detect condition exists, the Zero Flag pin(s) for the corresponding channel(s) will be set to a logic `1' state. The zero flag outputs include ZEROL (pin 23) and ZEROR (pin 24). These pins can be used to operate external mute circuits, or used as status indicators for audio signal processor, microcontroller, or other digitally-controlled functions.
20 0 -20 -40 -60 -80 -100 1 10 100 1k 10k 100k 1M 10M Log Frequency (Hz)
FIGURE 6. Output Filter Frequency Response.
Level (dB)
PCM1739 VOUTx 10F + R1
R2 R3 C2
C1
VCC
1/2 OPA2353
Filtered Output
VCOMx + 10F PCM1739 x = L or R OPA337 (a) Using VCOM To Bias A Single-Supply Filter Stage VCOMx x = L or R (b) Using a Voltage Follower to Buffer VCOM when Biasing Multiple Nodes 25k + 10F Buffered VCOM VCC
V+ PCM1739 VOUTx VCOMx + x = L or R 10F V- -IN +IN 25k 25k
Sense
INA134
Out
To Low-Pass Filter Stage
25k
Ref
(c) Using INA134 for DC-Coupled Output
FIGURE 7. Biasing External Circuits Using the VCOML and VCOMR Pins.
(R)
PCM1739
12
APPLICATIONS INFORMATION
CONNECTION DIAGRAM A basic connection diagram with the necessary power supply bypassing and decoupling components is shown in Figure 8. Burr-Brown recommends using the component values shown in Figure 8 for all designs. The use of series resistors (22 to 100) is recommended for the SCLK, LRCK, BCLK, and DATA inputs. The series resistor combines with the stray PCB and device input capacitance to form a low-pass filter, which reduces high frequency noise emissions and helps to dampen glitches and ringing present on clock and data lines. POWER SUPPLIES AND GROUNDING The PCM1739 requires a +5V analog supply and a +3.3V digital supply. The +5V supply is used to power the DAC analog and output filter circuitry, while the +3.3V supply is used to power the digital filter and logic circuitry. For best performance, the +3.3V supply should be derived from the +5V supply using a linear regulator, shown in Figure 8. Burr-Brown's REG1117-3.3 is an ideal choice for this application.
Proper power supply bypassing is shown in Figure 8. The bypass capacitors should be located as close as possible to the PCM1739 package. The 1F and 10F capacitors should be tantalum or aluminum electrolytic, while the 0.1F capacitors are ceramic (X7R type is recommended for surface mount applications). D/A OUTPUT CIRCUITS Delta-sigma D/A converters utilize noise-shaping techniques to improve in-band Signal-to-Noise (SNR) performance at the expense of generating increased out-of-band noise above the Nyquist Frequency, or fS/2. The out-of-band noise must be low-pass filtered in order to provide optimal converter performance. This is accomplished by a combination of onchip and external low pass filtering. Figures 7a and 9 show the recommended external low pass active filter circuits for dual and single-supply applications. These circuits are 2nd-order filters using the Multiple Feedback (MFB) circuit arrangement, which reduces sensitivity to passive component variations over frequency and temperature. For more information regarding MFB active filter design, please refer to Burr-Brown Applications Bulletin AB-034.
RS(1) LRCK From/To Audio Source DATA BCLK CLKO SCLK C1 C2 VSS VDD TEST1 IBIT + VCCR C3 GNDR + C4 VCOMR VOUTR GNDA
PCM1739 FORM DEM1 DEM0 NC ZEROR ZEROL RSTB MUTE FILT VCCL GNDL VCOML VOUTL VCCA + C8 + C9 + C10 Zero Flag Outputs From Host Or Master Reset From Mode Control Logic From Mode Control Logic
+
From Mode Control Logic
+3.3V Regulator
C5 To Output Filter Circuits
C6 +
+5V Analog
C7 +
C1, C4, C6, C9 = 10F Tantalum or Aluminum Electrolytic C2, C5 = 0.1F Ceramic C3, C10 = 1F Tanatlum or Aluminum Electrolytic C7, C8 = 1-10F Aluminum Electrolytic NOTE: (1) RS = 20 to 100.
FIGURE 8. Basic Connection Diagram.
(R)
13
PCM1739
Since the overall system performance is defined by the quality of the D/A converters and their associated analog output circuitry, high quality audio op amps are recommended for the active filters. Burr-Brown's OPA2134 and OPA2353 dual op amps are shown in Figures 7a and 9, and are recommended for use with the PCM1739.
PCB LAYOUT GUIDELINES
A typical PCB floor plan for the PCM1739 is shown in Figure 10. A ground plane is recommended, with the analog and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1739 should be oriented with the digital I/O pins facing the ground plane split/cut, allowing for direct connection of the digital audio interface and control signals originating from the digital section of the board. Separate power supplies are recommended for the digital and analog sections of the board. This prevents the switching noise present on the digital supply from contaminating the analog power supply and degrading the dynamic performance of the PCM1739. In cases where a common +5V supply must be used for the analog and digital sections, an
R2 R1 VIN C2 R3
C1 2 1 3 OPA2134
AV -
R2 R1
R4 VOUT
FIGURE 9. Dual Supply Filter Circuit.
Digital Power +VD DGND
Analog Power AGND +5VA +VS -VS
REG
VCC Digital Logic and Audio Processor VDD DGND PCM1739 AGND Output Circuits Digital Ground
DIGITAL SECTION
ANALOG SECTION
Analog Ground
Return Path for Digital Signals
FIGURE 10. Recommended PCB Layout.
Power Supplies RF Choke or Ferrite Bead +5V AGND +VS -VS
REG
VDD VDD
VCC
DGND PCM1739 AGND
Output Circuits
Common Ground DIGITAL SECTION ANALOG SECTION
FIGURE 11. Single-Supply PCB Layout.
(R)
PCM1739
14
inductance (RF choke, ferrite bead) should be placed between the analog and digital +5V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 11 shows the recommended approach for single-supply applications
enhanced multi-level delta-sigma architecture also has advantages for input clock jitter sensitivity due to the multilevel quantizer, with the simulated jitter sensitivity shown in Figure 14.
THEORY OF OPERATION
The delta-sigma section of PCM1739 is based on a 8-level amplitude quantizer and a 4th-order noise sharper. This section converts the oversampled input data to 8-level deltasigma format. A block diagram of the 8-level delta-sigma modulator is shown in Figure 12. This 8-level delta-sigma modulator has the advantage of stability and clock jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the interpolation filter is 64fS for all system clock combinations (128, 192, 256, 384, 512, 768fS). The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown in Figure 13. The
KEY PERFORMANCE PARAMETERS AND MEASUREMENT
This section provides information on how to measure key dynamic performance parameters for the PCM1739. In all cases, an Audio Precision System Two Cascade or equivalent audio measurement system is utilized to perform the testing. TOTAL HARMONIC DISTORTION + NOISE Total Harmonic Distortion + Noise (THD+N) is a significant figure of merit for audio D/A converters since it takes into account both harmonic distortion and all noise sources within a specified measurement bandwidth. The true rms value of the distortion and noise is referred to as THD+N.
- + 4fS or 8fS + Z-1 + Z-1 + Z-1 + Z-1
+
8-Level Quantizer
64fS
FIGURE 12. Eight-Level Delta-Sigma Modulator.
CLOCK JITTER 125 120
Dynamic Range (dB)
0 -20 -40
Amplitude (dB)
115 110 105 100 95 90 85
-60 -80 -100 -120 -140 -160 -180 0 1 2 3 4 5 6 7 8 Frequency (fS)
80 0 100 200 300 Jitter (ps) 400 500 600
FIGURE 13. Quantization Noise Spectrum. 15
FIGURE 14. Jitter Sensitivity.
(R)
PCM1739
For the PCM1739, THD+N is measured with a full scale, 1kHz digital sine wave as the test stimulus at the input of the DAC. The digital generator is set to 24-bit audio word length and a sampling frequency of 44.1kHz, 96kHz, or 192kHz. The digital generator output is taken from the unbalanced S/PDIF connector of the measurement system. The S/PDIF data is transmitted via a coaxial cable to the digital audio receiver on the DEM-DAI1739 demo board. The receiver is then configured to output 24-bit data in either I2S or left-justified data format. The DAC audio interface format is programmed to match the receiver output format. The analog output is then taken from the DAC post filter and connected to the analog analyzer input of the measurment system. The analog input is band limited using filters resident in the analyzer. The resulting THD+N is measured by the analyzer and displayed by the measurement system. DYNAMIC RANGE Dynamic range is specified as A-Weighted, THD+N measured with a -60dBFS, 1kHz digital sine wave stimulus at the input of the D/A converter. This measurement is de-
signed to give a good indicator of how the DAC will perform given a low-level input signal. The measurement setup for the dynamic range measurement is shown in Figure 15, and is similar to the THD+N test setup discussed previously. The differences include the bandlimit filter selection, the additional A-Weighting filter, and the -60dBFS input level. IDLE CHANNEL SIGNAL-TO-NOISE RATIO The SNR test provides a measure of the noise floor of the D/A converter. The input to the D/A is all 0's data, and the D/A converter's Infinite Zero Detect Mute function must be disabled (default condition at power up for the PCM1739). This ensures that the delta-sigma modulator output is connected to the output amplifier circuit so that idle tones (if present) can be observed and effect the SNR measurement. The dither function of the digital generator must also be disabled to ensure an all `0's data stream at the input of the D/A converter. The measurement setup for SNR is identical to that used for dynamic range, with the exception of the input signal level. (see the notes provided in Figure 16).
Evaluation Board DEM-DAI1737 S/PDIF Receiver 2nd-Order Low-Pass Filter f-3dB = 54kHz or 108kHz
PCM1737
S/PDIF Output
Digital Generator 0dBFS, 1kHz Sine Wave
Analyzer and Display RMS Mode
20kHz Apogee Filter
Band Limit HPF = 22Hz LPF = 30kHz
Notch Filter fC = 1kHz
FIGURE 15. Test Setup for THD+N Measurement.
Evaluation Board DEM-DAI1737 S/PDIF Receiver 2nd-Order Low-Pass Filter f-3dB = 54kHz or 108kHz
PCM1737(1)
S/PDIF Output
Digital Generator 0% Full Scale, Dither Off (SNR) or -60dBFS, 1kHz Sine Wave (Dynamic Range)
Analyzer and Display RMS Mode
A-Weight Filter(2)
Band Limit HPF = 22Hz LPF = 22kHz
Notch Filter fC = 1kHz
NOTES: (1) Infinite Zero Detect Mute disabled. (2) Results without A-Weighting will be approximately 3dB worse.
FIGURE 16. Test Set-Up for Dynamic Range and SNR Measurements.
(R)
PCM1739
16

▲Up To Search▲

Price & Availability of PCM1739

	To Download PCM1739 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .