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PCA9535 REMOTE 16-BIT AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS I2C
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SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
FEATURES
* * * * * * * Low Standby-Current Consumption of 1 A Max I2C to Parallel Port Expander Open-Drain Active-Low Interrupt Output 5-V Tolerant I/O Ports Compatible With Most Microcontrollers 400-kHz Fast I2C Bus Address by Three Hardware Address Pins for Use of up to Eight Devices
DB, DBQ, DGV, DW, N, OR PW PACKAGE (TOP VIEW)
* * * *
Polarity Inversion Register Latched Outputs With High-Current Drive Capability for Directly Driving LEDs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 1000-V Charged-Device Model (C101)
RGE PACKAGE (TOP VIEW)
RHL PACKAGE (TOP VIEW)
VCC
INT
INT A1 A2 P00 P01 P02 P03 P04 P05 P06 P07 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC SDA SCL A0 P17 P16 P15 P14 P13 P12 P11 P10
1
24 23 SDA 22 SCL 21 A0 20 P17 19 P16 18 P15 17 P14 16 P13 15 P12 14 P11 24 23 22 21 20 19
A1 A2 P00 P01 P02 P03 P04 P05 P06 P07
2 3 4 5 6 7 8 9 10 11 12 13
P00 P01 P02 P03 P04 P05
1 2 3 4 5 6 7 8 9 10 11 12
SDA SCL
18 A0 17 P17 16 P16 15 P15 14 P14 13 P13
GND
DESCRIPTION/ORDERING INFORMATION
ORDERING INFORMATION
TA SSOP - DB QSOP - DBQ TVSOP - DGV SOIC - DW -40C to 85C PDIP - N TSSOP - PW QFN - RGE QFN - RHL (1) PACKAGE (1) Reel of 2000 Reel of 250 Reel of 2500 Reel of 2000 Tube of 25 Reel of 2000 Reel of 250 Tube of 15 Tube of 60 Reel of 1200 Reel of 250 Reel of 3000 Reel of 1000 ORDERABLE PART NUMBER PCA9535DBR PCA9535DBT PCA9535DBQR PCA9535DGVR PCA9535DW PCA9535DWR PCA9535DWT PCA9535N PCA9535PW PCA9535PWR PCA9535PWT PCA9535RGER PCA9535RHLR TOP-SIDE MARKING PD9535 PCA9535 PD9535 PCA9535 PREVIEW PREVIEW PD9535 PREVIEW PREVIEW PREVIEW
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
P10
Copyright (c) 2005, Texas Instruments Incorporated
P06 P07 GND P10 P11 P12
A2 A1 INT VCC
PCA9535 REMOTE 16-BIT I2C AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This 16-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V VCC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL), serial data (SDA)]. The PCA9535 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active-high or active-low operation) registers. At power on, the I/Os are configured as inputs. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or Output Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The system master can reset the PCA9535 in the event of a timeout or other improper operation by utilizing the power-on reset feature which puts the registers in their default state and initializes the I2C/SMBus state machine. The PCA9535 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the PCA9535 can remain a simple slave device. The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low current consumption. Although pin-to-pin and I2C-address compatible with the PCF8575, software changes are required due to the enhancements. The PCA9535 is identical to the PCA9555, except for the removal of the internal I/O pullup resistor, which greatly reduces power consumption when the I/Os are held low. Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to eight devices to share the same I2C bus or SMBus. The fixed I2C address of the PCA9535 is the same as the PCA9555, PCF8575, PCF8575C, and PCF8574, allowing up to eight of these devices in any combination to share the same I2C bus or SMBus.
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PCA9535 REMOTE 16-BIT AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS I2C
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
TERMINAL FUNCTIONS
NO. QFN (RHL), PDIP (N), SOIC (D), SSOP (DB), QSOP (DBQ), TSSOP (PW), AND TVSOP (DGV) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
QFN (RGE)
NAME
DESCRIPTION
22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
INT A1 A2 P00 P01 P02 P03 P04 P05 P06 P07 GND P10 P11 P12 P13 P14 P15 P16 P17 A0 SCL SDA VCC
Interrupt output. Connect to VCC through a pullup resistor. Address input. Connect directly to VCC or ground. Address input. Connect directly to VCC or ground. P-port input/output P-port input/output P-port input/output P-port input/output P-port input/output P-port input/output P-port input/output P-port input/output Ground P-port input/output P-port input/output P-port input/output P-port input/output P-port input/output P-port input/output P-port input/output P-port input/output Address input. Connect directly to VCC or ground. Serial clock bus. Connect to VCC through a pullup resistor. Serial data bus. Connect to VCC through a pullup resistor. Supply voltage
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PCA9535 REMOTE 16-BIT I2C AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
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LOGIC DIAGRAM (POSITIVE LOGIC)
1 PCA9535 Interrupt Logic LP Filter
INT
A0 A1 A2 SCL SDA
21 2 3 22 23 Input Filter I2C Bus Control Shift Register 16 Bits I/O Port P17-P10 P07-P00
Write Pulse VCC GND 24 12 Power-On Reset Read Pulse
A. B.
Pin numbers shown are for DB, DBQ, DGV, DW, N, PW, and RHL packages. All I/Os are set to inputs at reset.
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PCA9535 REMOTE 16-BIT AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS I2C
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
SIMPLIFIED SCHEMATIC OF P-PORT I/Os(1)
Data From Shift Register Configuration Register Data From Shift Register Write Configuration Pulse Write Pulse D FF CLK Q Q D FF CLK Q Output Port Register Q
Output Port Register Data VCC Q1
I/O Pin
Q2
Input Port Register D FF Read Pulse CLK Q Q
GND
Input Port Register Data
To INT
Data From Shift Register
D FF
Q
Polarity Register Data
Write Polarity Pulse
CLK Q Polarity Inversion Register
(1)
At power-on reset, all registers return to default values.
I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation.
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PCA9535 REMOTE 16-BIT I2C AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
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I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during the high of the ACK-related clock pulse. The address inputs (A0-A2) of the slave device must not be changed between the Start and Stop conditions. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 2). A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 1). Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation. A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S Start Condition
P Stop Condition
Figure 1. Definition of Start and Stop Conditions
SDA
SCL Data Line Stable; Data Valid Change of Data Allowed
Figure 2. Bit Transfer
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PCA9535 REMOTE 16-BIT AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS I2C
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
Data Output by Transmitter NACK Data Output by Receiver ACK
SCL From Master S Start Condition
1
2
8
9
Clock Pulse for Acknowledgment
Figure 3. Acknowledgment on I2C Bus Interface Definition
BYTE I2C slave address P0x I/O data bus P1x I/O data bus BIT 7 (MSB) L P07 P17 6 H P06 P16 5 L P05 P15 4 L P04 P14 3 A2 P03 P13 2 A1 P02 P12 1 A0 P01 P11 0 (LSB) R/W P00 P10
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PCA9535 REMOTE 16-BIT I2C AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
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Device Address
Figure 4 shows the address byte of the PCA9535.
R/W Slave Address 0 1 0 0 A2 A1 A0
Fixed
Programmable
Figure 4. PCA9535 Address Address Reference
INPUTS A2 L L L L H H H H A1 L L H H L L H H A0 L H L H L H L H I2C BUS SLAVE ADDRESS 32 (decimal), 20 (hexadecimal) 33 (decimal), 21 (hexadecimal) 34 (decimal), 22 (hexadecimal) 35 (decimal), 23 (hexadecimal) 36 (decimal), 24 (hexadecimal) 37 (decimal), 25 (hexadecimal) 38 (decimal), 26 (hexadecimal) 39 (decimal), 27 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation.
Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the PCA9535. Three bits of this data byte state the operation (read or write) and the internal register (input, output, polarity inversion or configuration) that will be affected. This register can be written or read through the I2C bus. The command byte is sent only during a write transmission. Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent.
0 0 0 0 0 B2 B1 B0
Figure 5. Control Register Bits Control Register
CONTROL REGISTER BITS B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 COMMAND BYTE (HEX) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 REGISTER Input Port 0 Input Port 1 Output Port 0 Output Port 1 Polarity Inversion Port 0 Polarity Inversion Port 1 Configuration Port 0 Configuration Port 1 PROTOCOL Read byte Read byte Read/write byte Read/write byte Read/write byte Read/write byte Read/write byte Read/write byte POWER-UP DEFAULT xxxx xxxx xxxx xxxx 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111
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PCA9535 REMOTE 16-BIT AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS I2C
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
Register Descriptions
The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration Register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to let the I2C device know that the Input Port registers will be accessed next. Registers 0 and 1 (Input Port Registers) Table
Bit Default Bit Default I0.7 X I1.7 X I0.6 X I1.6 X I0.5 X I1.5 X I0.4 X I1.4 X I0.3 X I1.3 X I0.2 X I1.2 X I0.1 X I1.1 X I0.0 X I1.0 X
The Output Port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Registers 2 and 3 (Output Port Registers) Table
Bit Default Bit Default O0.7 1 O1.7 1 O0.6 1 O1.6 1 O0.5 1 O1.5 1 O0.4 1 O1.4 1 O0.3 1 O1.3 1 O0.2 1 O1.2 1 O0.1 1 O1.1 1 O0.0 1 O1.0 1
The Polarity Inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin original polarity is retained. Registers 4 and 5 (Polarity Inversion Registers) Table
Bit Default Bit Default N0.7 0 N1.7 0 N0.6 0 N1.6 0 N0.5 0 N1.5 0 N0.4 0 N1.4 0 N0.3 0 N1.3 0 N0.2 0 N1.2 0 N0.1 0 N1.1 0 N0.0 0 N1.0 0
The Configuration registers (registers 6 and 7) configure the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. Registers 6 and 7 (Configuration Registers) Table
Bit Default Bit Default C0.7 1 C1.7 1 C0.6 1 C1.6 1 C0.5 1 C1.5 1 C0.4 1 C1.4 1 C0.3 1 C1.3 1 C0.2 1 C1.2 1 C0.1 1 C1.1 1 C0.0 1 C1.0 1
Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9535 in a reset condition until VCC has reached VPOR. At that point, the reset condition is released, and the PCA9535 registers and I2C/SMBus state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to the operating voltage for a power-reset cycle.
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PCA9535 REMOTE 16-BIT I2C AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
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Interrupt (INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from the port that generated the interrupt or in a Stop event. Resetting occurs in the read mode at the acknowledge (ACK) bit or not acknowledge (NACK) bit after the falling edge of the SCL signal. In a Stop event, INT is cleared after the rising edge of SDA. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa. INT has an open-drain structure and requires a pullup resistor to VCC.
Bus Transactions
Data is exchanged between the master and the PCA9535 through write and read commands. Writes Data is transmitted to the PCA9535 by sending the device address and setting the least-significant bit to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. The eight registers within the PCA9535 are configured to operate as four register pairs. The four pairs are Input Ports, Output Ports, Polarity Inversions, and Configurations. After sending data to one register, the next data byte is sent to the other register in the pair (see Figure 6 and Figure 7). For example, if the first byte is sent to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers.
SCL 1 2 3 4 5 6 7 8 9 Command Byte Data to Port 0 Data to Port 1
Slave Address SDA
S
0
1
0
0
A2 A1 A0
0
A
0
0
0
0
0
0
1
0
A 0.7 Acknowledge From Slave
Data 0
0.0
A 1.7 Acknowledge From Slave
Data 1
1.0
A
P
Start Condition Write to Port
R/W
Acknowledge From Slave
Data Out from Port 0 tpv Data Out from Port 1 Data Valid tpv
Figure 6. Write to Output Port Registers

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PCA9535 REMOTE 16-BIT AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS I2C
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5
SCL
1
2
Slave Address
Command Byte
Data to Register
Data to Register
SDA
S
0
1
0
0
A2 A1 A0
0 R/W
A
0
0
0
0
0
1
1
0
A MSB Acknowledge From Slave
Data 0
LSB
A MSB Acknowledge From Slave
Data 1
LSB
A
P
Start Condition
Acknowledge From Slave
Figure 7. Write to Configuration Registers Reads The bus master first must send the PCA9535 address with the least-significant bit set to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data from the register defined by the command byte then is sent by the PCA9535 (see Figure 8 through Figure 10). After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data
Slave Address Acknowledge From Slave A1 A0 0 R/W A Command Byte Acknowledge From Slave A S 0 1 Slave Address Acknowledge From Slave 1 R/W A MSB Data From Lower or Upper Byte of Register Acknowledge From Master LSB A
S
0
1
0
0
A2
0
0
A2 A1 A0
Data First Byte
At this moment, master transmitter becomes master receiver, and slave receiver becomes slave transmitter.
Data From Upper or Lower Byte of Register
No Acknowledge From Master LSB NA P
MSB
Data Last Byte
Figure 8. Read From Register

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PCA9535 REMOTE 16-BIT I2C AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
SCL 1 2 3 4 5 6 7 8 9 I0.x SDA S 0 1 0 0
A2 A1 A0
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I1.x 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4
I0.x 3 2 1 0 A 7 6 5 4
I1.x 3 2 1 0 1 P
1 R/W
A
7
6
5
4
3
Acknowledge From Slave
Acknowledge From Master
Acknowledge From Master
Acknowledge From Master No Acknowledge From Master
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
INT tiv tir
A.
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register). This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from P port. See Figure 8 for these details.
B.
Figure 9. Read Input Port Register, Scenario 1

SCL
1
2
3
4
5
6
7
8
9
I0.x
SDA S 0 1 0 0 A2 A1 A0 1 A Acknowledge From Slave 00 A
I1.x
10 Acknowledge From Master A
I0.x
03 A
I1.x
12 1 P
R/W
Acknowledge From Master
Acknowledge From Master
No Acknowledge From Master
tph
Read From Port 0
tps
Data Into Port 0
Data 00
Data 01
Data 02
Data 03
Read From Port 1
tph
tps
Data Into Port 1
Data 10
Data 11
Data 12
INT
tiv
tir
A.
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register). This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from P port. See Figure 8 for these details.
B.
Figure 10. Read Input Port Register, Scenario 2
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PCA9535 REMOTE 16-BIT AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS I2C
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005 (1)
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN VCC VI VO IIK IOK IIOK IOL IOH ICC Supply voltage range Input voltage range (2) Output voltage range (2) VI < 0 VO < 0 VO < 0 or VO > VCC VO = 0 to VCC VO = 0 to VCC Input clamp current Output clamp current Input/output clamp current Continuous output low current Continuous output high current Continuous current through GND Continuous current through VCC DB package DBQ package DGV package JA Package thermal impedance (3) DW package N package PW package RGE package RHL package Tstg (1) (2) (3) Storage temperature range -65 -0.5 -0.5 -0.5 MAX 6 6 6 -20 -20 20 50 -50 -200 160 63 61 86 46 67 88 TBD TBD 150 C C/W UNIT V V V mA mA mA mA mA mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature SCL, SDA A2-A0, P07-P00, P17-P10 SCL, SDA A2-A0, P07-P00, P17-P10 P07-P00, P17-P10 P07-P00, P17-P10 -40 2.3 0.7 x VCC 0.7 x VCC -0.5 -0.5 MAX 5.5 5.5 5.5 0.3 x VCC 0.3 x VCC -10 25 85 UNIT V V V mA mA C
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PCA9535 REMOTE 16-BIT I2C AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
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Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VPOR Input diode clamp voltage Power-on reset voltage TEST CONDITIONS II = -18 mA VI = VCC or GND, IO = 0 IOH = -8 mA VOH P-port high-level output voltage (2) IOH = -10 mA SDA IOL P port (3) INT II IIH IIL SCL, SDA A2-A0 P port P port Operating mode ICC Standby mode VI = GND, IO = 0, I/O = inputs, fSCL = 0 kHz One input at VCC - 0.6 V, Other inputs at VCC or GND VI = VCC or GND VIO = VCC or GND VOL = 0.4 V VOL = 0.5 V VOL = 0.7 V VOL = 0.4 V VI = VCC or GND VI = VCC VI = GND VI = VCC or GND, IO = 0, I/O = inputs, fSCL = 400 kHz VCC 2.3 V to 5.5 V VPOR 2.3 V 3V 4.75 V 2.3 V 3V 4.75 V 2.3 V to 5.5 V 2.3 V to 5.5 V 2.3 V to 5.5 V 2.3 V to 5.5 V 2.3 V to 5.5 V 2.3 V to 5.5 V 2.3 V to 5.5 V 5.5 V 3.6 V 2.7 V 5.5 V 3.6 V 2.7 V 2.3 V to 5.5 V 2.3 V to 5.5 V 2.3 V to 5.5 V 3 3 3.7 100 30 20 0.5 0.4 0.25 1.8 2.6 4.1 1.7 2.5 4 3 8 10 3 1 1 1 -1 200 75 50 1 0.9 0.8 200 7 7 9.5 A pF pF A A A A 20 24 mA V MIN -1.2 1.5 1.65 TYP (1) MAX UNIT V V
ICC CI Cio (1) (2) (3)
Additional current in standby mode SCL SDA P port
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25C. Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07-P00 and P17-P10) must be limited to a maximum current of 100 mA, for a device total of 200 mA. The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07-P00 and 80 mA for P17-P10).
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PCA9535 REMOTE 16-BIT AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS I2C
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 11)
MIN fscl tsch tscl tsp tsds tsdh ticr ticf tocf tbuf tsts tsth tsps tvd(Data) tvd(ack) Cb (1) I2C clock frequency I2C clock high time I2C clock low time I2C spike time I2C serial-data setup time I2C serial-data hold time I2C input rise time I2C input fall time I2C output fall time 10-pF to 400-pF bus I2C bus free time between Stop and Start I2C Start or repeated Start condition setup I2C Start or repeated Start condition hold I2C Stop condition setup SCL low to SDA output valid ACK signal from SCL low to SDA (out) low Valid-data time Valid-data time of ACK condition I2C bus capacitive load Cb = total capacitance of one bus line in pF 100 0 20 + 0.1Cb (1) 20 + 0.1Cb (1) 20 + 0.1Cb
(1)
MAX 400
UNIT kHz s s
0 0.6 1.3
50
ns ns ns
300 300 300
ns ns ns s s s s ns
1.3 0.6 0.6 0.6 50 0.1 0.9 400
s pF
Switching Characteristics
over recommended operating free-air temperature range, CL 100 pF (unless otherwise noted) (see Figure 12 and Figure 13)
PARAMETER tiv tir tpv tps tph Interrupt valid time Interrupt reset delay time Output data valid Input data setup time Input data hold time FROM (INPUT) P port SCL SCL P port P port TO (OUTPUT) INT INT P port SCL SCL 150 1 MIN MAX 4 4 200 UNIT s s ns ns s
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PCA9535 REMOTE 16-BIT I2C AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
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TYPICAL OPERATING CHARACTERISTICS
TA = 25C (unless otherwise noted)
SUPPLY CURRENT vs TEMPERATURE
55 50 45 V CC = 5 V
STANDBY SUPPLY CURRENT vs TEMPERATURE
30 SCL = V CC 25 ICC - Supply Current - nA
ICC - Supply Current - A
40 35 30 25 20 15 10 5 0 -50 V CC = 2.5 V V CC = 3.3 V f SCL = 400 kHz I/Os Unloaded
20 V CC = 5 V 15 V CC = 3.3 V 10
5
V CC = 2.5 V
-25
0
25
50
75
100
TA - Free-Air Tem perature - C
0 -50
-25
0
25
50
75
100
TA - Free-Air Tem perature - C
SUPPLY CURRENT vs SUPPLY VOLTAGE
I/O SINK CURRENT vs OUTPUT LOW VOLTAGE
70 60 f SCL = 400 kHz I/Os Unloaded
30 V CC = 2.5 V 25 ISINK - I/O Sink Current - mA TA = -40C 20 TA = 25C 15
ICC - Supply Current - A
50 40 30 20 10 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
10 TA = 125C 5
0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 V OL - Output Low Voltage - V
V CC - Supply Voltage - V
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PCA9535 REMOTE 16-BIT AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS I2C
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
TYPICAL OPERATING CHARACTERISTICS (continued)
TA = 25C (unless otherwise noted)
I/O SINK CURRENT vs OUTPUT LOW VOLTAGE I/O SINK CURRENT vs OUTPUT LOW VOLTAGE
40 V CC = 3.3 V 35 TA = -40C
ISINK - I/O Sink Current - mA
50 45 40
ISINK - I/O Sink Current - mA
V CC = 5 V TA = -40C
30 25 TA = 25C 20 15 10 TA = 125C 5 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 V OL - Output Low Voltage - V
35 30 25 20 15 10 5 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 V OL - Output Low Voltage - V TA = 125C TA = 25C
I/O OUTPUT LOW VOLTAGE vs TEMPERATURE
300 275 250
V OL - Output Low Voltage - mV
I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE
35
V CC = 2.5 V, ISINK = 10 m A
V CC = 2.5 V
ISOURCE - I/O Source Current - mA
30 TA = -40C 25 20 15 10 TA = 125C 5 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 TA = 25C
225 200 175 150 125 100 75 50 25 0 -50 V CC = 2.5 V, ISINK = 1 m A V CC = 5 V, ISINK = 1 m A V CC = 5 V, ISINK = 10 m A
-25
0
25
50
75
100
(V CC - V OH) - V
TA - Free-Air Tem perature - C
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PCA9535 REMOTE 16-BIT I2C AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
www.ti.com
TYPICAL OPERATING CHARACTERISTICS (continued)
TA = 25C (unless otherwise noted)
I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE
50 45 V CC = 3.3 V TA = -40C TA = 25C
ISOURCE - I/O Source Current - mA
75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 0.0
V CC = 5 V TA = -40C
ISOURCE - I/O Source Current - mA
40 35 30 25 20 15 10 5 0 0.0 0.1 0.2 0.3
TA = 25C
TA = 125C
TA = 125C
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.4
0.5
0.6
0.7
(V CC - V OH) - V
(V CC - V OH) - V
I/O HIGH VOLTAGE vs TEMPERATURE
OUTPUT HIGH VOLTAGE vs SUPPLY VOLTAGE
300 275
6 TA = 25C
V OH - Output High Voltage - mV
225 200 175 150 125 100 75 50 25 0 -50 V CC = 5 V, IOL = 10 m A
V OH - Output High Voltage - V
250
V CC = 2.5 V, IOL = 10 m A
5
4 IOH = -8 m A 3 IOH = -10 m A 2
1
0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
-25
0
25
50
75
100
V CC - Supply Voltage - V
TA - Free-Air Tem perature - C
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PCA9535 REMOTE 16-BIT AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS I2C
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
PARAMETER MEASUREMENT INFORMATION
VCC
RL = 1 k DUT SDA CL = 50 pF (see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete Device Programming Stop Condition (P) Start Address Address Condition Bit 7 Bit 6 (S) (MSB) tscl tsch 0.7 x VCC SCL ticr tbuf SDA ticf tsth Start or Repeat Start Condition VOLTAGE WAVEFORMS ticr tsds tsdh Repeat Start Condition tsps Stop Condition ticf tsp tPHL tPLH 0.7 x VCC 0.3 x VCC tsts 0.3 x VCC Address Bit 1 R/W Bit 0 (LSB) ACK (A) Data Bit 7 (MSB) Data Bit 0 (LSB) Stop Condition (P)
BYTE 1 2, 3
DESCRIPTION I2C address P-port data
A. B. C.
CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. All parameters and waveforms are not applicable to all devices.
Figure 11. I2C Interface Load Circuit and Voltage Waveforms
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PCA9535 REMOTE 16-BIT I2C AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
VCC
RL = 4.7 k DUT INT CL = 100 pF (see Note A)
INTERRUPT LOAD CONFIGURATION
ACK From Slave Start Condition Slave Address S 0 1 0 0 A2 A1 A0 1 A R/W 8 Bits (One Data Byte) From Port Data 1
ACK From Slave Data From Port A Data 2 1 P
1
2
3
4
5
6
7
8
A
A
tir
tir
B B
INT A A Data Into Port Address Data 1 tsps Data 2
tiv
0.7 x VCC INT 0.3 x VCC tiv 0.7 x VCC 0.3 x VCC View A-A
SCL
0.7 x VCC R/W A 0.3 x VCC tir
Pn
INT
0.7 x VCC 0.3 x VCC View B-B
A. B. C.
CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. All parameters and waveforms are not applicable to all devices.
Figure 12. Interrupt Load Circuit and Voltage Waveforms
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PCA9535 REMOTE 16-BIT AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS I2C
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Pn DUT CL = 50 pF (see Note A) 500 W 500 W 2 x VCC
P-PORT LOAD CONFIGURATION
SCL
0.7 x VCC P0 A Slave ACK P3 0.3 x VCC
SDA tpv (see Note B)
Pn
WRITE MODE (R/W = 0)
SCL
P0 tps
Pn
READ MODE (R/W = 1)
A. B. C. D. E.
CL includes probe and jig capacitance. tpv is measured from 0.7 x VCC on SCL to 50% I/O (Pn) output. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. The outputs are measured one at a time, with one transition per measurement. All parameters and waveforms are not applicable to all devices.
Figure 13. P-Port Load Circuit and Voltage Waveforms

A
Unstable Data
Last Stable Bit
0.7 x VCC P3 tph 0.7 x VCC 0.3 x VCC 0.3 x VCC
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PCA9535 REMOTE 16-BIT I2C AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
VCC
RL = 1 k DUT SDA CL = 50 pF (see Note A)
Pn DUT CL = 50 pF (see Note A)
500 W
2 x VCC
500 W
SDA LOAD CONFIGURATION
P-PORT LOAD CONFIGURATION
Start SCL ACK or Read Cycle
SDA
0.3 y VCC tRESET
RESET tREC tw
VCC/2
Pn
VCC/2 tRESET
A. B. C. D. E.
CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. The outputs are measured one at a time, with one transition per measurement. I/Os are configured as inputs. All parameters and waveforms are not applicable to all devices.
Figure 14. Reset Load Circuits and Voltage Waveforms
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PCA9535 REMOTE 16-BIT AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS I2C
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
APPLICATION INFORMATION
Figure 15 shows an application in which the PCA9535 can be used.
Subsystem 1 (e.g., Temperature Sensor) INT VCC (5 V) VCC SCL Master Controller SDA INT GND 10 kW 10 kW 10 kW 10 kW 22 23 1 24 VDD SCL SDA INT P00 P01 P02 P03 P04 P05 PCA9535 VCC P06 P07 3 A2 P10 P11 2 A1 P12 P13 21 A0 P14 P15 P16 GND P17 12 10 11 13 14 15 16 17 18 19 20 Controlled Switch (e.g., CBT Device) 4 5 6 7 8 9 ENABLE B 2 kW 100 kW 100 kW 100 kW Subsystem 2 (e.g., Counter) RESET A
ALARM Keypad Subsystem 3 (e.g., Alarm)
A. B. C. D.
Device address is configured as 0100100 for this example. P00, P02, and P03 are configured as outputs. P01, P04-P07, and P10-P17 are configured as inputs. Pin numbers shown are for DB, DBQ, DGV, DW, N, PW, and RHL packages.
Figure 15. Typical Application
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PCA9535 REMOTE 16-BIT I2C AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
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APPLICATION INFORMATION (continued) Minimizing ICC When the I/O Is Used to Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in Figure 15. Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ICC parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. For battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC, when the LED is off, to minimize current consumption. Figure 16 shows a high-value resistor in parallel with the LED. Figure 17 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional supply-current consumption when the LED is off.
VCC
LED VCC LEDx
100 kW
Figure 16. High-Value Resistor in Parallel With LED
3.3 V 5V
VCC LEDx
LED
Figure 17. Device Supplied by Lower Voltage
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PCA9535 REMOTE 16-BIT AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS I2C
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
THERMAL PAD MECHANICAL DATA RGE (S-PQFP-N24)
25
PCA9535 REMOTE 16-BIT I2C AND SMBus, LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS129A - AUGUST 2005 - REVISED DECEMBER 2005
www.ti.com
THERMAL PAD MECHANICAL DATA RHL (S-PQFP-N24)
26
PACKAGE OPTION ADDENDUM
www.ti.com
14-Dec-2005
PACKAGING INFORMATION
Orderable Device PCA9535DB PCA9535DBQR PCA9535DBR PCA9535DGVR PCA9535DW PCA9535DWR PCA9535PW PCA9535PWE4 PCA9535PWR PCA9535PWRE4 PCA9535RGER PCA9535RHLR
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PREVIEW PREVIEW
Package Type SSOP SSOP/ QSOP SSOP TVSOP SOIC SOIC TSSOP TSSOP TSSOP TSSOP QFN QFN
Package Drawing DB DBQ DB DGV DW DW PW PW PW PW RGE RHL
Pins Package Eco Plan (2) Qty 24 24 24 24 24 24 24 24 24 24 24 24 60 Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI Call TI
MSL Peak Temp (3) Level-1-260C-UNLIM Level-2-260C-1YEAR Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Call TI Call TI
2500 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 25 Green (RoHS & no Sb/Br)
2000 Green (RoHS & no Sb/Br) 60 60 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 3000 1000 TBD TBD
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C - FEBRUARY 1996 - REVISED AUGUST 2000
DGV (R-PDSO-G**)
24 PINS SHOWN 0,23 0,13 13
PLASTIC SMALL-OUTLINE
0,40 24
0,07 M
0,16 NOM 4,50 4,30 6,60 6,20
Gage Plane
0,25 0- 8 1 A 12 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,08
PINS ** DIM A MAX A MIN
14 3,70 3,50
16 3,70 3,50
20 5,10 4,90
24 5,10 4,90
38 7,90 7,70
48 9,80 9,60
56 11,40 11,20
4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins - MO-153 14/16/20/56 Pins - MO-194
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001
DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 0- 8 0,25 0,95 0,55
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 /E 12/01
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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