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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Multiplexer - Demultiplexer
The MC74VHC1G54 is an advanced high speed CMOS multiplexer - demultiplexer analog switch fabricated with silicon gate CMOS technology. It achieves high speed propagation delays and low ON resistances while maintaining CMOS low power dissipation. This multiplexer - demultiplexer controls analog and digital voltages that may vary across the full power-supply range (from VCC to GND). The device has been designed so that the ON resistances (RON) are much lower and more linear over input voltage than RON of the typical metal-gate CMOS or High Speed CMOS analog switches. The ON/OFF control inputs are compatible with standard CMOS outputs; with pull-up resistors, it is compatible with LSTTL outputs. * * * * * * Fast Switching and Propagation Speeds Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C Diode Protection Provided on Channel Select Input Improved Linearity and Lower ON Resistance over Input Voltage Latchup Performance Exceeds 300 mA ESD Performance: HBM > 2000 V; MM > 200 V, CDM > 1500 V
MC74VHC1G54
PLANNED PACKAGE 6-LEAD TSSOP Tamb = -55C to 125C
FUNCTION TABLE
Select L H ON Channel X0 X1
CHANNEL SELECT 1 VCC 2 GND 3
6 IN/OUT X1 5 OUT/IN X 4 IN/OUT X0
PIN ASSIGNMENT
V Vd CHANNEL SELECT OUT/IN X U 2X0 2X1
LOGIC SYMBOL
DEVICE ORDERING INFORMATION
Device Nomenclature Motorola Circuit Indicator MC MC Temp Range Identifier 74 74 Device Function 54 54 Package Suffix DT DT Tape and Reel Suffix T1 T3 Package Pk Type TSOP6 TSOP6 Tape and R l T d Reel Size 7-Inch/3000 Unit 13-Inch/ 10000 Unit
Device Order Number D i Od N b MC74VHC1G54DTT1 MC74VHC1G54DTT3
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
10/98
(c) Motorola, Inc. 1998
1
U U
IN/OUT X0 IN/OUT X1
Pin 1
MARKING DIAGRAM d = date code
Technology VHC1G VHC1G
REV 0
MC74VHC1G54
ABSOLUTE MAXIMUM RATINGS Maximum ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions.
Characteristics DC Supply Voltage Digital Input Voltage Analog Input Voltage Digital Input Diode Current DC Supply Current, VCC and GND Power dissipation in still air, TSOP6 Lead temperature, 1 mm from case for 10 s Storage temperature Symbol VCC VIN VIS IIK ICC PD TL Tstg Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC + 0.5 -20 25 450 260 -65 to +150 Unit V V V mA mA mW C C
Power Dissipation Derating: TSOP6 Package: - 6 mW/_C from 65_C to 125_C
RECOMMENDED OPERATING CONDITIONS
Characteristics DC Supply Voltage Digital Input Voltage Analog Input Voltage Static or Dynamic Voltage Across Switch Operating Temperature Range Input Rise and Fall Time, SELECT & ENABLE Symbol VCC VIN VIS VIO* TA tr, tf Min 2.0 GND GND -- -55 Max 5.5 VCC VCC 100 +125 Unit V V V mV C ns/V
VCC = 3.3 V 0.3 V 0 100 VCC = 5.0 V 0.5 V 0 20 * For voltage drops across the switch greater than 100 mV (switch on), excessive VCC current may be drawn; i.e. the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
MOTOROLA
2
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74VHC1G54
DC ELECTRICAL CHARACTERISTICS
VCC Symbol VIH Parameter Minimum High-Level Input Voltage Channel Select Input Maximum Low-Level Input Voltage Channel Select Input Maximum Input Leakage Current Channel Select Input Maximum Quiescent Supply Current Maximum "ON" Resistance Test Conditions RON = Per Spec (V) 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 0 to 5.5 5.5 2.0 3.0 4.5 2.0 3.0 4.5 4.5 5.5 4.5 5.5 4.5 5.5 25 12 5 25 12 5 Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 0.1 TA = 25C Typ Max TA 85C Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 1.0 Max TA 125C Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 1.0 Max Unit V
VIL
RON = Per Spec
V
IIN
VIN = VCC or GND
A
ICC RON
VIN = VCC or GND VIO = 0 V VIN = VIH VIS = VCC to GND IIS 20 mA (Figure 1) Endpoints VIN = VIH VIS = VCC to GND IIS 20 mA (Figure 1)
2.0 50 20 10 50 20 10 0.1 0.5 0.1 0.5 0.2 1.0
20 70 30 15 65 26 13 5.0 10 5.0 10 10 20
40 100 45 25 90 40 22 10 20 10 20 20 40
A
W W
IOFF
Maximum Off-Channel Leakage Current, Any One Channel Maximum Off-Channel Leakage Current, Common Channel
VIN = VIL VIO = VCC to GND Switch Off (Figure 2) VIN = VIL VIO = VCC to GND Switch Off (Figure 3) VIN = VIH VIS = VCC to GND (Figure 4)
nA
nA
ION
Maximum On-Channel Leakage Current
nA
II I I I I IIIIIIIIIIIIIIIII IIIIIIIIIIIIIII III I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII I I I
Symbol Parameter Test Conditions Typ 1.0 Max 5.0 Unit mV Vout Maximum Shift of Output Voltage of Enabled Analog Channel (Figure 7) Iin 10 mA, RS 10 k CL = 1000 pF 1. Iin = Total current injected into disabled channel. To express Injection Current Coupling in terms of charge: Q = Vout CL where Q is in pC, Vout is in V and CL is in pF. VHC Data - Advanced CMOS Logic DL203 -- Rev 1 3 MOTOROLA
INJECTION CURRENT COUPLING SPECIFICATIONS (VCC = 5.0 V, TA = 25C)
MC74VHC1G54
II I I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II I I I I I I I I IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIII I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, Input tr/tf = 3.0 ns)
Symbol S bl Parameter P Test C di i T Conditions VCC (V) 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 0.0 5.0 TA = 25C Typ 1 0 0 0 TA 85C TA 125C Min Max 5 2 1 1 Min Max 6 3 1 1 Min Max 7 4 2 1 Unit Ui ns tPLH, tPHL Maximum Propagation Delay, Input X to X0 or X1 Maximum Propagation Delay, SELECT to Analog Output Maximum Input Capacitance Figure 5 tPLH, tPHL Figure 6 15 8 6 4 3 35 15 10 7 10 15 15 50 46 20 13 9 10 20 20 50 57 25 17 11 10 20 20 50 ns CIN Channel Select Input pF Analog I/O Common O/I Feedthrough Channel Select = GND 8 8 20 Typical @ 25C, VCC = 5.0 V 18 CPD Power Dissipation C P Di i i Capacitance ( i (per S i h) (N Switch) (Note 1) Fi Figure 8 pF F 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
II II I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I II I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol Parameter Test Conditions VCC 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 Limit { 25C 150 175 200 -90 -90 -90 -80 -80 -80 Unit BW Maximum On-Channel Bandwidth or Minimum Frequency Response Figure 9 fin = 1 MHz Sine Wave Adjust fin voltage to obtain 0 dBm at VOS Increase fin = frequency until dB meter reads -3 dB RL = 50 W, CL = 10 pF fin = Sine Wave Adjust fin voltage to obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF fin = 1.0 MHz, RL = 50 W, CL = 10 pF MHz ISOoff Off-Channel Feedthrough Isolation Figure 10 dB NOISEfeed Feedthrough Noise Channel Select to Switch Figure 11 Vin 1 MHz Square Wave (tr = tf = 2 ns) Adjust RL at setup so that Is = 0 A RL = 600 W, CL = 50 pF RL = 50 W, CL = 10 pF 45 60 100 25 30 60 mVPP THD Total Harmonic Distortion Figure 12 fin = 1 kHz, RL = 10 kW, CL = 50 pF THD = THDMeasured - THDSource VIS = 3.0 VPP sine wave VIS = 4.0 VPP sine wave VIS = 5.0 VPP sine wave % 3.3 4.5 5.5 0.20 0.10 0.06 Guaranteed limits not tested. Determined by design and verified by qualification. MOTOROLA 4 VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74VHC1G54
PLOTTER DC PARAMETER ANALYZER POWER SUPPLY + VCC 1 2 3 6 5 4 VIH - 1 VCC 2 3 5 4 6 VCC A
COMPUTER
Figure 1. On Resistance Test Set-Up
Figure 2. Maximum Off-Channel Leakage Current Test Set-Up, Any One Channel
VCC 1 VCC 2 3 5 4 6 A 1 2 1 2 VCC VCC VCC 2 3 5 4 A N/C VCC 1 6
Figure 3. Maximum Off-Channel Leakage Current Test Set-Up, Common Channel
Figure 4. Maximum On-Channel Leakage Current Test Set-Up
VCC 1 2 3 6 5 CL 4 VCC 3 4 Test Point 1 VCC 2 5 6
VCC Test Point
VCC
CL
Figure 5. Propagation Delay Test Set-Up, Analog I/O to Analog I/O
Figure 6. Propagation Delay Test Set-Up, Channel Select to Analog I/O
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
5
MOTOROLA
MC74VHC1G54
VCC 1 2 1 2 3 Test Point RS 1 2 CL* 4 1 2 *Includes all probe and jig capacitance. RS A IIN 1 VCC 2 3 5 4 N/C 6 VCC A
VCC
6 5
Figure 7. Injection Current Coupling Test Set-Up
Figure 8. Power Dissipation Capacitance Test Set-Up
VCC
VCC fin
VCC
1 2 3
6 5
VOS CL*
VCC
1 2
6 5
VOS CL*
0.1 mF
4
dB Meter 0.1 mF fin
3
4
dB Meter RL
VIS
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 9. Maximum On-Channel Bandwidth Test Set-Up
V tr VCC GND 1 VCC 2 3 5 RL 4 RL CL* 3 6 RL Test Point VCC 1 2
Figure 10. Off-Channel Feedthrough Isolation Test Set-Up
IN
v 1 MHz + tf + 2 ns
6 5 CL* 4 RL VOS
VCC fin 0.1 mF
To Distortion Meter
VIS RL
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 11. Feedthrough Noise, Channel Select to Analog Out, Test Set-Up
Figure 12. Total Harmonic Distortion Test Set-Up
MOTOROLA
6
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74VHC1G54 INFORMATION FOR USING THE TSOP-6 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.094 2.4
interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95 0.074 1.9 0.037 0.95 0.028 0.7 0.039 1.0 inches mm
TSOP-6
TSOP-6 POWER DISSIPATION
The power dissipation of the TSOP-6 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA . Using the values provided on the data sheet for the TSOP-6 package, PD can be calculated as follows: PD = TJ(max) - TA RJA
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 450 milliwatts. PD = 125C - 25C 225C/W = 450 milliwatts
The 225C/W for the TSOP-6 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 450 milliwatts. There are other alternatives to achieving higher power dissipation from the TSOP-6 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal CladTM. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
7
MOTOROLA
MC74VHC1G54
TSOP-6 Tape and Reel Options
B F E J AA H
QL
A
C
G
D T
K
AA
K SECTION A-A
M
N V
L
PACKAGE ORIENTATION
P DEVICE
QUANTITY PER REEL REEL SIZE 7-inches 13-inches T3 Inches Min 0.303 0.065 0.122 0.120 0.154 0.154 0.122 0.007 0.059 0.051 0.039 6.929 -- 0.059 0.504 0.846 0.039 2.087 0.311 Max 0.327 0.073 0.130 0.128 0.161 0.161 0.130 0.009 0.063 0.059 0.043 7.087 3 0.098 0.520 0.886 0.078 2.126 0.350 Millimeters Min 7.70 1.65 3.10 3.05 3.90 3.90 3.10 0.17 1.50 1.30 1.00 328 -- 1.50 12.8 21.5 1.00 53.0 24.4 Max 8.30 1.85 3.30 3.25 4.10 4.10 3.30 0.23 1.60 1.50 1.10 332 3 2.50 13.2 22.5 2.00 54.0 16.4 Min 0.303 0.065 0.122 0.120 0.154 0.154 0.122 0.007 0.059 0.051 0.039 12.91 -- 0.059 0.504 0.847 0.039 2.087 0.961 Inches Max 0.327 0.073 0.130 0.128 0.161 0.161 0.130 0.009 0.063 0.059 0.043 13.07 3 0.098 0.520 0.886 0.078 2.126 1.039 QUANTITY 3,000 10,000
MGSF34xxX-T1 W T1 Millimeters Dim Di A B C D E F G H J K K L Min 7.70 1.65 3.10 3.05 3.90 3.90 3.10 0.17 1.50 1.30 1.00 170 -- 1.50 12.8 21.5 1.00 53.0 7.90 Max 8.30 1.85 3.30 3.25 4.10 4.10 3.30 0.23 1.60 1.50 1.10 180 3 2.50 13.2 22.5 2.00 54.0 8.90 MGSF34xxX-T3
QL
M N P T V W
MOTOROLA
8
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74VHC1G54
OUTLINE DIMENSIONS
PLANNED PACKAGE 6-Lead TSSOP Tamb = -55C to 125C
A L
6 5 1 2 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. DIM A B C D G H J K L M S MILLIMETERS MIN MAX 2.90 3.10 1.30 1.70 0.90 1.10 0.25 0.50 0.85 1.05 0.013 0.100 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 INCHES MIN MAX 0.1142 0.1220 0.0512 0.0669 0.0354 0.0433 0.0098 0.0197 0.0335 0.0413 0.0005 0.0040 0.0040 0.0102 0.0079 0.0236 0.0493 0.0610 0_ 10 _ 0.0985 0.1181
S
3
B
D G M 0.05 (0.002) H C K J
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VHC Data - Advanced CMOS Logic DL203 -- Rev 1 9
MC74VHC1G54/D MOTOROLA

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