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MC10EP56
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Dual Differential 2:1 Multiplexer
The MC10EP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided to ease AC coupling of input signals. If used, the VBB output should be bypassed to ground with a 0.01F capacitor. The device features both individual and common select inputs to address both data path and random logic applications.
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* * * * * * * * * * * * * *
350ps Typical Propagation Delays Typical Frequency 3.0GHz 20-Lead TSSOP Package PECL mode: 3.0V to 5.5V VCC with VEE = 0V ECL mode: 0V VCC with VEE = -3.0V to -5.5V Separate and Common Select Internal Input Resistors: Pulldown on D, D Q Output will default LOW with inputs open or at VEE ESD Protection: >4KV HBM, >200V MM VBB Outputs New Differential Input Common Mode Range Moisture Sensitivity Level 1, Indefinite Time Out of Drypack. For Additional Information, See Application Note AND8003/D Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34 Transistor Count = 140 devices
COM_SEL
TSSOP-20 DT SUFFIX CASE 948E
MARKING DIAGRAM*
A L Y W = Assembly Location = Wafer Lot = Year = Work Week
MC10 EP56 ALYW
*For additional information, see Application Note AND8002/D
PIN DESCRIPTION
PIN D0a-D1a D0a-D1a D0b-D1b D0b-D1b SEL0-SEL1 COM_SEL VBB0, VBB1 Q0-Q1 Q0-Q1 VCC VEE FUNCTION ECL Input Data a ECL Input Data a Invert ECL Input Data b ECL Input Data b Invert ECL Indiv. Select Input ECL Common Select Input Output Reference Voltage ECL True Outputs ECL Inverted Outputs Positive Supply Negative, 0 Supply
VCC 20
Q0 19
Q0 18
SEL0 17
SEL1 VCC 15 14
Q1 13
Q1 12
VEE 11
16
TRUTH TABLE
1 0 1 0 SEL0 X L L H H SEL1 X L H H L COM_SEL H L L L L Q0, Q0 a b b a a Q1, Q1 a b a a b
1 D0a
2 D0a
3
4
5 D0b
6 D1a
7 D1a
8
9
10 D1b
VBBO D0b
VBB1 D1b
Figure 1. 20-Lead TSSOP (Top View) and Logic Diagram
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
ORDERING INFORMATION
Device MC10EP56DT MC10EP56DTR2 Package TSSOP TSSOP Shipping 75 Units/Rail 2500 Tape & Reel
(c) Semiconductor Components Industries, LLC, 1999
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January, 2000 - Rev. 2
Publication Order Number: MC10EP56/D
MC10EP56
MAXIMUM RATINGS*
Symbol VEE VCC VI VI Iout IBB TA Tstg JA JC Tsol Power Supply (VCC = 0V) Power Supply (VEE = 0V) Input Voltage (VCC = 0V, VI not more negative than VEE) Input Voltage (VEE = 0V, VI not more positive than VCC) Output Current VBB Sink/Source Current{ Operating Temperature Range Storage Temperature Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Solder Temperature (<2 to 3 Seconds: 245C desired) Still Air 500lfpm Continuous Surge Parameter Value -6.0 to 0 6.0 to 0 -6.0 to 0 6.0 to 0 50 100 0.5 -40 to +85 -65 to +150 140 100 23 to 41 5% 265 Unit VDC VDC VDC VDC mA mA C C C/W C/W C
* Maximum Ratings are those values beyond which damage to the device may occur. { Use for inputs of same package only.
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V; VEE = -5.5V to -3.0V) (Note 4.)
-40C Symbol IEE VOH VOL VIH VIL VBB Characteristic Power Supply Current (Note 1.) Output HIGH Voltage (Note 2.) Output LOW Voltage (Note 2.) Input HIGH Voltage Single Ended Input LOW Voltage Single Ended Output Voltage Reference Min 50 -1135 -1935 -1210 -1935 -1510 -1410 Typ 65 -1060 -1810 Max 88 -885 -1685 -885 -1610 -1310 0.0 150 0.5 -150 0.5 -150 Min 50 -1070 -1870 -1145 -1870 -1445 -1345 25C Typ 65 -945 -1745 Max 88 -820 -1620 -820 -1545 -1245 0.0 150 0.5 -150 Min 50 -1010 -1810 -1085 -1810 -1385 -1285 85C Typ 65 -885 -1685 Max 88 -760 -1560 -760 -1485 -1185 0.0 150 Unit mA mV mV mV mV mV V A A
VIHCMR Input HIGH Voltage Common Mode Range (Note 3.) IIH IIL Input HIGH Current Input LOW Current SEL, COM_SEL, D D
VEE+2.0
VEE+2.0
VEE+2.0
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 1. VCC = 0V, VEE = VEEmin to VEEmax, all other pins floating. 2. All loading with 50 ohms to VCC-2.0 volts. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 4. Input and output parameters vary 1:1 with VCC.
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MC10EP56
DC CHARACTERISTICS, LVPECL (VCC = 3.3V 0.3V, VEE = 0V) (Note 8.)
-40C Symbol IEE VOH VOL VIH VIL VBB Characteristic Power Supply Current (Note 5.) Output HIGH Voltage (Note 6.) Output LOW Voltage (Note 6.) Input HIGH Voltage Single Ended Input LOW Voltage Single Ended Output Voltage Reference Min 50 2165 1365 2090 1365 1790 2.0 1890 Typ 65 2240 1490 Max 88 2415 1615 2415 1690 1990 3.3 150 0.5 -150 0.5 -150 Min 50 2230 1430 2155 1430 1855 2.0 1955 25C Typ 65 2355 1555 Max 88 2480 1680 2480 1755 2055 3.3 150 0.5 -150 Min 50 2290 1490 2215 1490 1915 2.0 2015 85C Typ 65 2415 1615 Max 88 2540 1740 2540 1815 2115 3.3 150 Unit mA mV mV mV mV mV V A A
VIHCMR Input HIGH Voltage Common Mode Range (Note 7.) IIH IIL Input HIGH Current Input LOW Current SEL, COM_SEL, D D
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 5. VCC = 3.3V, VEE = 0V, all other pins floating. 6. All loading with 50 ohms to VCC-2.0 volts. 7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 8. Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, PECL (VCC = 5.0V 0.5V, VEE = 0V) (Note 12.)
-40C Symbol IEE VOH VOL VIH VIL VBB Characteristic Power Supply Current (Note 9.) Output HIGH Voltage (Note 10.) Output LOW Voltage (Note 10.) Input HIGH Voltage Single Ended Input LOW Voltage Single Ended Output Voltage Reference Min 50 3865 3065 3790 3065 3490 2.0 3590 Typ 65 3940 3190 Max 88 4115 3315 4115 3390 3690 5.0 150 0.5 -150 0.5 -150 Min 50 3930 3130 3855 3130 3555 2.0 3655 25C Typ 65 4055 3255 Max 88 4180 3380 4180 3455 3755 5.0 150 0.5 -150 Min 50 3990 3190 3915 3190 3615 2.0 3715 85C Typ 65 4115 3315 Max 88 4240 3440 4240 3515 3815 5.0 150 Unit mA mV mV mV mV mV V A A
VIHCMR Input HIGH Voltage Common Mode Range (Note 11.) IIH IIL Input HIGH Current Input LOW Current SEL, COM_SEL, D D
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 9. VCC = 5.0V, VEE = 0V, all other pins floating. 10. All loading with 50 ohms to VCC-2.0 volts. 11. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 12. Input and output parameters vary 1:1 with VCC.
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MC10EP56
AC CHARACTERISTICS (VCC = 0V; VEE = -3.0V to -5.5V) or (VCC = 3.0V to 5.5V; VEE = 0V)
-40C Symbol fmax tPLH, tPHL Characteristic Maximum Toggle Frequency (Note 13.) Propagation Delay to Output Differential D->Q, Q (Diff) D->Q, Q (SE) SEL->Q, Q COM_SEL->Q, Q Within-Device Skew (Note 14.) Duty Cycle Skew (Note 15.) Cycle-to-Cycle Jitter Input Voltage Swing (Diff.) 150 Min Typ Max Min 25C Typ 3.0 Max Min 85C Typ Max Unit GHz ps 250 250 200 200 340 340 340 350 TBD TBD TBD 800 1200 150 480 480 550 580 250 250 200 200 360 360 340 360 TBD TBD TBD 800 1200 150 480 480 550 580 300 300 200 200 400 400 390 400 TBD TBD TBD 800 1200 520 520 650 675 ps ps mV
tSKEW tJITTER VPP
tr Output Rise/Fall Times Q, Q 100 150 200 100 150 200 100 160 220 ps tf (20% - 80%) 13. Fmax guaranteed for functionality only. 14. Within-Device Skew is defined as identical transitions on similar paths through a device. 15. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs.
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MC10EP56
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX 20 PIN PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
K K1
2X
B L
PIN 1 IDENT 1 10
J J1
-U-
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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IIII IIII IIII
SECTION N-N 0.25 (0.010) M DETAIL E
L/2
20
11
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC10EP56
Notes
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MC10EP56
Notes
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MC10EP56
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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MC10EP56/D

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