 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| OCX1601 Crosspoint Switch Features 1.6 Gb/s port data bandwidth, >128Gb/s aggregate bandwidth Low power CMOS, 2.5V and 3.3V power supply SRAM-based, in-system programmable 160 configurable I/O ports - 80 dedicated differential input ports - 80 dedicated differential output ports - Supports LVPECL and LVDS I/O - LVTTL control interface - Output Enable control for all outputs * Non-blocking switch matrix - Patented ActiveArrayTM matrix for superior performance - Double-buffered configuration RAM cells for simultaneous global updates - ImpliedDisconnectTM function for single cycle disconnect/ connect * * * * * Full Broadcast and multicast capability - One-to-One and One-to-Many connections - Special broadcast mode routes one input to all outputs at maximum data rate * Low jitter and signal skew * Low duty cycle distortion * RapidConfigureTM parallel interface for configuration and readback * Serial programming interface for configuration * 420 BGA package with 1.27mm ball spacing * Integrated Termination Resistors Advanced Datasheet Description The OCX1601 SRAM-based device is a non-blocking 80 X 80 digital crosspoint switch capable of data rates of 1.6 Gigabits per second per port. The I/O ports are fixed as either input or output ports. The input ports support flow-through mode only. The output ports operate in flow-through (asynchronous) mode. The patented ActiveArray provides greater density, superior performance, and greater flexibility compared to a traditional n:1 multiplexer architecture. The OCXTM devices support various operating modes covering one input to one output at a time as well as one input to many outputs, plus a special broadcast mode to program one input to all outputs while maintaining maximum data rates. In all modes data integrity and connections are maintained on all unchanged data paths. The RapidConfigure parallel interface allows fast configuration of the Output Buffers and the switch matrix. Readback is supported for device test and verification purposes. The OCX1601 also includes a JTAG-like serial interface for configuration of the device. A functional block diagram of the OCX1601 is shown in Figure 1. Applications * SONET/SDH and DWDM * Digital Cross-Connects * System Backplanes and Interconnects * High Speed Test Equipment 160 OUT[79:0] Input Buffers 80 x 80 Crosspoint Switch Matrix Output Buffers OE# * ATM Switch Cores * Video Switching 160 IN[79:0] RapidConfigure Signals RCA[6:0] 7 RCB[6:0] 7 RCI[3:0] 4 RCO[2:0] 3 RC_CLK# RC_EN# UPDATE# Configuration and Programming Logic SCLK SMS SDI SRST# SDO Serial Programming Interface HW_RST# Figure 1 OCX1601 Functional Block Diagram Fairchild Semiconductor [Rev. 1.8] 3/21/02 1 OCX1601 Crosspoint Switch--Advanced Datasheet (This page intentionally left blank) 2 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet Contents 1. 1.1 Introduction ........................................................................................................................... 7 Input and Output Buffers...................................................................................................... 8 Input and Output Port Function Mode ........................................................................... 8 Broadcast Mode ............................................................................................................. 8 1.1.1 1.1.2 1.2 1.3 Output Control Signals......................................................................................................... 9 RapidConfigure Interface ..................................................................................................... 9 RapidConfigure Programming Instructions.................................................................... 9 1.3.1 1.4 Serial Interface Configuration Controller ........................................................................... 12 Serial Interface ............................................................................................................. 12 Output Port Configuration ........................................................................................... 12 Switch Matrix Configuration ....................................................................................... 12 Mode Control Register Configuration.......................................................................... 12 Serial Interface Architecture ........................................................................................ 13 Serial Interface State Machine ..................................................................................... 14 Serial Input Format ...................................................................................................... 14 Serial Interface Instructions ......................................................................................... 15 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.5 1.6 2. 3. 3.1 3.2 4. 4.1 4.2 4.3 4.4 4.5 4.6 ImpliedDisconnect ............................................................................................................. 17 Device Reset Options ......................................................................................................... 18 Pin Description .....................................................................................................................19 Differential I/O Standards ...................................................................................................20 LVPECL ............................................................................................................................. 20 LVDS ................................................................................................................................. 20 Electrical Specifications .......................................................................................................21 Absolute Maximum Ratings .............................................................................................. 21 Recommended Operating Conditions ................................................................................ 21 Pin Capacitance ................................................................................................................. 21 DC Electrical Specifications .............................................................................................. 22 LVPECL AC Electrical Specifications ............................................................................... 23 Timing Diagrams................................................................................................................ 24 Fairchild Semiconductor [Rev. 1.8] 3/21/02 3 OCX1601 Crosspoint Switch--Advanced Datasheet 5. 5.1 5.2 5.3 6. 6.1 6.2 7. 7.1 8. 9. 10. Pinout.................................................................................................................................... 27 Package Pinout ................................................................................................................... 27 Pinout by Ball Sequence..................................................................................................... 28 Pinout by Ball Name .......................................................................................................... 31 Package Information ........................................................................................................... 33 PB420 Package Information ............................................................................................... 33 Package Thermal Characteristics........................................................................................ 34 Power Consumption ............................................................................................................ 35 Power for LVPECL I/O ..................................................................................................... 35 Component Availability and Ordering Information ......................................................... 36 Glossary ................................................................................................................................ 36 Product Status Definition .................................................................................................... 38 4 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 OCX1601 Functional Block Diagram .................................................................................................. 1 OCX1601 Switch Matrix ...................................................................................................................... 7 Input and Output Buffer Configuration ................................................................................................ 8 OCX1601 Serial Interface Architecture ............................................................................................. 13 OCX1601 Serial Interface State Machine .......................................................................................... 14 OCX1601 Operating in LVPECL Mode ............................................................................................ 20 Flow-Through Mode Timing .............................................................................................................. 24 Output Enable Timing ........................................................................................................................ 24 Duty Cycle Distortion ......................................................................................................................... 24 RapidConfigure Write Cycle .............................................................................................................. 25 RapidConfigure Read Cycle ............................................................................................................... 25 Serial Timing ...................................................................................................................................... 26 Typical Performance........................................................................................................................... 26 OCX1601 Package Pinout .................................................................................................................. 27 OCX1601 Package--Bottom, Top and Side Views ........................................................................... 33 Power Consumption Diagram for the OCX1601 using LVPECL ...................................................... 35 Fairchild Semiconductor [Rev. 1.8] 3/21/02 5 OCX1601 Crosspoint Switch--Advanced Datasheet Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Summary for Programmable I/O Attributes for OCX1601............................................................... 8 RapidConfigure Programming Instructions ...................................................................................... 9 RCO[2:0] Readback Pin Assignment.............................................................................................. 11 Programming an Output Buffer using RapidConfigure .................................................................. 11 Mode Control Register .................................................................................................................... 12 Serial Input Format.......................................................................................................................... 14 Serial Interface Instructions............................................................................................................. 15 Programming an Output using the Serial Interface ......................................................................... 16 Number of Cycles and Configuration Time .................................................................................... 17 Device Reset Options ...................................................................................................................... 18 OCX1601 Pin Description............................................................................................................... 19 Absolute Maximum Ratings1.......................................................................................................... 21 Recommended Operating Conditions.............................................................................................. 21 Pin Capacitance5 ............................................................................................................................. 21 LVTTL DC Electrical Specifications.............................................................................................. 22 LVPECL DC Electrical Specifications ........................................................................................... 22 LVPECL AC Electrical Specifications ........................................................................................... 23 OCX1601 Pinout By Ball Sequence................................................................................................ 28 OCX1601 Pinout By Ball Name ..................................................................................................... 31 Package Thermal Coefficients......................................................................................................... 34 6 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet 1. Introduction The OCX1601 is a differential crosspoint-switching device. The main functional block of the device is a Switch Matrix as shown in Figure 1. The Switch Matrix is a x-y structure supporting an input-to-output data flow. Figure 2 shows a conceptual view of the switch matrix with inputs connected to the horizontal trace and outputs to the vertical trace. Connections between vertical and horizontal lines are implemented with a proprietary highperformance buffering circuit. Signal path delays through the Switch Matrix are very well balanced, resulting in predictable and uniform pin-to-pin delays. Note - For the purpose of clarity, the logic diagrams within this datasheet are conceptual representations only and do not show actual circuit implementation. Data Loading SRAM Cell Active SRAM Cell UPDATE# Proprietary High-performance Buffering Circuit Figure 2 OCX1601 Switch Matrix The Active SRAM cells are responsible for establishing connections in the switch matrix by turning on the interconnect circuit, while the Loading SRAM cell can be used to store a second configuration that can be transferred to the Active SRAM cell at a later time. The two SRAM cells are arranged so that a double buffered scheme can be employed. Through the use of an internal signal (generated automatically during a programming cycle) it is possible to store a second configuration map in the Loading SRAM while the Active SRAM maintains its present connection status. When the UPDATE# signal is asserted low, the contents of the Loading SRAM cell are transferred to the Active SRAM cell and the switch matrix connection is either made or broken. The UPDATE# signal can be used to control when the switch matrix is reconfigured. For instance, as long as the UPDATE# signal is asserted high, the Loading SRAM cells for the entire switch matrix could be changed without affecting the current configuration of the switch. When the UPDATE# signal is asserted low, the entire switch matrix would be reconfigured simultaneously. If the UPDATE# signal is asserted continuously, all crosspoint programming commands (generated by RapidConfigure or Serial programming cycles) will take effect immediately, since the Loading SRAM cell's contents will be transferred directly to the Active SRAM cell. Fairchild Semiconductor [Rev. 1.8] 3/21/02 7 OCX1601 Crosspoint Switch--Advanced Datasheet 1.1 Input and Output Buffers All of the I/O buffers are differential with flow-through mode. Figure 3 shows the basic block diagram of the input and output blocks with the sources for the output control signals (OE#). The control signals are explained in more details in the following sections. Input Switch Matrix OE# Output Figure 3 Input and Output Buffer Configuration 1.1.1 Input and Output Port Function Mode The following legend describes the various modes of the Input and Output Ports and the specification used by the OCXProTM Software. Legend: Ax-Switch Matrix Signal Px-Port Signal OE#-Output Enable (# means "Active Low") Table 1 Symbol Px Ax Summary for Programmable I/O Attributes for OCX1601 I/O Port Function Input - The external signal is buffered from the Input Port pin to the corresponding Switch Matrix line. Mnemonic IN Ax Px Output - The internal signal is buffered from the corresponding Switch Matrix line to the Output Port pin. In this mode an optional output enable (OE#) can be selected. The default state is logic high with enable set to ON. No Connect - In this mode, the output Port pin is isolated from the Switch Matrix. OP OE# NC Ax Px 1.1.2 Broadcast Mode The OCX1601 has a special Broadcast Mode which connects any input to all outputs without performance degradation. The input is selected using RapidConfigure or Serial interface and disconnects all other inputs. The Global Update pin (UPDATE#) must be held high during Broadcast Mode. Asserting the UPDATE# pin returns the array to the previous program condition. 8 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet 1.2 Output Control Signals Every output port of the OCX1601 has a global Output Enable signal (OE#). All output buffers have output enables that have programmable polarity and are individually configurable. Additionally each output can be permanently enabled (always ON) or disabled (always OFF) which is useful for applications which need to tri-state outputs (for example when using multiple chips in expansion mode) or for power saving in designs that do not need to use all the outputs available. Two control bits are used to control the function of the output enable. 1.3 RapidConfigure Interface RapidConfigure (RC) is a 23 signal parallel interface that is used to program the OCX1601 device. The 23 pins are allocated as follows: RCA[6:0] = RapidConfigure Address A. RCA are input pins. RCB[6:0] = RapidConfigure Address B. RCB are input pins. RCI[3:0] = RapidConfigure Instruction Bits RCO[2:0] = RapidConfigure Readback. RCO are output pins. RC_CLK# = RapidConfigure Clock RC_EN# = RapidConfigure Cycle Enable (state is sensed on the negative edge of clock) 1.3.1 RapidConfigure Programming Instructions The RC interface supports both write and read types of operations: 1. Write Operations (reset crosspoint and Input or Output Buffer (IOB), configure an Output Buffer, connect/disconnect crosspoint) 2. Read Operations (Output Buffer and crosspoint configuration read). Table 2 RapidConfigure Programming Instructions RCO[2:0] Instruction Reserved Reserved X X Reset Crosspoint Array Reset, along with an Update operation (UPDATE# pin or Update command) resets the entire crosspoint array to no connect. All Output Buffers remain unchanged by this operation. Connects the input selected by RCB[6:0] to all output ports and disconnects all other inputs. The Global Update (UPDATE#) pin must be held high during Broadcast mode. Activating the Global Update pin returns the array to the previous program condition. Program an Output Buffer specified by RCA[6:0]. See Table 4 for RCB[6:0] bit assignment and buffer functionality. Description RCI[3:0] 0000 0001 0010 RCA[6:0] RCB[6:0] 0011 X Input Port Address Set Array to Broadcast mode 0100 Output Port Address Data Configure an Output Buffer Fairchild Semiconductor [Rev. 1.8] 3/21/02 9 OCX1601 Crosspoint Switch--Advanced Datasheet Table 2 RCI[3:0] 0101 Cycle 1 Output Port Address X Input Port Address X X RCA[6:0] RapidConfigure Programming Instructions (Continued) RCO[2:0] Instruction Readback Crosspoint, Output Buffer status Description This is a two-cycle instruction. Specify the crosspoint connect status at output location specified by RCA[6:0] to the input location specified by RCB[6:0]. Readback (using RCO[2:0]) the status of the input buffer specified in Cycle 1 by RCA[6:0], the output buffer specified in Cycle 1 by RCO[2:0] and the crosspoint connect status. See Table 3 for RCO[2:0] readback pin assignment. 0110 0111 1000 X X Output Port Address X Input Port Address Input Port Address Update Disconnect Input Disconnect Input and Output Program the Global Update function without the use of the UPDATE# pin. Disconnect the crosspoint cells of the input row location specified by RCA[6:0]. Disconnect the crosspoint cell at the output location specified by RCA[6:0] to the input location specified by RCB[6:0]. All other connections from the source input address or to the same output address remain the same as before. 1001 Output Port Address Input Port Address Connect, with ImpliedDisconnect Connect the crosspoint cell at the output location specified by RCA[6:0] to the input location specified by RCB[6:0]. All other connections from the same input address or to the same output address are set to no connect (NC). 1010 Output Port Address Input Port Address Connect, without ImpliedDisconnect Connect the crosspoint cell at the output location specified by RCA[6:0] to the input location specified by RCB[6:0]. All other connections to the same output address are set to "no connect" while all other connections from the same input address remain the same as before. 1011 1100 1101 X X Reserved Reserved Reset All Reset the switch matrix to no connects (NC). Update is forced internally. Sets the Output buffer to Flow-through mode with Output Enabled. RCB[6:0] Cycle 2 Output Data 1110 1111 Reserved Reserved Note - X = Don't care. 10 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet Table 3 RCO[2:0] O2 RCO[2:0] Readback Pin Assignment Signal/Function Connection Status: 0 = No connection (NC) -- (default state at reset) 1 = Connected Output Enable: Output enabled (ON) - this is the default state at reset Output disabled (OFF) Output controlled by OE (active high) Output controlled by OE# (active low) Readback Location Crosspoint O1, O0 0,0 0,1 1,0 1,1 Output Buffer Table 4 Programming an Output Buffer using RapidConfigure Signal/Function Don't care Output Enable: Output enabled (ON) - this is the default state at reset Output disabled (OFF) Output controlled by OE (active high) Output controlled by OE# (active low) RCB[6:0] B6, B5, B4, B3, B2 B1, B0 0,0 0,1 1,0 1,1 Fairchild Semiconductor [Rev. 1.8] 3/21/02 11 OCX1601 Crosspoint Switch--Advanced Datasheet 1.4 Serial Interface Configuration Controller The Output port attributes and the Switch Matrix connections can be programmed using the serial bus. The RapidConfigure Interface can be enabled or disabled using the serial bus. The serial interface mode is always available for configuration regardless of whether the RapidConfigure mode is enabled or disabled. However, proper care must be taken when switching between Serial Interface and RapidConfigure for configuring the devices. Before attempting to change Switch Matrix connections or output port configuration through the Serial Interface, the user must first ensure that the RapidConfigure mode is disabled by using the Serial Interface serial mode to set the RCE bit to zero in the Mode Control Register. 1.4.1 Serial Interface The dedicated Serial interface has five pins: Serial Data Out (SDO), Serial Mode Select (SMS), Serial Data In (SDI), Serial Reset (SRST#), and Serial Clock (SCLK), for device configuration and verification. The Fairchild supplied software will automatically generate the necessary bitstream from a higher-level textual description of the required configuration. Data on the SDI and SMS pins are clocked into the device on the rising edge of the SCLK signal, while the valid data appears on the SDO pin after the falling edge of SCLK. For more detailed information on Serial programming, refer to the OCX Family Register Programming Manual. 1.4.2 Output Port Configuration Output port configuration is accomplished by loading the appropriate bitstream into the programming registers present at each Output port. The serial bus is used to load configuration data into the Output port programming registers, one Output port at a time. 1.4.3 Switch Matrix Configuration The contents of the SRAM cells controlling Switch Matrix connection can be modified using the Serial interface. This is accomplished by loading the configuration data, one word at a time, into the SRAM cells in the Switch Matrix. 1.4.4 Mode Control Register Configuration The OCX1601 contains a single bit Mode Control Register used to store user flags for RapidConfigure Enable (RCE). These are required for proper functioning of the device. The contents of this register can be changed using the Serial interface and a special Serial instruction. Table 5 RCE 0 1 Mode Control Register Mode RapidConfigure interface disabled (OFF) RapidConfigure interface enabled (ON) 12 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet 1.4.5 Serial Interface Architecture Programming Registers (189 x 2 = 378 Bits) Data Register - 1 Bit Device Identification Register - 32 Bits SDI Mode Control Register - 1 Bit MUX BUF SDO Address Register - 7 Bits Bypass Register - 1 Bit Instruction Register - 16 Bits SMS SCLK Figure 4 Serial Interface Controller OCX1601 Serial Interface Architecture SRST# Fairchild Semiconductor [Rev. 1.8] 3/21/02 13 OCX1601 Crosspoint Switch--Advanced Datasheet 1.4.6 Serial Interface State Machine 1 Test Logic Reset 0 1 Run Test/ 1 Idle Select DR Scan 0 Capture DR 0 1 1 Select IR Scan 0 Capture IR 0 1 0 0 Shift DR 1 Exit 1 DR 1 0 Pause DR 1 0 Shift IR 1 Exit 1 IR 1 0 Pause IR 1 0 0 0 Exit 2 DR 1 Update DR 1 0 0 Exit 2 IR 1 Update IR 1 0 Figure 5 OCX1601 Serial Interface State Machine 1.4.7 Serial Input Format Table 6 Instruction Serial Input Format Data 12 I0 11 10 9 B9 8 B8 7 B7 6 A6 5 A5 BB BA Address A 4 A4 3 A3 2 A2 1 A1 0 A0 Bit Number Bit Name 15 I3 14 I2 13 I1 14 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet 1.4.8 Serial Interface Instructions Table 7 I [3:0] 0000 0001 0010 BB X X X BA X X X B9 X X X B8 X X X B7 X X X Serial Interface Instructions A6-A0 X X X Instruction Sample/EXTEST Sample/EXTEST Description Places the device in scan mode. Places the device in scan mode. Reset the Crosspoint Reset, along with an Update operation (UPDATE# pin Array or Update command) resets the entire Crosspoint Array to no-connect (B7 and B8 are not changed). Set Array for Broadcast mode Use the Address Register as the Input address to be the broadcast input. Connects the selected Input to all Output cells and disconnects all other Inputs. Activating the Global Update instruction returns the Crosspoint array from the Broadcast mode to the previous programed state. Programs the Output Buffer address specified in the Serial instruction (A6-A0). The configuration data is also specified in the Serial instruction bits BA-B7. See Table 8 for bit assignment of the Buffer functionality. Readback the connectivity of the Crosspoint cell with the Input location specified in the Address Register and the Output location specified Serial instruction (A0-A6). It also returns the configuration of the Output Buffer addressed in the Serial instruction (A0-A6). The readback data is shifted out of SDO in the following sequence: 1. Crosspoint Connect (1=connected, 0=no connection) 2. Output Enable--B7 (see Table 8) 3. Output Enable--B8 (see Table 8) 4. Reserved (Don't Care) 5. Reserved (Don't Care) 6. State of Broadcast bit 7. State of the RCE bit NOTE: This instruction does not increment the Address Register. This instruction also requires two DR cycles 0011 X X X X X X 0100 X X X OE OE Output Buffer Address Program a Buffer 0101 X X X X X Output Address/ Configuration Buffer readback 0110 0111 1000 X X X X X X X X X X X X X X X X X Update the Crosspoint Array Disconnect Input cell Update the programmed connection from the Loading SRAM to the Active SRAM. Disconnect the Crosspoint connections from the Input address specified in the Address Register. Disconnect the Crosspoint cell at the Input location specified at the Address Register and the Output location specified in the Disconnect instruction (A6A0). All other connections from the same input address or to the same output address remain the same. Output Address Disconnect Input and Output Fairchild Semiconductor [Rev. 1.8] 3/21/02 15 OCX1601 Crosspoint Switch--Advanced Datasheet Table 7 I [3:0] 1001 BB X BA X B9 X B8 X B7 X Serial Interface Instructions (Continued) A6-A0 Instruction Description Connects the Crosspoint cell at the Input location specified on the Address Register and the output location specified in the Connect Serial instruction (A6-A0). All other connections from the same Input address or the same Output address are set to no-connects. NOTE: This instruction increments the Address Register (Input address). Connects the Crosspoint cell at the Input address specified in the Address Register and the Output address specified in the Connect instruction (A6-A0). All connections to the same output address are set to "no connect" while all other connections from the same input remain the same as before. Sets the 7-bit Address Register with the 7-bit address (A6-A0) of the Instruction Register. The 7-bit address of the Address Register becomes the Input port address for Crosspoint Access. Serialize the device ID and revision history out to SDO. ID for the OCX1601 is 0x0000D89F Output Address Connect with ImpliedDisconnect 1010 X X X X X Output Address Connect--no ImpliedDisconnect 1011 X X X X X Input Address Set the Address Register 1100 1101 X X X X X X X X X X X X Device ID out Reset Output Buffer Resets the Crosspoint Array to no-connects. Sets the and Crosspoint Output buffer to Flow-through mode with Output Array Enabled. The device ID is serialized to SDO. Set RCE Bit Sets the RCE bit of the Mode Control Register with the Serial instruction bit A0. To turn ON the RCE bit, encode bit A0 to 1. To turn OFF the RCE bit, encode bit A0 to 0. Places device in a mode to pass SDI data to SDO with one clock delay. Used for programming and testing devices through serial connected controls. 1110 X X X X X X 1111 X X X X X X Bypass Table 8 BA, B9, B8, B7 B8, B7 0,0 0,1 1,0 1,1 Programming an Output using the Serial Interface Signal/Function Output Enable: Output enabled (ON) - this is the default state at reset Output disabled (OFF) Output controlled by OE (active high) Output controlled by OE# (active low) 16 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet Table 9 Number of Cycles and Configuration Time OCX1601 Operation Serial Cycles 7 28 28 2,240 35 56 181,440 183,680 Reset Sequence (SMS = "11111") Enable or Disable RapidConfigure Change attributes of ONE Output Port Change attributes of ALL Output Ports Reset Controller + Reset ALL Output Ports + Clear ALL SRAM cells Connect or disconnect two Ports Configure Entire Switch Matrix (All Switch Matrix Connections) Completely Configure the Device (All Output Ports and All Switch Matrix Connections) 1.5 ImpliedDisconnect ImpliedDisconnect is a feature that provides the ability to make fast switch connection changes. When using the normal "Connect" command, all other connection to the specified output are set to "no connect". However, the specified input remains connected to any other outputs it was connected to before. The "Connect with ImpliedDisconnect" command allows the user to disconnect the specified input from all other outputs as well. This enables the user to make a complete connection change in one RapidConfigure cycle. Fairchild Semiconductor [Rev. 1.8] 3/21/02 17 OCX1601 Crosspoint Switch--Advanced Datasheet 1.6 Device Reset Options The power-on reset, RapidConfigure reset, hardware reset, and Serial reset functions will program the output buffers to flow-through mode (with Global Clock selected), and Output Enabled (ON). The Serial interface can be reset via the SRST# pin or by clocking five consecutive one to the SMS pin. The hardware reset pin can be done accomplished through the HW_RST# pin (active low). RC reset can be accomplished by applying the RC instruction 1101 to the RCI[3:0] pins. Table 10 Programming Interface Reset Method Power-on Reset Hardware Reset HW_RST# (low pulse) 1. Low Pulse on SRST# 2. SMS high for 5 SCLK cycles Serial Reset 3. Device Reset (instruction 1101) 4. Reset Crosspoint Array (instruction 0010) RapidConfigure Reset 1. Device reset (instruction 1101) 2. Reset Crosspoint Array (instruction 0010) Device Reset Options Output Ports OP OP Unchanged Unchanged OP Unchanged OP Unchanged Switch Matrix NC NC Unchanged Unchanged NC NC NC NC RCE Mode Control 1 (RC Enabled) 1 (RC Enabled) Unchanged Unchanged 1 (RC Enabled) Unchanged 1 (RC Enabled) Unchanged Serial TAP TLR1 TLR TLR TLR TLR Unchanged Unchanged Unchanged 1. TLR = Test Logic Reset state. 18 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet 2. Pin Description Table 11 Pin Name INP[79:0] INN[79:0] OUTP[79:0] OUTN[79:0] OE# HW_RST# UPDATE# # of Pins 80 80 80 80 1 1 1 OCX1601 Pin Description Description Non-inverting differential input signals Inverting differential input signals Non-inverting differential input signals Inverting differential input signals Global Output Enable Hardware Reset Global Update Type Input Input Output Output Input Input Input RC Pins RCA[6:0] RCB[6:0] RCO[2:0] RCI[3:0] RC_CLK# RC_EN# 7 7 3 4 1 1 Input Input Output Input Input Input RapidConfigure Address A RapidConfigure Address B RapidConfigure Readback RapidConfigure Instruction Bits RapidConfigure Clock RapidConfigure Cycle Enable Serial Interface Pins SCLK SMS SDI SRST# SDO 1 1 1 1 1 Input Input Input Input Output Serial Clock Serial Mode Select Serial Data In Serial Reset Serial Data Out Power and Ground Pins VDD.CORE VDD.PAD VDD.IN VSS NC (2) (1, 3) 12 8 8 36 5 2.5V Power 3.3V Power 3.3V Power Ground No Connect Core Voltage Differential Output Buffer Voltage LVTTL Control pins Voltage and Differential Input Buffer Voltage Ground No Connect NOTES: 1. Dedicated differential input buffers can receive both LVPECL and LVDS voltage levels using 3.3V supply. 2. VDD.PAD is 3.3V for LVPECL outputs. 3. The LVTTL control, Serial pins, and differential input ports are 3.3V--they are not 5V tolerant. Fairchild Semiconductor [Rev. 1.8] 3/21/02 19 OCX1601 Crosspoint Switch--Advanced Datasheet 3. Differential I/O Standards The OCX1601 support the two most popular differential signaling standards: Low Voltage Positive Emitter Coupled Logic (LVPECL) and Low Voltage Differential Signaling (LVDS). LVPECL is commonly used in video switching applications or those designs requiring transmission of highspeed clock signals. This is the default I/O supported by the OCX1601 device. LVDS is typically used in communication systems as high speed, low noise point-to-point links. The OCX1601 conforms to the ANSI/TIA/EIA-644 standard covering electrical specifications for output drivers and receiver inputs. 3.1 LVPECL LVPECL is a differential signaling standard that specifies two pins per input or output. The voltage swing between these two signal lines is approximately 850 mV. The use of a reference voltage or a board termination voltage is not required. Transmitting and receiving circuits for LVPECL are shown in Figure 6 with termination resistors integrated on-chip, thus, removing the need for any external resistors. Integrated Output Attenuation resistors produce the required LVPECL output swing while providing a 100 ohm output impedance to minimize return reflections. OCX1601 Device Z0=50 INP From LVPECL Driver Z0=50 INN RT 110 + - VDD.PAD = 3.3V Switch Z0=50 OUTP To Receiver Matrix Z0=50 OUTN Figure 6 OCX1601 Operating in LVPECL Mode 3.2 LVDS LVDS is a differential signaling standard that requires the use of two pins per input or output. It requires that one data bit is carried through two signal lines. As with all differential signaling standards, LVDS has an inherent noise immunity over single-ended standards. The voltage swing between two signal lines is approximately 350mV. The use of a reference voltage or a board termination voltage is not required. Note - It is possible to operate the OCX1601 device with VDD.PAD = 2.5V that will allow the outputs to closely approximate "true LVDS" levels. Refer to the application note "Operating the OCX1601 in LVDS Applications" for further details. 20 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet 4. Electrical Specifications 4.1 Absolute Maximum Ratings Table 12 Symbol VDD.CORE VDD.IN VDD.PAD VIN2 TJ TSTG PMAX ESD6 Absolute Maximum Ratings1 Parameter Supply Voltage (core) Supply Voltage (inputs) Supply Voltage (differential outputs) Input Voltage Junction Temperature Storage Temperature Maximum Power Dissipation Electrostatic Discharge Limits -0.3 to +3.0 -0.3 to +3.6 -0.3 to +3.6 -0.3 to +3.63 +150 -65 to +150 6 2000 Units V V V V C C W V 4.2 Recommended Operating Conditions Table 13 Symbol VDD.CORE VDD.PAD4 VDD.IN TA Recommended Operating Conditions Parameter Supply Voltage (core) Supply Voltage (differential output buffers) Supply Voltage (inputs) Operating Temperature: Commercial Operating Temperature: Industrial Limits +2.375 to +2.625 3.3V 10% +3.0 to +3.6 0 to +70 -40 to +85 Units V V V C 4.3 Pin Capacitance Table 14 Symbol CPIN 1. 2. 3. 4. 5. 6. Pin Capacitance5 Parameter Max 10 Units pF Signal Pin Capacitance Exposure to absolute maximum rated conditions for extended periods may affect device reliability. A maximum undershoot of 2V for a maximum duration of 20 ns is acceptable. Overshoot to 3.6V is acceptable. All inputs are 3.3V tolerant with the VDD pin at 2.5V or 3.3V. Note that min and max values for VDD for differential outputs are I/O Standard dependent. Capacitance measured at 25C. Sample tested only. Measured using Human Body Model. Fairchild Semiconductor [Rev. 1.8] 3/21/02 21 OCX1601 Crosspoint Switch--Advanced Datasheet 4.4 DC Electrical Specifications (TA = -40C to 85C, VDD.IN = 3.3V 10%, VDD.CORE = 2.5V 5%) Table 15 Symbol VIH VIL VOH VOL ILIH, ILIL (1) ILOZ Parameter High-level Input Low-level Input High-level Output Low-level Output Input Pin Leakage Current (2) LVTTL DC Electrical Specifications Conditions Ports are 3.3V tolerant Ports are 3.3V tolerant VDD.PAD = Min IOH = -4mA VDD.PAD = Min IOL = 8mA VDD.IN= Max 0.0 < In < VDD.PAD (2) Min 2.0 -0.3 2.4 Max 3.6 0.8 VDD.PAD+ 0.3 0.4 +5 -50 +5 -5 Units V V V V Tristate Leakage Output OFF State VDD.PAD = Max 0.0 < In < VDD.PAD Power PDDQ (3) Quiescent Power Table 16 Symbol VIN_DIFF VIN_COM VOUT_DIFF VOUT_COM ZIN 1. 2. 3. 4. All VDD = Max LVPECL DC Electrical Specifications Min 100 0.25 650 VDD.PAD 2 80 2.25 900 VDD.PAD 2 120 Max Units mV V mV V 0.5 W DC Parameters Input Differential Voltage Input Common Mode Voltage Output Differential Voltage Output Common Mode Voltage Termination Impedance All LVTTL input pins have pull-up resistors. Input leakage only valid when both positive and negative inputs/outputs are equal (i.e. both high or both low). See section 7 for dynamic power consumption calculation. Maximum capacitive load is 12 pF. The VOH levels are 200mV below standard single-grounded LVPECL levels and are compatible with devices tolerant of lower common-mode ranges. The above table summarizes the DC output specifications of LVPECL. 22 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet 4.5 LVPECL AC Electrical Specifications (VDD.IN = 3.3V 10%, VDD.CORE = 2.5V 5%, , VDD.PAD = 3.3V 10%) Table 17 LVPECL AC Electrical Specifications 0C to 70C Symbol RDATA tPHL, tPLH tW+ tWtDCD+, tDCDtJITTER tSK tPHZ_OT, tPLZ_OT tPZH_OT, tPZL_OT tRC tW+_RC tW-_RC tS_RC tH_RC tP_UD fSI tW_SI tS_SI tH_SI tP_SI NRZ Data Rate (1) -40C to +85C Min Max 1.6 3.5 0.6 0.6 Units Gb/s ns ns ns 60 60 0.25 5 5 12 5 4 4 ps ps ns ns ns ns ns ns ns 10 20 20 4 0 30 ns MHz ns ns ns 20 ns Parameter One Way Signal Propagation Delay, Fanout = 1 Input Flow-through Positive Pulse Width Input Flow-through Negative Pulse Width Duty Cycle Distortion Output Jitter Skew between Output Ports Output Enable to Valid Data Output Enable to High Z State RapidConfigure Clock Period RapidConfigure Clock Pulse Width RapidConfigure Address Setup to RC_CLK# RapidConfigure Address and Enable Hold Time to RC_CLK# Update of Crosspoint to Data Out Serial Clock Frequency (SCLK) Serial Clock Pulse Width (SCLK) @ 20MHz cycle Serial Setup Time Serial Hold Time Serial Clock to Output Data Valid (SDO) (1) Min Max 1.6 3.0 0.6 0.6 50 50 0.2 5 5 12 5 3 3 10 20 20 4 0 20 30 NOTES: 1. These parameters are guaranteed but not tested in production. Fairchild Semiconductor [Rev. 1.8] 3/21/02 23 OCX1601 Crosspoint Switch--Advanced Datasheet 4.6 Timing Diagrams Note - For the purpose of clarity, the timing diagrams within this datasheet are conceptual representations only and do not show actual circuit implementation. InPort 1 InPort 2 tW+ tPLH tPHL IN InPort 1 OP OutPort 1 OutPort 1 tSK OutPort 2 Switch Matrix InPort 2 tSK OutPort 2 Figure 7 Flow-Through Mode Timing OE# InPort IN InPort OE# tPZH_OT tPZL_OT tPLZ_OT tPHZ_OT Switch Matrix OP OutPort OutPort Figure 8 Output Enable Timing IN InPort Switch Matrix OP OutPort InPort tIN+ tIN- OutPort tOUT+ tDCD+ = tIN+ - tOUT+ tDCD- = tIN- - tOUT- tOUT- Figure 9 Duty Cycle Distortion 24 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet tRC tW+_RC RC_CLK# tS_RC RCA/RCB Address, Instruction tS_RC tH_RC RC_EN# tH_RC tW-_RC tRC Figure 10 RapidConfigure Write Cycle tRC tW+_RC RC_CLK# tW-_RC tRC tS_RC RCA/RCB Address, Instruction tH_RC tS_RC tH_RC RC_EN# Data Valid RCO High Impedance Figure 11 RapidConfigure Read Cycle Fairchild Semiconductor [Rev. 1.8] 3/21/02 25 OCX1601 Crosspoint Switch--Advanced Datasheet tW_SI SCLK tS_SI SDI, SMS tW_SI tH_SI tP_SI SDO Figure 12 Serial Timing Typical Performance at 1.6 Gb/s with PRBS Data (Currently not available for this document) Figure 13 Typical Performance 26 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet 5. Pinout 5.1 Package Pinout 12 A B C D E F G H J K L M N P R T U V W OUT51N VSS 34567 IN40N IN42N IN41N IN40P IN41P VSS RCI2 RC_EN# RCI1 VSS RCB4 VSS RCB5 OUT77P RCB6 OUT77N VDD.PAD OUT76P OUT71P OUT71N VDD.CORE RCI0 IN43N VDD.IN RCI3 IN43P IN45P IN42P IN44P IN45N IN44N IN48P IN48N 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 IN51N IN49N IN51P IN49P IN47N IN47P IN52P IN46N IN52N VDD.CORE IN50N IN54N IN55N IN54P VDD.IN VSS VSS IN50P IN53N IN55P IN60P VSS IN62N VDD.IN IN56N IN53P IN57P IN60N IN61P IN62P IN63N VSS IN56P IN57N IN58N IN64P IN61N IN63P IN68N IN69N VDD.IN VDD.CORE IN72N IN58P IN64N IN59N IN65P IN68P IN69P IN71N IN72P NC IN59P IN65N IN66N IN67P IN71P IN74P IN75N SCLK SRST# VSS IN66P IN67N IN70N IN73P IN75P IN79N VSS SDO OUT07N IN70P IN73N IN74N IN79P SDI VSS OUT01P OUT01N IN78P IN78N IN76N IN77N IN76P IN77P VSS HW_RST# OUT00P OUT00N RCO2 VSS VSS RC_CLK# OUT78P VSS OUT78N OUT79P OUT79N OUT75P OUT75N OUT74N OUT74P OUT73N OUT73P OUT72N OUT72P OUT67N OUT67P OUT66N OUT66P OUT65N OUT65P OUT64P OUT63N OUT61P OUT64N OUT61N OUT59P OUT55P OUT55N OUT57P OUT58N OUT57N OUT52P OUT46N OUT46P OUT56N OUT56P OUT44N OUT44P OUT51P OUT50N OUT48P OUT42P OUT48N OUT40P RCB0 RCB1 RCA6 VSS VSS RCA5 IN36P IN36N VSS OUT40N OUT42N OUT50P OUT45N OUT47N OUT52N OUT58P OUT53P OUT54N OUT59N OUT62N OUT63P OUT69N OUT69P OUT70P OUT76N A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF IN46P VDD.CORE 40-79 Inputs OUT07P UPDATE# OUT02P OUT09N OUT03N OUT03P OUT11N OUT05P OUT04P OUT16N OUT11P OUT09P SMS OUT02N OUT05N OUT16P VDD.PAD OUT17N OUT04N OUT70N OUT68N OUT68P VDD.PAD OUT62P OUT60P OUT60N VSS VSS VSS OUT54P VDD.PAD OUT53N OUT49N OUT49P VDD.CORE OUT47P VDD.CORE OUT45P VDD.PAD OUT43P OUT41P OUT43N RCB3 OUT41N VSS RCB2 RCA3 VSS IN39P RCA4 IN39N IN34N IN38N IN34P IN38P IN37N IN33P IN37P IN33N IN35P IN31P RCA2 IN31N IN35N OCX1601 in 420 BGA package 40-79 Outputs VDD.CORE OUT06N OUT17P OUT18P OUT06P OUT18N OUT10P VDD.CORE OUT13P OUT08P OUT08N OUT12P OUT10N OUT15P OUT13N Top View 0-39 Outputs OUT15N OUT12N VDD.PAD OUT14P OUT19P VSS VSS VSS OUT20N OUT20P OUT22P OUT22N OUT25P OUT19N OUT28P OUT24P OUT14N OUT21N OUT24N OUT21P OUT28N OUT25N VDD.PAD OUT23P OUT26P OUT23N OUT29N OUT29P OUT27P OUT26N OUT27N VDD.CORE OUT30P OUT32P OUT31N OUT31P OUT37N OUT32N OUT34N OUT30N Y AA AB AC AD AE AF 0-39 Inputs VDD.CORE VDD.IN IN29N IN30N IN29P IN30P IN27N IN32P IN27P IN32N IN26P IN26N IN25N IN24P IN28P IN25P IN22N IN24N IN19N IN28N IN23N IN22P IN20N IN19P IN18N IN17N VSS IN23P IN21P IN20P IN15P IN18P IN17P IN16P IN11N VDD.IN IN21N VSS IN15N IN14N IN13N IN16N IN11P IN09N IN07N VSS VSS IN14P IN12N IN13P IN10N IN09P IN07P IN04N VDD.IN IN12P IN08N VDD.CORE IN05P VDD.IN IN03N IN05N IN10P IN06P IN04P IN03P RCO0 VDD.CORE IN06N IN08P OUT37P OUT34P VDD.PAD OUT39P OUT35N OUT39N OUT38N VSS VSS OE# RCA1 RCA0 IN01N IN02P IN01P IN02N IN00N IN00P NC VSS VSS VSS NC VSS NC NC OUT38P RCO1 OUT33P OUT36N OUT36P OUT33N OUT35P 12 34567 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Figure 14 OCX1601 Package Pinout Fairchild Semiconductor [Rev. 1.8] 3/21/02 27 OCX1601 Crosspoint Switch--Advanced Datasheet 5.2 Pinout by Ball Sequence Table 18 Ball # Ball Name A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 VSS VSS IN40N IN41N IN42N IN44N IN48N IN49N IN51N IN56N IN56P IN57N IN58P IN64N IN59P IN65N IN66P IN67N IN70P IN73N IN78P IN78N IN76P IN77P RCO2 VSS OCX1601 Pinout By Ball Sequence Ball # Ball Name C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 OUT78P OUT78N VSS RCI2 RCI3 IN43P IN45N IN47P IN47N IN50N IN53N IN55P IN60N IN61P IN61N IN63P IN68P IN69P IN71P IN74P IN75P IN79N SDI VSS OUT00P OUT00N Ball # Ball Name B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 RC_CLK# VSS IN40P IN41P IN42P IN44P IN48P IN49P IN51P IN50P IN53P IN57P IN58N IN64P IN59N IN65P IN66N IN67P IN70N IN73P IN74N IN79P IN76N IN77N VSS HW_RST# Ball # Ball Name D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 OUT79P OUT79N RC_EN# VSS RCI1 IN43N IN45P IN46N IN52P IN52N IN54N IN55N IN60P VSS IN62P IN63N IN68N IN69N IN71N IN72P IN75N SCLK VSS SDO OUT01P OUT01N Ball # Ball Name E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 OUT75P OUT75N RCB4 RCB5 VSS RCI0 VDD.IN IN46P VDD.CORE VDD.CORE IN54P VDD.IN VSS VSS IN62N VDD.IN VSS VDD.CORE VDD.IN IN72N NC VSS SRST# UPDATE# OUT07N OUT07P 28 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet Table 18 Ball # Ball Name F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 L1 L2 L3 L4 L5 L22 L23 L24 L25 L26 T1 T2 T3 T4 T5 T22 T23 T24 T25 T26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 OUT74N OUT74P OUT77P OUT77N RCB6 SMS OUT02P OUT03N OUT09N OUT09P OUT65N OUT65P OUT63P OUT62P VDD.PAD OUT08N OUT08P OUT10N OUT13P OUT13N OUT57P OUT58N OUT58P OUT49P OUT49N VDD.PAD OUT22P OUT28N OUT25P OUT25N OUT51P OUT50N OUT50P OUT41N RCB3 OUT39N OUT39P OUT36N OUT35N OUT35P OCX1601 Pinout By Ball Sequence (Continued) Ball # Ball Name H1 H2 H3 H4 H5 H22 H23 H24 H25 H26 N1 N2 N3 N4 N5 N22 N23 N24 N25 N26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 OUT72N OUT72P OUT70P OUT71N OUT71P VDD.PAD OUT04P OUT05N OUT16N OUT16P OUT61P OUT64N OUT59N VSS VSS VSS OUT14P OUT14N OUT19P OUT21P OUT46N OUT46P OUT47N OUT45P VDD.CORE VDD.CORE OUT29N OUT27N OUT27P OUT30P Ball # Ball Name G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 M1 M2 M3 M4 M5 M22 M23 M24 M25 M26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 OUT73N OUT73P OUT76N OUT76P VDD.PAD OUT02N OUT03P OUT05P OUT11N OUT11P OUT64P OUT63N OUT62N OUT60N OUT60P VDD.PAD OUT12P OUT12N OUT15P OUT15N OUT57N OUT52P OUT52N OUT47P VDD.CORE OUT23N OUT23P OUT29P OUT26P OUT26N Ball # Ball Name J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 P1 P2 P3 P4 P5 P22 P23 P24 P25 P26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 OUT67N OUT67P OUT69P OUT70N VDD.CORE VDD.CORE OUT04N OUT06N OUT17N OUT17P OUT61N OUT59P OUT54N OUT54P VSS VSS VSS OUT19N OUT21N OUT24N OUT56N OUT56P OUT45N OUT43P VDD.PAD OUT31P OUT31N OUT32N OUT32P OUT30N Ball # Ball Name K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 R1 R2 R3 R4 R5 R22 R23 R24 R25 R26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 OUT66N OUT66P OUT69N OUT68P OUT68N VDD.CORE OUT06P OUT10P OUT18P OUT18N OUT55P OUT55N OUT53P OUT53N VDD.PAD OUT20P OUT20N OUT22N OUT28P OUT24P OUT51N OUT44P OUT44N OUT43N OUT41P VDD.PAD OUT37N OUT37P OUT34N OUT34P Fairchild Semiconductor [Rev. 1.8] 3/21/02 29 OCX1601 Crosspoint Switch--Advanced Datasheet Table 18 Ball # Ball Name AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 OUT48P OUT42P OUT42N RCB2 VSS RCA2 IN35N VDD.IN VDD.CORE VSS VDD.IN IN21N VSS VSS VDD.IN IN12P VDD.CORE VDD.CORE IN05P VDD.IN RCO0 VSS OUT38N OUT38P OUT36P OUT33N OCX1601 Pinout By Ball Sequence (Continued) Ball # Ball Name AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 RCB0 RCB1 VSS RCA4 IN39P IN37P IN31P IN30P IN29P IN28P IN23N IN22P IN20P IN15P IN14N IN13N IN13P IN10N IN10P IN06P IN03P RCA0 RCA1 VSS NC NC Ball # Ball Name AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 OUT48N OUT40P OUT40N VSS RCA3 IN35P IN31N IN30N IN29N IN28N IN23P IN21P VSS IN15N IN14P IN12N IN08N IN08P IN06N IN05N IN03N OE# VSS VSS RCO1 OUT33P Ball # Ball Name AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AD20 AE21 AE22 AE23 AE24 AE25 AE26 RCA6 VSS IN36N IN34N IN39N IN37N IN33N IN32P IN27N IN26N IN25P IN22N IN20N IN19P IN18P IN17P IN16N IN11P IN09P IN07P IN04P IN02P IN01N IN00P VSS NC Ball # Ball Name AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 VSS RCA5 IN36P IN34P IN38N IN38P IN33P IN32N IN27P IN26P IN25N IN24P IN24N IN19N IN18N IN17N IN16P IN11N IN09N IN07N IN04N IN02N IN01P IN00N NC VSS 30 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet 5.3 Pinout by Ball Name Table 19 Ball Name HW_RST# IN00N IN00P IN01N IN01P IN02N IN02P IN03N IN03P IN04N IN04P IN05N IN05P IN06N IN06P IN07N IN07P IN08N IN08P IN09N IN09P IN10N IN10P IN11N IN11P IN12N IN12P IN13N IN13P IN14N IN14P IN15N IN15P IN16N IN16P IN17N IN17P IN18N IN18P IN19N IN19P IN20N IN20P IN21N OCX1601 Pinout By Ball Name Ball # Ball Name C6 A6 B6 C7 D7 D8 E8 C9 C8 A7 B7 A8 B8 C10 B10 A9 B9 D10 D9 C11 B11 D11 E11 D12 C12 A10 A11 A12 B12 B13 A13 B15 A15 C13 D13 C15 C14 E15 D15 D16 C16 A14 B14 A16 IN65P IN66N IN66P IN67N IN67P IN68N IN68P IN69N IN69P IN70N IN70P IN71N IN71P IN72N IN72P IN73N IN73P IN74N IN74P IN75N IN75P IN76N IN76P IN77N IN77P IN78N IN78P IN79N IN79P NC NC NC NC NC OE# OUT00N OUT00P OUT01N OUT01P OUT02N OUT02P OUT03N OUT03P OUT04N Ball # Ball Name B26 AF24 AE24 AE23 AF23 AF22 AE22 AC21 AD21 AF21 AE21 AC20 AB19 AC19 AD20 AF20 AE20 AC17 AC18 AF19 AE19 AD18 AD19 AF18 AE18 AC16 AB16 AD16 AD17 AD15 AC15 AC14 AD14 AE17 AF17 AF16 AE16 AF15 AE15 AF14 AE14 AE13 AD13 AB12 IN21P IN22N IN22P IN23N IN23P IN24N IN24P IN25N IN25P IN26N IN26P IN27N IN27P IN28N IN28P IN29N IN29P IN30N IN30P IN31N IN31P IN32N IN32P IN33N IN33P IN34N IN34P IN35N IN35P IN36N IN36P IN37N IN37P IN38N IN38P IN39N IN39P IN40N IN40P IN41N IN41P IN42N IN42P IN43N Ball # Ball Name AC12 AE12 AD12 AD11 AC11 AF13 AF12 AF11 AE11 AE10 AF10 AE9 AF9 AC10 AD10 AC9 AD9 AC8 AD8 AC7 AD7 AF8 AE8 AE7 AF7 AE4 AF4 AB7 AC6 AE3 AF3 AE6 AD6 AF5 AF6 AE5 AD5 A3 B3 A4 B4 A5 B5 D6 IN43P IN44N IN44P IN45N IN45P IN46N IN46P IN47N IN47P IN48N IN48P IN49N IN49P IN50N IN50P IN51N IN51P IN52N IN52P IN53N IN53P IN54N IN54P IN55N IN55P IN56N IN56P IN57N IN57P IN58N IN58P IN59N IN59P IN60N IN60P IN61N IN61P IN62N IN62P IN63N IN63P IN64N IN64P IN65N Ball # Ball Name B16 B17 A17 A18 B18 D17 C17 D18 C18 B19 A19 D19 C19 E20 D20 A20 B20 B21 C20 D21 C21 B23 A23 B24 A24 A22 A21 C22 B22 E21 AD25 AD26 AE26 AF25 AC22 C26 C25 D26 D25 G22 F23 F24 G23 J23 OUT04P OUT05N OUT05P OUT06N OUT06P OUT07N OUT07P OUT08N OUT08P OUT09N OUT09P OUT10N OUT10P OUT11N OUT11P OUT12N OUT12P OUT13N OUT13P OUT14N OUT14P OUT15N OUT15P OUT16N OUT16P OUT17N OUT17P OUT18N OUT18P OUT19N OUT19P OUT20N OUT20P OUT21N OUT21P OUT22N OUT22P OUT23N OUT23P OUT24N OUT24P OUT25N OUT25P OUT26N Ball # H23 H24 G24 J24 K23 E25 E26 L22 L23 F25 F26 L24 K24 G25 G26 M24 M23 L26 L25 N24 N23 M26 M25 H25 H26 J25 J26 K26 K25 P24 N25 R23 R22 P25 N26 R24 T23 U22 U23 P26 R26 T26 T25 U26 Fairchild Semiconductor [Rev. 1.8] 3/21/02 31 OCX1601 Crosspoint Switch--Advanced Datasheet Table 19 Ball Name OUT26P OUT27N OUT27P OUT28N OUT28P OUT29N OUT29P OUT30N OUT30P OUT31N OUT31P OUT32N OUT32P OUT33N OUT33P OUT34N OUT34P OUT35N OUT35P OUT36N OUT36P OUT37N OUT37P OUT38N OUT38P OUT39N OUT39P OUT40N OUT40P OUT41N OUT41P OUT42N OUT42P OUT43N OUT43P OUT44N OUT44P OUT45N OUT45P OUT46N OUT46P OUT47N OUT47P OUT48N OUT48P OUT49N OUT49P OCX1601 Pinout By Ball Name (Continued) Ball # Ball Name G2 F1 F2 E2 E1 G3 G4 F4 F3 C2 C1 D2 D1 AD22 AD23 AB6 AC5 AD4 AF2 AE1 AD1 AD2 AB4 AA5 E3 E4 F5 B1 D3 E6 D5 C4 C5 AB21 AC25 A25 D22 C23 D24 F22 E23 E24 E9 E10 E18 J5 J22 VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # Ball Name U25 V24 V25 T24 R25 V23 U24 W26 V26 W23 W22 W24 W25 AB26 AC26 Y25 Y26 AA25 AA26 AA24 AB25 Y23 Y24 AB23 AB24 AA22 AA23 AC3 AC2 AA4 Y5 AB3 AB2 Y4 W4 Y3 Y2 W3 V4 V1 V2 V3 U4 AC1 AB1 T5 T4 OUT50N OUT50P OUT51N OUT51P OUT52N OUT52P OUT53N OUT53P OUT54N OUT54P OUT55N OUT55P OUT56N OUT56P OUT57N OUT57P OUT58N OUT58P OUT59N OUT59P OUT60N OUT60P OUT61N OUT61P OUT62N OUT62P OUT63N OUT63P OUT64N OUT64P OUT65N OUT65P OUT66N OUT66P OUT67N OUT67P OUT68N OUT68P OUT69N OUT69P OUT70N OUT70P OUT71N OUT71P OUT72N OUT72P OUT73N Ball # Ball Name AA2 AA3 Y1 AA1 U3 U2 R4 R3 P3 P4 R2 R1 W1 W2 U1 T1 T2 T3 N3 P2 M4 M5 P1 N1 M3 L4 M2 L3 N2 M1 L1 L2 K1 K2 J1 J2 K5 K4 K3 J3 J4 H3 H4 H5 H1 H2 G1 OUT73P OUT74N OUT74P OUT75N OUT75P OUT76N OUT76P OUT77N OUT77P OUT78N OUT78P OUT79N OUT79P RCA0 RCA1 RCA2 RCA3 RCA4 RCA5 RCA6 RCB0 RCB1 RCB2 RCB3 RCB4 RCB5 RCB6 RC_CLK# RC_EN# RCI0 RCI1 RCI2 RCI3 RCO0 RCO1 RCO2 SCLK SDI SDO SMS SRST# UPDATE# VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE Ball # Ball Name K22 U5 V5 V22 AB9 AB17 AB18 E7 E12 E16 E19 AB8 AB11 AB15 AB20 G5 H22 L5 M22 R5 T22 W5 Y22 A1 A2 A26 B2 B25 C3 C24 D4 D14 D23 E5 E13 E14 E17 E22 N4 N5 N22 P5 P22 P23 AB5 AB10 AB13 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # AB14 AB22 AC4 AC13 AC23 AC24 AD3 AD24 AE2 AE25 AF1 AF26 32 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet 6. Package Information 6.1 PB420 Package Information (BOTTOM VIEW) (TOP VIEW) (SIDE VIEW) Figure 15 OCX1601 Package--Bottom, Top and Side Views Fairchild Semiconductor [Rev. 1.8] 3/21/02 33 OCX1601 Crosspoint Switch--Advanced Datasheet 6.2 Package Thermal Characteristics Table 20 Package PBGA NOTE: 1. Thermal performance values are based on simulation data. Package Thermal Coefficients Pin Count 420 JC(C/W) JA(C/W) Still Air 1.7C/W 12C/W 34 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet 7. Power Consumption Chip power, consists of three integral elements (refer to Figure 16): 1. Input Power--This element has two components: * * a steady state component that is always ON, and a component that is based on the number of inputs being used. 2. Core Power--This element is the same for LVPECL or LVDS outputs. Core power is a function of data rate (Mb/s) and the number of connection paths through the switch matrix. 3. Output Power--This element is a fixed amount for each differential output. The value is zero if the Output Enable (OE#) is disabled or set to OFF. 7.1 Power for LVPECL I/O Input Power (always ON) Core Power Output Power Switch Matrix OE# Output Buffer (320mW + 10mW/Input) + 0.015mW/Mbs/Connection + 37mW/Output Example: Worst Case = (320mW + 800mW) + (0.015 mW x 1600 x 80) + (37mW x 80) 1120mW + 1920mW + 2960mW = 6.00 watts Figure 16 Power Consumption Diagram for the OCX1601 using LVPECL Fairchild Semiconductor [Rev. 1.8] 3/21/02 35 OCX1601 Crosspoint Switch--Advanced Datasheet 8. Component Availability and Ordering Information OCXxxxs - PP###T Family # I/O Ports Speed Grade Blank = 667 Mb/s 1 = 1.6 Gb/s Package Code PB420 = Ball Grid Array Temperature Range Blank - Commercial (0C to 70C) I - Industrial (-40C to +85C) 9. Glossary CROSSPOINT: A single cell controlled by two RAM bits. The RAM bits are connected in a master-slave configuration to provide an update for programming and changing program information all at once. CROSSPOINT ARRAY: An array of Crosspoint cells used to connect any input port to any output port. INPUT OR OUTPUT PATH: The signal flow from pin to array and array to pin. Each path has a register with selectable clocks, drivers for the loaded outputs with selectable enables, and sense circuits to detect changes on either side of the IO Buffer. PORT: A name followed by a number to identify a pin on the device. RAPIDCONFIGURE: A parallel programming method for the OCX devices. The RC mode uses 23 dedicated pins to program the Crosspoint Array and the IO Buffers. The 23 pins consist of an enable, a clock, four instruction bits, two seven-bit address fields, and a three-bit data field. 36 [Rev. 1.8] 3/21/02 Fairchild Semiconductor OCX1601 Crosspoint Switch--Advanced Datasheet Revision History Date/ 11/14/2000 12/1/00 Version No. Revision 1.0 Revision 2.0 Description Preliminary release of "Advanced" mini datasheet. Changed device name from 160-1G to 1601; changes to Functional Block Diagram - RCO changed from [4:0] to [2:0] and added SRST# to Serial Programming Interface; changes to Component Ordering number. Expanded mini datasheet to full datasheet; added new power consumption diagrams; replaced RCO4 with RCO2; changed RCO3, RCO2, CLKP, and CLKN to NC (no connects) on pinout drawing and tables; split the AC Electrical table into one for LVPECL and one for LVDS. Corrected Pinout tables to match Pinout drawing. Table 22: AC25 was NC; now RCO1 AD25 was RCO3; now NC IN22N was AE13; now AE12 T4 was OUT49N; now OUT49P T5 was OUT49P; now OUT49N Table 23: IN07P was AD20; now AE20 IN22N was AE13; now AE12 OUT49P is now OUT49N for T5 OUT49N is now OUT49P for T4 OUT50P is now OUT50N for AA2 OUT50N is now OUT50P for AA3 Removed CLKP and CLKN from pin description table (Table 11) 2/14/2001 Revision 2.2 Removed statement "The output buffers are programmable..." in section 1.1, "Input and Output Buffers", and removed CLK reference; changed Min and Max specs in Table 19, "LVPECL DC Electrical Specifications"; changed description for RapidConfigure Programming Instruction 1101 in Table 2; changed "Pass Transistor" verbiage in Introduction to "Proprietary High-performance Buffering Circuit"; description updates to RC Programming Instructions 0010 and 1101; corrected "Receiving LVPECL..." and "Receiving LVDS..." diagrams to include the resistor; updates to LVPECL and LVDS "Output Enable..." AC electrical specs; changed pin signals for AF25 and AE26 on pinout drawing and tables from NC to Vss; replaced "CLK" with "OE#" on LVPECL and LVDS power consumption drawings. Made LVPECL standard for OCX1601; updated definitions for ImpliedDisconnect; integrated on-chip termination resistors; replaced LVPECL Signal circuit drawings and Power Consumption drawings with updated versions; changes/corrections to LVPECL DC Electrical Specs table. Corrections to LVPECL power consumption calculations; changed 667 Mb/s to 1600; changed 128 outputs to 80; added new information regarding input power. Changed LVPECL Dc Electrical specs table; added termination impedance values Changed pin names of AE26 and AF25 on Figure 14 (package pinout) from Vss to NC; Table 2--Corrected input/output descriptions for RCA and RCB pins in instructions 0101, 1000, 1001, and 1010; Table 11--changed count on # of pins for Vss (from 38 to 36) and NC (from 3 to 5); Tables 18 & 19--changed pin name of AE26 from Vss to NC and AF25 from Vss to NC. Added Output Jitter and Duty Cycle Distortion specs to AC Electrical table 12/28/00 Revision 2.1 4/52001 Revision 2.3 5/21/01 7/27/01 8/7/01 Revision 2.4 Revision 2.5 Revision 2.6 9/17/01 Revision 2.7 Fairchild Semiconductor [Rev. 1.8] 3/21/02 37 OCX1601 Crosspoint Switch--Advanced Datasheet 10.Product Status Definition Datasheet Identification Advanced Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specification may change in any manner without notice. This datasheet contains the preliminary data, and supplementary data will be published at a later date. Fairchild reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This datasheet contains final specifications. Fairchild reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This datasheet contains specifications for a product that has been discontinued by Fairchild. The datasheet is provided for reference information only. Preliminary Preproduction Product No Identification Full Production Obsolete No longer in Production Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuity and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATIONS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect is safety of effectiveness. www.fairchildsemi.com 38 [Rev. 1.8] 3/21/02 Fairchild Semiconductor |
Price & Availability of OCX1601
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |