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| NTD60N02R Power MOSFET 60 Amps, 24 Volts N-Channel DPAK Features * * * * * Planar HD3e Process for Fast Switching Performance Low RDS(on) to Minimize Conduction Loss Low Ciss to Minimize Driver Loss Low Gate Charge Optimized for High Side Switching Requirements in High-Ef ficiency DC-DC Converters http://onsemi.com V(BR)DSS 24 V RDS(on) TYP 8.0 mW @ 4.5 V N-Channel D ID MAX 60 A MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Thermal Resistance - Junction-to-Case Total Power Dissipation @ TA = 25C Drain Current Continuous @ TA = 25C, Chip Continuous @ TA = 25C, Limited by Package Continuous @ TA = 25C, Limited by Wires Thermal Resistance Junction-to-Ambient (Note 1) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C Thermal Resistance Junction-to-Ambient (Note 2) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C Operating and Storage Temperature Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 50 Vdc, VGS = 10.0 Vdc, IL = 11 Apk, L = 1.0 mH, RG = 25 W) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS RqJC PD ID ID ID RqJA PD ID RqJA PD ID TJ, and Tstg EAS Value 24 20 2.6 48 60 50 32 80 1.56 9.3 120 1.04 7.6 - 55 to 150 60 Unit Vdc Vdc C/W W A A A C/W W A C/W W A C mJ 12 3 CASE 369C DPAK (Surface Mount) STYLE 2 4 S 1 G 4 2 3 CASE 369D DPAK (Straight Lead) STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENTS 4 Drain YWW T60 N02R 4 Drain YWW T60 N02R 123 Gate Drain Source Package DPAK DPAK DPAK Straight Lead Shipping 75 Units/Rail 2500 Tape & Reel 75 Units/Rail Publication Order Number: NTD60N02R/D TL 260 C 2 1 3 Drain Gate Source 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2. When surface mounted to an FR4 board using 0.5 sq. in. drain pad size. Y = Year WW = Work Week 60N02R = Device Code ORDERING INFORMATION Device NTD60N02R NTD60N02RT4 NTD60N02R-1 (c) Semiconductor Components Industries, LLC, 2003 1 May, 2003 - Rev. 4 NTD60N02R ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (Note 3) (VGS = 4.5 Vdc, ID = 15 Adc) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 30 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 15 Adc) (Note 3) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4) Turn-On Delay Time Rise Time Turn-Of f Delay Time Fall Time Gate Charge (VGS = 4.5 Vdc, ID = 30 Adc, VDS = 10 Vdc) (Note 3) SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage On Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 3) (IS = 30 Adc, VGS = 0 Vdc) (IS = 15 Adc, VGS = 0 Vdc, TJ = 125C) Ad Vd 125 C) (IS = 30 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 3) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. VSD 0.88 1.10 0 80 0.80 15.5 12.6 2.6 0.005 1.2 mC Vdc (VGS = 10.0 Vdc, VDD = 10 Vdc, ID = 30 Adc, RG = 3.0 W) td(on) tr td(off) tf QT Q1 Q2 7.0 53 14 10 8.4 3.7 4.04 nC ns (VDS = 20 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss 948 456 160 1330 640 225 pF VGS(th) 1.0 RDS(on) gFS 11.2 8.0 8.2 27 12.5 10.5 Mhos 1.5 4.1 2.0 Vdc mV/C mW V(BR)DSS 24 IDSS IGSS 1.5 10 100 nAdc 27.5 25.5 Vdc mV/C mAdc Symbol Min Typ Max Unit Reverse Recovery Time trr ta tb Qrr ns http://onsemi.com 2 NTD60N02R 120 100 80 60 40 VGS = 3.0 V 20 0 0 2 4 6 VGS = 2.5 V 8 10 VGS = 10 V ID, DRAIN CURRENT (A) VGS = 8.0 V VGS = 6.0 V VGS = 5.5 V VGS = 5.0 V VGS = 3.5 V VGS = 4.5 V 120 VDS w 10 V 100 80 60 40 TJ = 25C 20 0 0 1 2 3 5 6 VDS, DRAIN-TO-SOURCE VOLTAGE (V) TJ = 150C TJ = -55C ID, DRAIN CURRENT (A) VGS = 4.0 V VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.028 VGS = 10 V 0.024 0.02 0.016 0.012 TJ = 125C 0.008 0.004 10 20 30 40 50 60 70 80 90 100 110 120 ID, DRAIN CURRENT (A) TJ = -55C TJ = 25C RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.028 VGS = 4.5 V 0.024 0.02 0.016 TJ = 25C 0.012 0.008 0.004 10 TJ = -55C TJ = 150C TJ = 125C TJ = 150C 20 30 40 50 60 70 80 90 100 110 120 ID, DRAIN CURRENT (A) Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Temperature RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 -50 ID = 30 A VGS = 4.5 V and 10 V 10000 TJ = 150C IDSS, LEAKAGE (nA) 1000 TJ = 125C 100 TJ = 100C 10 -25 0 25 50 75 100 125 150 0 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 3 NTD60N02R 2000 Ciss 1600 C, CAPACITANCE (pF) VDS = 0 V VGS = 0 V TJ = 25C VGS, GATE-T O-SOURCE (V) 8 VGS 6 Q1 4 QT Q2 10 1200 Ciss 800 Crss Coss 400 Crss 0 10 5 VGS 0 VDS 5 10 15 20 2 ID = 30 A TJ = 25C 0 4 8 12 16 0 GATE-T O-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge 1000 IS, SOURCE CURRENT (A) VDS = 10 V ID = 30 A VGS = 10 V t, TIME (ns) 100 tr td(off) 10 tf td(on) 60 50 40 30 20 TJ = 150C 10 0 TJ = 25C 1 1 10 RG, GATE RESISTANCE (W) 100 0 0.2 0.4 0.6 0.8 1 VSD, SOURCE-TO-DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current 100 VGS = 20 V SINGLE PULSE 10 ms ID, DRAIN CURRENT (A) TC = 25C 100 ms 10 1 ms 10 ms RDS(ON) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 dc 1 100 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 NTD60N02R r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE t1 t2 DUTY CYCLE, D = t1/t2 0.001 0.01 t, TIME (s) 0.1 P(pk) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t) 0.01 0.00001 0.0001 1 10 Figure 12. Thermal Response http://onsemi.com 5 NTD60N02R INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection 6.20 0.244 interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm inches http://onsemi.com 6 NTD60N02R PACKAGE DIMENSIONS DPAK CASE 369C-01 ISSUE O -TB V R 4 SEATING PLANE C E DIM A B C D E F G H J K L R S U V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 --0.035 0.050 0.155 --MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 --0.89 1.27 3.93 --- A S 1 2 3 Z U K F L D G 2 PL J H 0.13 (0.005) M T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN http://onsemi.com 7 NTD60N02R PACKAGE DIMENSIONS DPAK CASE 369D-01 ISSUE O B V R 4 C E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 --MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 --- Z A 3 S -TSEATING PLANE 1 2 K F D G 3 PL J H 0.13 (0.005) M DIM A B C D E F G H J K R S V Z T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 NTD60N02R/D |
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