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| DS90CR286A/DS90CR216A +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link -- 66 MHz, +3.3V Rising Edge Data Strobe LVDS Receiver 21-Bit Channel Link-- 66 MHz June 1999 DS90CR286A/DS90CR216A +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link-- 66 MHz, +3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link-- 66 MHz 1.0 General Description The DS90CR286A receiver converts the four LVDS data streams (Up to 1.848 Gbps throughput or 231 Megabytes/ sec bandwidth) back into parallel 28 bits of CMOS/TTL data. Also available is the DS90CR216A that converts the three LVDS data streams (Up to 1.386 Gbps throughput or 173 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data. Both Receivers' outputs are Rising edge strobe. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. 2.0 Features n n n n n n n n n n 20 to 66 MHz shift clock support 50% duty cycle on receiver output clock Best-in-Class Set & Hold Times on RxOUTPUTs Rx power consumption <270 mW (typ) @66MHz Worst Case Rx Power-down mode <200W (max) ESD rating >7 kV (HBM), >700V (EIAJ) PLL requires no external components Compatible with TIA/EIA-644 LVDS standard Low profile 56-lead or 48-lead TSSOP package Operating Temperature: -40C to +85C 3.0 Block Diagrams DS90CR286A DS90CR216A DS100873-31 Order Number DS90CR216AMTD See NS Package Number MTD48 DS100873-30 Order Number DS90CR286AMTD See NS Package Number MTD56 TRI-STATE (R) is a registered trademark of National Semiconductor Corporation. (c) 1999 National Semiconductor Corporation DS100873 www.national.com 4.0 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. -0.3V to +4V Supply Voltage (VCC) CMOS/TTL Output Voltage -0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage -0.3V to (VCC + 0.3V) Junction Temperature +150C Storage Temperature -65C to +150C Lead Temperature (Soldering, 4 sec) +260C Maximum Package Power Dissipation Capacity @ 25C MTD56 (TSSOP) Package: DS90CR286A 1.61 W MTD48 (TSSOP) Package: DS90CR216A 1.89 W Package Derating: DS90CR286A DS90CR216A ESD Rating (HBM, 1.5 k, 100 pF) (EIAJ, 0, 200 pF) 12.4 mW/C above +25C 15 mW/C above +25C > 7 kV > 700V 5.0 Recommended Operating Conditions Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC) Min 3.0 -40 0 Nom 3.3 +25 Max 3.6 +85 2.4 100 Units V C V mVPP Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol VOH VOL IOS VTH VTL I IN Parameter High Level Output Voltage Low Level Output Voltage Output Short Circuit Current Differential Input High Threshold Differential Input Low Threshold Input Current V V RECEIVER SUPPLY CURRENT ICCRW Receiver Supply Current Worst Case CL = 8 pF, Worst Case Pattern, DS90CR286A (Figures 1, 2 ), TA=-10C to +70C CL = 8 pF, Worst Case Pattern, DS90CR286A (Figures 1, 2 ), TA=-40C to +85C CL = 8 pF, Worst Case Pattern, DS90CR216A (Figures 1, 2 ), TA=-10C to +70C CL = 8 pF, Worst Case Pattern, DS90CR216A (Figures 1, 2 ), TA=-40C to +85C Power Down = Low Receiver Outputs Stay Low during Power Down Mode f = 33 MHz f = 37.5 MHz f = 66 MHz f = 40 MHz 49 53 81 53 65 70 105 70 mA mA mA mA IN IN Conditions IOH = -0.4 mA IOL = 2 mA VOUT = 0V V = +1.2V Min 2.7 Typ 3.3 0.06 -60 Max Units V CMOS/TTL DC SPECIFICATIONS 0.3 -120 +100 -100 = +2.4V, VCC = 3.6V = 0V, VCC = 3.6V V mA mV mV A A LVDS RECEIVER DC SPECIFICATIONS CM 10 10 ICCRW Receiver Supply Current Worst Case f = 66 MHz 81 105 mA ICCRW Receiver Supply Current Worst Case f = 33 MHz f = 37.5 MHz f = 66 MHz f = 40 MHz 49 53 78 53 55 60 90 60 mA mA mA mA ICCRW Receiver Supply Current Worst Case f = 66 MHz 78 90 mA ICCRZ Receiver Supply Current Power Down 10 55 A www.national.com 2 Electrical Characteristics (Continued) Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. Note 2: Typical values are given for VCC = 3.3V and TA = +25C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and V OD). Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol CLHT CHLT RSPos0 RSPos1 RSPos2 RSPos3 RSPos4 RSPos5 RSPos6 RSPos0 RSPos1 RSPos2 RSPos3 RSPos4 RSPos5 RSPos6 RSKM RCOP RCOH RCOL RSRC RHRC RCOH RCOL RSRC RHRC RCCD RPLLS RPDD Parameter CMOS/TTL Low-to-High Transition Time (Figure 2 ) CMOS/TTL High-to-Low Transition Time (Figure 2 ) Receiver Input Strobe Position for Bit 0 (Figure 9, Figure 10) Receiver Input Strobe Position for Bit 1 Receiver Input Strobe Position for Bit 2 Receiver Input Strobe Position for Bit 3 Receiver Input Strobe Position for Bit 4 Receiver Input Strobe Position for Bit 5 Receiver Input Strobe Position for Bit 6 Receiver Input Strobe Position for Bit 0 (Figure 9, Figure 10) Receiver Input Strobe Position for Bit 1 Receiver Input Strobe Position for Bit 2 Receiver Input Strobe Position for Bit 3 Receiver Input Strobe Position for Bit 4 Receiver Input Strobe Position for Bit 5 Receiver Input Strobe Position for Bit 6 RxIN Skew Margin (Note 4) (Figure 11 ) RxCLK OUT Period (Figure 3) RxCLK OUT High Time (Figure 3 ) RxCLK OUT Low Time (Figure 3) RxOUT Setup to RxCLK OUT (Figure 3 ) RxOUT Hold to RxCLK OUT (Figure 3 ) RxCLK OUT High Time (Figure 3 ) RxCLK OUT Low Time (Figure 3) RxOUT Setup to RxCLK OUT (Figure 3 ) RxOUT Hold to RxCLK OUT (Figure 3 ) RxCLK IN to RxCLK OUT Delay 25C, VCC = 3.3V (Note 5)(Figure 4 ) Receiver Phase Lock Loop Set (Figure 5 ) Receiver Power Down Delay (Figure 8 ) f = 66 MHz f = 40 MHz f = 40 MHz f = 66 MHz f = 66 MHz f = 40 MHz 1.0 4.5 8.1 11.6 15.1 18.8 22.5 0.7 2.9 5.1 7.3 9.5 11.7 13.9 490 400 15 10.0 10.0 6.5 6.0 5.0 5.0 4.5 4.0 3.5 T 12.2 11.0 11.6 11.6 7.6 6.3 7.3 6.3 5.0 7.5 10 1 50 Min Typ 2 1.8 1.4 5.0 8.5 11.9 15.6 19.2 22.9 1.1 3.3 5.5 7.7 9.9 12.1 14.3 Max 5 5 2.15 5.8 9.15 12.6 16.3 19.9 23.6 1.4 3.6 5.8 8.0 10.2 12.4 14.6 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ns ns ns ns ns ns ns ns ns ns ms s Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 250 ps). Note 5: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency for the 215/285 transmitter and 216A/286A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period. 3 www.national.com 6.0 AC Timing Diagrams DS100873-2 FIGURE 1. "Worst Case" Test Pattern DS100873-4 FIGURE 2. DS90CR286A/DS90CR216A (Receiver) CMOS/TTL Output Load and Transition Times DS100873-5 FIGURE 3. DS90CR286A/DS90CR216A (Receiver) Setup/Hold and High/Low Times DS100873-6 FIGURE 4. DS90CR286A/DS90CR216A (Receiver) Clock In to Clock Out Delay www.national.com 4 6.0 AC Timing Diagrams (Continued) DS100873-7 FIGURE 5. DS90CR286A/DS90CR216A (Receiver) Phase Lock Loop Set Time DS100873-9 FIGURE 6. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CR286A DS100873-10 FIGURE 7. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CR216A 5 www.national.com 6.0 AC Timing Diagrams (Continued) DS100873-8 FIGURE 8. DS90CR286A/DS90CR216A (Receiver) Power Down Delay DS100873-25 FIGURE 9. DS90CR286A (Receiver) LVDS Input Strobe Position www.national.com 6 6.0 AC Timing Diagrams (Continued) DS100873-26 FIGURE 10. DS90CR216A (Receiver) LVDS Input Strobe Position 7 www.national.com 6.0 AC Timing Diagrams (Continued) DS100873-11 C -- Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos -- Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 6) + ISI (Inter-symbol interference) (Note 7) Cable Skew -- typically 10 ps-40 ps per foot, media dependent Note 6: Cycle-to-cycle jitter is less than TBD ps at 66 MHz. Note 7: ISI is dependent on interconnect length; may be zero. FIGURE 11. Receiver LVDS Input Skew Margin www.national.com 8 7.0 DS90CR286A Pin Description -- 28-Bit Channel Link Receiver Pin Name RxIN+ RxIN- RxOUT RxCLK IN+ RxCLK IN- RxCLK OUT PWR DOWN V CC GND PLL V CC PLL GND LVDS V CC LVDS GND I/O I I O I I O I I I I I I I No. 4 4 28 1 1 1 1 4 5 1 2 1 3 Description Positive LVDS differentiaI data inputs. Negative LVDS differential data inputs. TTL level data outputs. Positive LVDS differential clock input. Negative LVDS differential clock input. TTL Ievel clock output. The rising edge acts as data strobe. TTL level input. When asserted (low input) the receiver outputs are low. Power supply pins for TTL outputs. Ground pins for TTL outputs. Power supply for PLL. Ground pin for PLL. Power supply pin for LVDS inputs. Ground pins for LVDS inputs. 8.0 DS90CR216A Pin Description -- 21-Bit Channel Link Receiver Pin Name RxIN+ RxIN- RxOUT RxCLK IN+ RxCLK IN- RxCLK OUT PWR DOWN V CC GND PLL V CC PLL GND LVDS V CC LVDS GND I/O I I O I I O I I I I I I I No. 3 3 21 1 1 1 1 4 5 1 2 1 3 Description Positive LVDS differentiaI data inputs. (Note 8) Negative LVDS differential data inputs. (Note 8) TTL level data outputs. Positive LVDS differential clock input. Negative LVDS differential clock input. TTL Ievel clock output. The rising edge acts as data strobe. TTL level input. When asserted (low input) the receiver outputs are low. Power supply pins for TTL outputs. Ground pins for TTL outputs. Power supply for PLL. Ground pin for PLL. Power supply pin for LVDS inputs. Ground pins for LVDS inputs. Note 8: These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions receiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the clock input is also floating/terminated outputs will remain in the last valid state. A floating/terminated clock input will result in a LOW clock output. 9 www.national.com 9.0 Pin Diagram DS90CR286A DS90CR216A DS100873-13 DS100873-23 www.national.com 10 10.0 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90CR286AMTD NS Package Number MTD56 11 www.national.com DS90CR286A/DS90CR216A +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link -- 66 MHz, +3.3V Rising Edge Data Strobe LVDS Receiver 21-Bit Channel Link-- 66 MHz 10.0 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90CR216AMTD NS Package Number MTD48 LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Francais Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. |
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