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DS3893A BTL TURBOTRANSCEIVER
March 1997
DS3893A BTL TURBOTRANSCEIVERTM
General Description
The TURBOTRANSCEIVER is designed for use in very high speed bus systems. The bus terminal characteristics of the TURBOTRANSCEIVER are referred to as "Backplane Transceiver Logic" (BTL). BTL is a new logic signaling standard that has been developed to enhance the performance of backplane buses. BTL compatible transceivers feature low output capacitance drivers to minimize bus loading, a 1V nominal signal swing for reduced power consumption and receivers with precision thresholds for maximum noise immunity. This new standard eliminates the settling time delays, that severely limit the TTL bus performance, to provide significantly higher bus transfer rates. The TURBOTRANSCEIVER is compatible with the requirements of the proposed IEEE 896 Futurebus draft standard. It is similar to the DS3896/97 BTL TRAPEZOIDALTM Transceivers but the trapezoidal feature has been removed to improve the propagation delay. A stripline backplane is therefore required to reduce the crosstalk induced by the faster rise and fall times. This device can drive a 10 load with a typical propagation delay of 3.5 ns for the driver and 5 ns for the receiver. When multiple devices are used to drive a parallel bus, the driver enables can be tied together and used as a common control line to get on and off the bus. The driver enable delay is designed to be the same as the driver propagation delay in order to provide maximum speed in this configuration. The low input current on the enable pin eases the drive required for the common control line. The bus driver is an open collector NPN with a Schottky diode in series to isolate the transistor output capacitance from the bus when the driver is in the inactive state. The active output low voltage is typically 1V. The bus is intended to be operated with termination resistors (selected to match the bus impedance) to 2.1V at both ends. Each of the resistors can be as low as 20.
Features
n Fast single ended transceiver (typical driver enable and receiver propagation delays are 3.5 ns and 5 ns) n Backplane Transceiver Logic (BTL) levels (1V logic swing) n Less than 5 pF bus-port capacitance n Drives densely loaded backplanes with equivalent load impedances down to 10 n 4 transceivers in 20 pin PCC package n Specially designed for stripline backplanes n Separate bus ground returns for each driver to minimize ground noise n High impedance, MOS and TTL compatible inputs n TRI-STATETM control for receiver outputs n Built-in bandgap reference provides accurate receiver threshold n Glitch free power up/down protection on all outputs n Oxide isolated bipolar technology
Connection and Logic Diagram
DS008698-1
Order Number DS3893AV See NS Package Number V20A
TRI-STATE (R) is a registered trademark of National Semiconductor Corporation. TRAPEZOIDALTM and TURBOTRANSCEIVERTM are trademarks of National Semiconductor Corp.
(c) 1999 National Semiconductor Corporation
DS008698
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Control Input Voltage Driver Input and Receiver Output Driver Output Receiver Input Clamp Current Power Dissipation at 70C 6.5V 5.5V 5.5V
Storage Temperature Range Lead Temperature (Soldering, 3 sec.)
-65C to +150C 260C
Recommended Operating Conditions
Supply Voltage, VCC Bus Termination Voltage (VT) Operating Free Air Temperature Min 4.5 2.0 0 Max 5.5 2.2 70 Units V V C
15 mA 900 mW
Electrical Characteristics (Notes 2, 3, 4)
TA = 0 to +70C, VCC = 5V 10% Symbol VIH VIL II IIH IIL Parameter Input High Voltage Input Low Voltage Input Leakage Current Input High Current Dn Input Low Current DE Input Low Current RE Input Low Current VCL VOLB Input Diode Clamp Voltage Output Low Bus Voltage DRIVER OUTPUT/RECEIVER INPUT: (Bn) Dn = DE = VIH (Figure 2) RT = 10, VT = 2.2V Dn = DE = VIH (Figure 2) RT = 18.5, VT = 2.14 Dn = DE = 0.8V, VCC = Max Bn = 0.75V Dn = DE = 0.8V, VCC = 0V Bn = 1.2V VCC = Max or 0V, Bn = 1 mA VCC = Max or 0V, Bn = 10 mA VCC = Max, Dn = 0.8V (Figure 2) VT = 2.0V, RT = 10 0.75 0.75 -250 1.0 1.0 1.2 1.1 100 100 2.9 3.2 1.90 1.47 Bn = 1.2V, Ioh = -3 mA, RE = 0.8V Bn = 2V, Iol = 6 mA, RE = 0.8V Vo = 2.5V, RE = 2V Vo = 0.5V, RE = 2V Bn = 1.2V, Vo = 0V RE = 0.8V, VCC = Max Dn = DE = RE = VIH, VCC = Max 2.5V 0.35 0.5 20 -20 -80 -120 70 -200 95 1.55 1.62 V V A A V V V V V V A A mA mA DE = RE = Dn = VCC DE = RE = Dn = 2.5V Dn = 0.5V, DE = VCC = Max DE = 0.5V, Dn = VCC = Max RE = 0.5V, VCC = Max Iclamp = -12 mA Conditions Min 2.0 0.8 100 20 -200 -500 -100 -1.2 Typ Max Units V V A A A A A V DRIVER AND CONTROL INPUT: (DE, RE , Dn)
IILB IIHB VOCB VOHB VTH VOH VOL IOZ IOS ICC
Output Bus Current (Power On) Output Bus Current (Power Off) Driver Output Positive Clamp Output High Bus Voltage Receiver Input Threshold Voltage Output High Voltage Output Low TRI-STATE Leakage Output Short Circuit Current (Note 5) Supply Current
RECEIVER OUTPUT: (Rn)
Note 1: "Absolute maximum ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of "Electrical Characteristics" provide conditions for actual device operation. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. Note 3: All typicals are given for VCC = 5V and TA = 25C. Note 4: Unused inputs should not be left floating. Tie unused inputs to either VCC or GND thru a resistor. Note 5: Only one output at a time should be shorted.
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Switching Characteristics
TA = 0 to +70C, VCC = 5V 10% Symbol tPHL tPLH tr tf tskew Parameter Driver Input to Output Driver Input to Output Output Rise time Output Fall Time Skew Between Drivers in Same Package DRIVER ENABLE: (Figure 3 and Figure 6) tPHL tPLH tPHL tPLH tskew Enable Delay Disable Delay Receiver Input to Output Receiver Input to Output Skew Between Receivers in Same Package RECEIVER ENABLE: (Figure 5 and Figure 8) tZL tZH tLZ tHZ Receiver Enable to Output Low Receiver Enable to Output High Receiver Disable From Output Low Receiver Disable From Output High CL = 50 pF, RL = 500, DE = 0.3V S2 Open Bn = 2V CL = 50 pF, RL = 500, DE = 0.3V S1 OpenBn = 1V CL = 50 pF, RL = 500, DE = 0.3V S2 OpenBn = 2V CL = 50 pF, RL = 500, DE = 0.3V S1 OpenBn = 1V 2 2 1 1 6 5 5 4 12 12 8 8 ns ns ns ns VT = 2V, RT = 10, CL = 30 pF, Dn = 3V VT = 2V, RT = 10, CL = 30 pF, Dn = 3V CL = 50 pF, RE = DE = 0.3V, S3 Closed CL = 50 pF, RE = DE = 0.3V, S3 Open (Note 6) 1 1 2 2 3.5 3.5 5 5 1 7 7 8 8 ns ns ns ns ns Conditions VT = 2V RT = 10, CL = 30 pF, DE = 3V VT = 2V, RT = 10, CL = 30 pF, DE = 3V VT = 2V, RT = 10, CL = 30 pF, DE = 3V VT = 2V, RT = 10, CL = 30 pF, DE = 3V (Note 6) Min 1 1 1 1 Typ 3.5 3.5 2 2 1 Max 7 7 5 5 Units ns ns ns ns ns DRIVER: (Figure 3 and Figure 6)
RECEIVER: (Figure 4 and Figure 7)
Note 6: tD and tR skew is an absolute value, defined as differences seen in propagation delays between each of the drivers or receivers in the same package of the same delay, VCC, temperature and load conditions.
DS008698-2 DS008698-12
Note: n = 1, 2, 3, 4
FIGURE 1. Equivalent Bus Output
FIGURE 2. Driver Output Voltage
AC Test Circuits
DS008698-3
FIGURE 3.
3
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AC Test Circuits
(Continued)
DS008698-4
FIGURE 4.
DS008698-5
Note: Unless Otherwise Specified The Switches are Closed
FIGURE 5.
Switching Time Waveforms
DS008698-6
FIGURE 6. Driver Propagation Delay
DS008698-7
FIGURE 7. Receiver Propagation Delay
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4
Switching Time Waveforms
(Continued)
DS008698-8
Note: tR = tF 4 ns From 10% to 90%
Note: n = 1, 2, 3, 4
FIGURE 8. Receiver Enable and Disable Times
Typical Application
DS008698-9
Application Information
Due to the high current and very high speed capability of the TURBOTRANSCEIVER's driver output stage, circuit board layout and bus grounding are critical factors that affect the system performance. Each of the TURBOTRANSCEIVER's bus ground pins should be connected to the nearest backplane ground pin with the shortest possible path. The ground pins on the connector should be distributed evenly through its length. Although the bandgap reference receiver threshold provides sufficient DC noise margin (Figure 9), ground noise and ringing on the data paths could easily exceed this margin if the series inductance of the traces and connectors are not kept to a minimum. The bandgap ground pin should be returned to the connector through a separate trace that does not carry transient switching currents. The transceivers should be mounted as close as possible to the connector. It should be noted that even one inch of trace can add a significant amount of ringing to the bus signal.
DS008698-11 DS008698-10
FIGURE 10.
FIGURE 9. Noise Margin
5
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DS3893A BTL TURBOTRANSCEIVER
Physical Dimensions
inches (millimeters) unless otherwise noted
Plastic Chip Carrier (V) Order Number DS3893AV NS Package Number V20A
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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