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| PRODUCT SPECIFICATION 433MHz Single Chip RF Transceiver )($785(6 * * * * * * * * * True single chip FSK transceiver Few external components required No set up or configuration No coding of data required 20kbit/s data rate 2 channels Wide supply range Very low power consumption Standby mode Q5) $33/,&$7,216 * * * * * * * * * Alarm and Security Systems Automatic Meter Reading (AMR) Home Automation Remote Control Surveillance Automotive Telemetry Toys Wireless Communication *(1(5$/ '(6&5,37,21 NRF401 is a true single chip UHF transceiver designed to operate in the 433MHz ISM (Industrial, Scientific and Medical) frequency band. It features Frequency Shift Keying (FSK) modulation and demodulation capability. NRF401 operates at bit rates up to 20kbit/s. Transmit power can be adjusted to a maximum of 10dBm. Antenna interface is differential and suited for low cost PCB antennas. NRF401 features a standby mode which makes power saving easy and efficient. NRF401 operates from a single +3-5V DC supply. As a primary application, NRF401 is intended for UHF radio equipment in compliance with the European Telecommunication Standard Institute (ETSI) specification EN 300 220-1 V1.2.1. 48,&. 5()(5(1&( '$7$ 3DUDPHWHU Frequency, Channel#1/Channel#2 Modulation Frequency deviation Max. RF output power @ 400, 3V Sensitivity @ 400, BR=20 kbit/s, BER<10-3 Maximum bit rate Supply voltage Receive supply current Transmit supply current @ -10 dBm output power Standby supply current 9DOXH 433.93 / 434.33 FSK 15 10 -105 20 2.7 - 5.25 250* 8 8 8QLW MHz kHz dBm dBm kbit/s V A mA A Table 1. NRF401 quick reference data 25'(5,1* ,1)250$7,21 7\SH QXPEHU NRF401-IC NRF401-EVKIT 'HVFULSWLRQ 9HUVLRQ A 1.0 20 pin SSOIC Evaluation kit with NRF401 IC Table 2. NRF401 ordering information. * The PWR_UP pin is used for power duty cycling. The duty-cycle is 2 % with a period of 200msec. Vestre Rosten 81, N-7075 Tiller, Norway QhtrA AsA & Nordic VLSI ASA Revision: 1.6 - Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU %/2&. ',$*5$0 DOUT TXEN CS DIN DEM LNA 10 19 12 9 16 ANT1 ANT2 15 PWR_UP 18 OSC PLL VCO PA 1 20 4 5 6 11 RF_PWR VCO INDUCTOR REFERENCE LOOP FILTER Figure 1. NRF401 block diagram with external components. 3,1 )81&7,216 3LQ 1DPH 1 2 3 4 5 6 7 8 9 10 11 12 3LQ IXQFWLRQ 'HVFULSWLRQ Crystal oscillator input Power supply (+3-5V DC) Ground (0V) Loop filter External inductor for VCO External inductor for VCO Ground (0V) Power supply (+3-5V DC) Data input Data output Transmit power setting Channel selection CS="0" 433.93MHz (Channel#1) CS="1" 434.33MHz (Channel#2) Power supply (+3-5V DC) Ground (0V) Antenna terminal Antenna terminal Ground (0V) Power on/off PWR_UP = "1" Power up (Operating mode) PWR_UP = "0" Power down (Standby mode) Transmit enable TXEN = "1" Transmit mode TXEN = "0" Receive mode Crystal oscillator output XC1 VDD VSS FILT1 VCO1 VCO2 VSS VDD DIN DOUT RF_PWR CS Input Power Ground Input Input Input Ground Power Input Output Input Input 13 14 15 16 17 18 VDD VSS ANT2 ANT1 VSS PWR_UP Power Ground Input/Output Input/Output Ground Input 19 TXEN Input 20 XC2 Output Table 3. NRF401 pin functions. Nordic VLSI ASA Revision: 1.6 Vestre Rosten 81, N-7075 Tiller, Norway QhtrA!AsA & Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU (/(&75,&$/ 63(&,),&$7,216 Conditions: VDD = +3V DC, VSS = 0V, TA= -25C to +85C 6\PERO VDD VSS IDD 3DUDPHWHU FRQGLWLRQ 0LQ 7\S 0D[ 8QLWV PRF VIH VIL VOH VOL IH IL f1 f2 f fIF BWIF fXTAL ZI Supply voltage 2.7 3 5.25 V Ground 0 V Total current consumption Receive mode 11 mA Transmit mode @ -10 dBm RF power 8 mA Stand by mode 8 A 10 dBm Max. RF output power @ 400 load Logic "1" input voltage VDD V 0.7VDD Logic "0" input voltage 0 V 0.3VDD Logic "1" output voltage (IOH = - 1.0mA) VDD V 0.7VDD Logic "0" output voltage (IOL = 1.0mA) 0 V 0.3VDD Logic "1" input current (VI = VDD) +20 A Logic "0" input current (VI = VSS) -20 A Channel#1 frequency 433.93 MHz Channel#2 frequency 434.33 MHz Dynamic range 90 dB Modulation type FSK Frequency deviation kHz 15 IF frequency 400 kHz IF bandwidth 65 85 kHz Crystal frequency 4.0 MHz ppm Crystal frequency stability requirement 1) 45 Loop filter voltage 3) 0.9 1.1 1.3 V -105 dBm Sensitivity @ 400,BR=20 kbit/s, BER < 10-3 Bit rate 0 20 kbit/s Recommended antenna port differential impedance 400 Spurious emission Compliant with EN 300-220-1 V1.2.1 2) Table 4. NRF401 electrical specifications. 1) Maximum 5dB sensitivity degradation at temperature extremes. See also page 11. With a PCB loop antenna or a differential to single ended matching network to a 50 antenna. 3) See also page 9, Loop filter. 2) $%62/87( 0$;,080 5$7,1*6 6XSSO\ YROWDJHV VDD ................................- 0.3V to +6V VSS .................................................. 0V ,QSXW YROWDJH VI .......................- 0.3V to VDD + 0.3V 2XWSXW YROWDJH VO ......................- 0.3V to VDD + 0.3V 3RZHU GLVVLSDWLRQ PD (TA=25C) ........................... 250mW 7HPSHUDWXUHV Operating Temperature.... -25C to +85C Storage Temperature...... -40C to +125C 1RWH 6WUHVV H[FHHGLQJ RQH RU PRUH RI WKH OLPLWLQJ YDOXHV PD\ FDXVH SHUPDQHQW GDPDJH WR WKH GHYLFH $77(17,21 Electrostatic Sensitive Device Observe Precaution for handling Nordic VLSI ASA Revision: 1.6 Vestre Rosten 81, N-7075 Tiller, Norway QhtrA"AsA & Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU 3,1 $66,*10(17 XC1 VDD VSS FILT1 VCO1 VCO2 VSS VDD DIN DOUT 1 2 3 4 5 6 7 8 9 10 20 XC2 19 TXEN NRF401 20 pin SSOIC 18 PWR_UP 17 VSS 16 ANT1 15 ANT2 14 VSS 13 VDD 12 CS 11 RF_PWR Figure 2. NRF401 pin assignment. 3$&.$*( 287/,1( NRF401, 20 pin SSOIC. (Dimensions in mm.) 20 19 18 E H 123 D A1 A e b L 3DFNDJH 7\SH 20 pin SSOIC (Wide) 0LQ 0D[ ' 6.90 7.50 ( 5.00 5.60 + 7.40 8.20 $ 2.00 $ 0.05 H 0.65 E 0.22 0.38 / 0.55 0.95 &RSO 0.10 D 0 8 Figure 3. SSOIC-20 Package outline. Nordic VLSI ASA Revision: 1.6 Vestre Rosten 81, N-7075 Tiller, Norway QhtrA#AsA & Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU ,03257$17 7,0,1* '$7$ 7LPLQJ LQIRUPDWLRQ The timing information for the different operations is summarised in Table 5. (TX is transmit mode, RX is receive mode and Std.by is Standby mode.) Change of Mode TX I RX RX I TX Std.byI TX Std.byI RX VDD=0 I TX VDD =0 I RX Name tTR tRT tST tSR tVT tVR Max Delay 3ms 1ms 2ms 3ms 4ms 5ms Condition Operational mode Start-up Table 5 Switching times for NRF401. 6ZLWFKLQJ 7; l 5; RSHUDWLRQDO PRGH When switching from RX-mode to TX-mode data (DIN) may not be sent before the TXEN-input has been high for at least 1ms, see Figure 4(a). When switching from TX-mode to RX-mode the receiver may not receive data (DOUT) before the TXEN-input has been low for at least 3ms, see Figure 4(b). RX to TX VDD VDD TX to RX PWR_UP PWR_UP TXEN TXEN DIN DOUT 1ms ms 0 2 4 0 3ms ms 2 4 (a) (b) Figure 4. Timing diagram for NRF401for switching from RX to TX (a) and TX to RX (b). 6ZLWFKLQJ EHWZHHQ VWDQGE\ DQG 5;PRGH RSHUDWLRQDO PRGH The time from the PWR_UP input is set to "1", until the data (DOUT) is valid is tSR,, see Table 5. Worst case tSR is 3ms for NRF401 as can be seen in Figure 5 (a). 6ZLWFKLQJ EHWZHHQ VWDQGE\ DQG 7;PRGH RSHUDWLRQDO PRGH The time from the PWR_UP input is set to "1", until the synthesised frequency is stable is tST, see Table 5. Nordic VLSI ASA Revision: 1.6 Vestre Rosten 81, N-7075 Tiller, Norway QhtrA$AsA & Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU Std.by to RX VDD VDD Std.by to TX PWR_UP PWR_UP TXEN TXEN DOUT DIN 3ms ms 0 2 4 1ms1ms ms 0 2 4 (a) (b) Figure 5 Timing diagram for NRF401 when going from standby to RX-mode (a) or TX-mode (b). 3RZHU XS WR WUDQVPLWPRGH VWDUWXS To avoid spurious emission outside the ISM-band when the power supply is switched on, the TXEN-input must be kept low until the synthesised frequency is stable, see Figure 6 (a). When enabling transmit-mode, TXEN-input should be high for at least 1 ms before data (DIN) is transmitted, see Figure 6 (a). VDD=0 to TX VDD VDD VDD=0 to RX PWR_UP PWR_UP TXEN TXEN DIN DOUT 3ms 1ms ms 5ms ms 0 2 4 6 0 2 4 (a) (b) Figure 6. Timing diagram for NRF401 when powering up to TX-mode (a) or RX-mode (b). 3RZHU XS WR UHFHLYH PRGH VWDUW XS In transition from power up to receive mode, the receiver may not receive data (DOUT) until VDD has been stable (VDD > 2.7 V) for at least 5ms, see Figure 6(b). If an external reference oscillator is used, the receiver may receive data (DOUT) after 3ms. Nordic VLSI ASA Revision: 1.6 Vestre Rosten 81, N-7075 Tiller, Norway QhtrA%AsA & Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU $33/,&$7,21 ,1)250$7,21 $QWHQQD LQSXWRXWSXW The ANT1 and ANT2 pins provide RF input to the LNA (Low Noise Amplifier) when NRF401 is in receive mode, and RF output from the PA (Power Amplifier) when NRF401 is in transmit mode. The antenna connection to NRF401 is differential and the recommended load impedance at the antenna port is 400. Figure 12 shows a typical application schematic with a differential loop antenna on a Printed Circuit Board (PCB). The output stage (PA) consists of two open collector transistors in a differential pair configuration. VDD to the PA must be supplied through the collector load. When connecting a differential loop antenna to the ANT1/ANT2 pins, VDD should be supplied through the centre of the loop antenna as shown in Figure 12. A 50 single ended antenna or 50 test instrument may be connected to NRF401 by using a differential to single ended matching network (BALUN) as shown in Figure 7. 8.2pF 22nH ANT1 220pF RF in/out 50 oh xxx NRF401 1.5pF 22nH VDD ANT2 22nH 8.2pF 220pF Figure 7. Connection of NRF401 to single ended antenna by using a differential to single ended matching network. The value of the capacitor connected between ANT1 and ANT2 is dependent on parasitics in the layout. 1.5 pF is the optimal value when using Nordic VLSI layout and 1.6 mm, 2 layer, FR4 printed circuit board, see application note AN400-05. The 22 nH inductor to VDD in Figure 7, need to have a Self-Resonance Frequency (SRF) above 868 MHz to be effective. Suitable inductors are listed in Table 6. 9HQGRUV Pulse Coilcraft muRata Stetco KOA ::: DGGUHVV http://www.pulseeng.com http://www.coilcraft.com http://www.murata.com http://www.stetco.com http://www.koaspeer.com 3DUW QR Q+ LQGXFWRUV VL]H PE-0603CD220GTT 0603CS-22NXGBC LQW1608A22NG00 0603G220GTE KQ0603TE22NG Table 6. Vendors and part. no. for suitable 22 nH inductors. Nordic VLSI ASA Revision: 1.6 Vestre Rosten 81, N-7075 Tiller, Norway QhtrA&AsA & Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU A single ended antenna may also be connected to NRF401 using an 8:1 impedance RF transformer. The RF transformer must have a centre tap at the primary side for VDD supply. 5) RXWSXW SRZHU The external bias resistor R3 connected between the RF_PWR pin and VSS in Figure 12 sets the output power. The RF output power may be set to levels up to +10dBm. In Figure 8 the output power is plotted for power levels down to, but not limited to, 8.5dBm for a differential load of 400. DC power supply current versus external bias resistor value is shown in Figure 9. ASAAPAQrA 10 8 6 4 d 7 q b A r Q 22 27 33 39 47 2 0 -2 -4 -6 56 68 82 100 120 150 -8 -10 0 20 40 60 80 100 120 140 160 180 180 200 SrvAWhyrAbx:d Figure 8. RF output power vs. external power setting resistor (R3) for NRF401. UhyA8uvA8rA 30,0 22 27 33 39 47 56 68 82 100 120 25,0 d 6 b A v 8 A r 8 20,0 15,0 10,0 150 180 5,0 0,0 0 20 40 60 80 100 120 140 160 180 200 SrvAWhyrAbx: d Figure 9. Total chip current consumption vs. external power setting resistor (R3) for NRF401. Nordic VLSI ASA Revision: 1.6 Vestre Rosten 81, N-7075 Tiller, Norway QhtrA'AsA & Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU 3// ORRS ILOWHU The synthesiser loop filter is an external, single-ended second order lag-lead filter. The recommended filter component values are: C3 = 820 pF, C4 =15 nF, and R2 = 4.7 k, see Figure 12. The loop filter voltage, measured at pin 4, should be 1.1 0.2 V. Measuring the specified loop filter voltage verifies that the VCO inductor value and placement are correct. This means optimal NRF401 performance. 9&2 LQGXFWRU An external 22nH inductor connected between the VCO1 and VCO2 pins is required for the on-chip voltage controlled oscillator (VCO). This inductor must be a high quality chip inductor, Q > 45 @ 433 MHz, with a maximum tolerance of 2%. The following 22 nH inductors (0603) are suitable for use with NRF401. 9HQGRUV Pulse Coilcraft muRata Stetco KOA ::: DGGUHVV http://www.pulseeng.com http://www.coilcraft.com http://www.murata.com http://www.stetco.com http://www.koaspeer.com 3DUW QR Q+ LQGXFWRUV VL]H PE-0603CD220GTT 0603CS-22NXGBC LQW1608A22NG00 0603G220GTE KQ0603TE22NG Table 7. Vendors and part no. for suitable 22nH inductors. The VCO inductor placement is important. The optimum placement of the VCO inductor gives a PLL loop filter voltage of 1.1 0.2 V, which can be measured at FILT1 (pin4). For a 0603 size inductor the length between the centre of the VCO1/VCO2 pad and the centre of the inductor pad should be 5.4 mm, see Figure 13 (c) (layout, top view), for a 2 layer, 1.6 mm thick FR4 PCB. &U\VWDO VSHFLILFDWLRQ To achieve an active crystal oscillator (XOSC) with low power consumption, certain requirements apply for crystal loss and capacitive load. The crystal specification is: I 0+] &R 7 S) (65 150 RKP . &/ 14 S) Crystal parallel resonant frequency Crystal parallel equivalent capacitance Crystal equivalent series resistance Total crystal load capacitance, including capacitance in PCB layout. For the crystal oscillator shown in Figure 10 the load capacitance is given by: &1 & 2 , &/ = &1 + & 2 Where C1 = C1 + CPCB1 and C2 = C2 + CPCB2 Nordic VLSI ASA Revision: 1.6 Vestre Rosten 81, N-7075 Tiller, Norway QhtrA(AsA & Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU C1 and C2 are 0603 SMD capacitors as shown in the application schematic, see Figure 12 and Table 9. CPCB1 and CPCB2 are the layout parasitic capacitance on the circuit board. Layout parasitics are significant when using SMD crystals on PCBs with ground planes. Changes in CL leads to changes in crystal frequency. Crystal oscillator Internal R External components ESR Cs L Crystal equivalent Co Crystal C1 C2 Figure 10. Crystal oscillator and crystal equivalent. 6KDULQJ D UHIHUHQFH FU\VWDO ZLWK D PLFURFRQWUROOHU Figure 11 shows circuit diagram of a typical application where NRF401 and a micro controller share the reference crystal. XC1 1.0M R micro controller X1 X2 NRF401 C XC2 5.6pF C1 22pF 4.0 MHz C2 22pF Figure 11. NRF401 and a micro-controller sharing the reference crystal. The crystal reference line from the micro-controller must be shielded from noise, e.g. not be routed close to full swing digital data or control signals. When sharing crystal, frequency (f) and frequency tolerance of the crystal is set by NRF401 specifications. CL, C0 and ESR are set by the microcontroller (MCU) specifications. The voltage amplitude at XC2 should be > 300 mVPP. Changing the value of C, see figure 11, changes the XC2 voltage amplitude. Nordic VLSI ASA Revision: 1.6 Vestre Rosten 81, N-7075 Tiller, Norway QhtrA AsA & Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU )UHTXHQF\ GLIIHUHQFH EHWZHHQ WUDQVPLWWHU DQG UHFHLYHU For optimum performance, the total frequency difference between transmitter and receiver should not exceed 70 ppm (30 kHz). This yields a crystal stability requirement of 35 ppm for the transmitter and receiver. Frequency difference exceeding this will result in a -12dB/octave drop in receiver sensitivity. The functional frequency window of the transmission link is typically 450 ppm (200 kHz). Example: A crystal with 20 ppm frequency tolerance and 25 ppm frequency stability over the operating temperature has a worst case frequency difference of 45 ppm. If the transmitter and receiver operate in different temperature environments, the resulting worst-case frequency difference may be as high as 90 ppm. Resulting drop in sensitivity due to the extra 20 ppm, is then approx. 5dB 7UDQVPLWUHFHLYH PRGH VHOHFWLRQ TXEN is a digital input for selection of transmit or receive mode. TXEN = "1" selects transmit mode. TXEN = "0" selects receive mode. &KDQQHO &KDQQHO VHOHFWLRQ CS is a digital input for selection of either channel#1 (f1=433.93MHz) or channel#2 (f2=434.33MHz). CS = "0" selects channel#1. CS = "1" selects channel#2. 3RZHU XS PWR_UP is a digital input for selection of normal operating mode or standby mode. PWR_UP = "1" selects normal operating mode. PWR_UP = "0" selects standby mode. TXEN 0 0 1 1 X Input CS 0 1 0 1 X PWR_UP 1 1 1 1 0 Response Channel # Mode 1 RX 2 RX 1 TX 2 TX -Standby Table 8. Required setting for standby and channel selection in RX and TX. ' GDWD LQSXW DQG ' GDWD RXWSXW The DIN pin is the input to the digital modulator of the transmitter. The input signal to this pin should be standard CMOS logic level at data rates up to 20 kbit/s. No coding of data is required. DIN = "1" f = f0 + f DIN = "0" f = f0 - f DI PVU Nordic VLSI ASA Revision: 1.6 Vestre Rosten 81, N-7075 Tiller, Norway QhtrA AsA & Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU The demodulated digital output data appear at the DOUT pin at standard CMOS logic levels. f0 + f DOUT="1", f0 - f DOUT="0". 3&% OD\RXW DQG GHFRXSOLQJ JXLGHOLQHV A well-designed PCB is necessary to achieve good RF performance. A PCB with a minimum of two layers including a ground plane is recommended for optimum performance. The NRF401 DC supply voltage should be decoupled as close as possible to the VDD pins with high performance RF capacitors, see Table 9. It is preferable to mount a large surface mount capacitor (e.g. 4.7 F tantalum) in parallel with the smaller value capacitors. The NRF401 supply voltage should be filtered and routed separately from the supply voltages of any digital circuitry (star routed). Long power supply lines on the PCB should be avoided. All device grounds, VDD connections and VDD bypass capacitors must be connected as close as possible to the NRF401 IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground plane, the best technique is to have via holes in or close to the VSS pads. Full swing digital data or control signals should not be routed close to the PLL loop filter components or the external VCO inductor. The VCO inductor placement is important. The optimum placement of the VCO inductor gives a PLL loop filter voltage of 1.1 0.2 V, which can be measured at FILT1 (pin4). For a 0603 size inductor the length between the centre of the VCO1/VCO2 pad and the centre of the inductor pad should be 5.4 mm, see Figure 13 (c) (layout, top view), for a 2 layer, 1.6 mm thick FR4 PCB. 3&% OD\RXW H[DPSOH Figure 13 shows a PCB layout example for the application schematic in Figure 12. A double-sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane on the bottom layer. Additionally, there are ground areas on the component side of the board to ensure sufficient grounding of critical components. A large number of via holes connect the top layer ground areas to the bottom layer ground plane. There must 127 be a ground plane shielding the radiation from the antenna. For more layout information, please refer to application note nAN400-05, "NRF401 RF and antenna layout". Nordic VLSI ASA Revision: 1.6 Vestre Rosten 81, N-7075 Tiller, Norway QhtrA !AsA & Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU $33/,&$7,21 6&+(0$7,& +3V R1 C5 4.7uF 3216 C1 22pF 0603 1M 0603 X1 4.000 MHz C2 22pF 0603 REFERENCE U1 1 2 3 4 5 6 7 8 9 10 XC1 VDD VSS FILT1 VCO1 VCO2 VSS VDD DIN DOUT XC2 TXEN PWR_UP VSS ANT1 ANT2 VSS VDD CS RF_PWR 20 19 18 17 16 15 14 13 12 11 TXEN PWR_UP C10 3.3pF 0603 C11 5.6pF 0603 C4 15nF 0603 C3 820pF 0603 L1 22nH 0603 R2 4.7K 0603 C6 100nF 0603 C7 1nF 0603 DIN DOUT R4 18K aaaaaaaa 0603 CS C9 220pF 0603 C8 220pF 0603 NRF401 433MHz Single Chip RF Transceiver SSOIC20 R3 22K 0603 PLL FILTER J1 Loop antenna 25x15mm Figure 12. NRF401 application schematic. &RPSRQHQW C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 L1 R1 R2 R3 R4 X1 'HVFULSWLRQ NP0 ceramic chip capacitor, (Crystal oscillator) NP0 ceramic chip capacitor, (Crystal oscillator) X7R ceramic chip capacitor, (PLL loop filter) X7R ceramic chip capacitor, (PLL loop filter) Tantalum chip capacitor, (Supply decoupling) X7R ceramic chip capacitor, (Supply decoupling) X7R ceramic chip capacitor, (Supply decoupling) NP0 ceramic chip capacitor, (Supply decoupling) NP0 ceramic chip capacitor, (Supply decoupling) NP0 ceramic chip capacitor, (Antenna tuning) NP0 ceramic chip capacitor, (Antenna tuning) VCO inductor, Q>45 @ 433 MHz 0.1W chip resistor, (Crystal oscillator) 0.1W chip resistor, (PLL loop filter) 0.1W chip resistor, (Transmitter power setting) 0.1W chip resistor, (Antenna Q reduction) Crystal 6L]H 0603 0603 0603 0603 3216 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 - 9DOXH 22 22 820 15 4.7 100 1 220 220 3.3 5.6 22 1.0 4.7 22 18 4.000 7ROHUDQFH 8QLWV pF pF pF nF F nF nF pF pF pF pF nH M k k k MHz 0.1 0.1 2% Table 9. Recommended External Components. Nordic VLSI ASA Revision: 1.6 Vestre Rosten 81, N-7075 Tiller, Norway QhtrA "AsA & Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU a) Top silk screen b) Bottom silk screen c) Top view d) Bottom view Figure 13. PCB layout (example) for NRF401 with loop antenna. Nordic VLSI ASA Revision: 1.6 Vestre Rosten 81, N-7075 Tiller, Norway QhtrA #AsA & Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU '(),1,7,216 'DWD VKHHW VWDWXV Objective product specification Preliminary product specification Product specification This datasheet contains target specifications for product development. This datasheet contains preliminary data; supplementary data may be published from Nordic VLSI ASA later. This datasheet contains final product specifications. Nordic VLSI ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. /LPLWLQJ YDOXHV Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. $SSOLFDWLRQ LQIRUPDWLRQ Where application information is given, it is advisory and does not form part of the specification. Table 10. Definitions Nordic VLSI ASA reserves the right to make changes without further notice to the product to improve reliability, function or design. Nordic VLSI does not assume any liability arising out of the application or use of any product or circuits described herein. /,)( 6833257 $33/,&$7,216 These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nordic VLSI ASA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nordic VLSI ASA for any damages resulting from such improper use or sale. Product specification: Revision Date: 28.02.2002. Datasheet order code: 280202NRF401 All rights reserved (R). Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. Nordic VLSI ASA Revision: 1.6 Vestre Rosten 81, N-7075 Tiller, Norway QhtrA $AsA & Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU <285 127(6 Nordic VLSI ASA Revision: 1.6 Vestre Rosten 81, N-7075 Tiller, Norway QhtrA %AsA & Phone +4772898900 - Fax +4772898989 February 2002 PRODUCT SPECIFICATION Q5) 6LQJOH &KLS 5) 7UDQVFHLYHU 1RUGLF 9/6, :RUOG :LGH 'LVWULEXWRUV )RU Revision: 1.6 QhtrA &AsA & February 2002 |
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