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E2E1036-18-95
Semiconductor MSM66573 Family
Semiconductor
im Version E2: Sep.Family ina MSM66573 1998
Pr
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ry
Oki's Original High-Performance, 16-Bit CMOS Single-Chip Microcontrollers Microcontrollers for Controlling Compact Devices
GENERAL DESCRIPTION
The MSM66573 family consists of high-performance, 16-bit CMOS single-chip microcontrollers based on Oki's own architecture. Internal peripherals include a selection of multifunction timers configurable for compare output, input capture, event counting, auto reloading, and PWM output for such uses as measuring frequencies and time intervals. In addition to the main clock, the family supports a low-speed (32.768 kHz) clock for use in applications requiring energy conservation modes. Interfaces to external devices include a high-speed bus interface using separate address and data buses to eliminate the need for an external address latch and a three-channel serial interface. The 16-bit core supports high-speed 16-bit arithmetic and a wide variety of bit manipulations, making the microcontrollers ideal for such system control applications as high-speed CD-ROM drives and other PC peripherals. The family includes the flash ROM version MSM66Q573, rewritable with a single power supply (VDD = 2.7 to 3.3/4.5 to 5.5 V) and thus rapidly adaptable for changing specifications and applying field upgrades.
APPLICATIONS
High-speed CD-ROM drives, PC peripherals, audiovisual equipment control sysems, office electronics control systems
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Semiconductor
MSM66573 Family
FEATURES
Family device Operating temperature Power supply voltage and maximum clock frequency Minimum instruction execution time Internal ROM (Maximum external ROM) Internal RAM (Maximum external RAM) I/O ports MSM66572 -30C to +70C VDD = 4.5 V to 5.5 V/f = 30 MHz VDD = 2.4 V to 3.6 V/f = 14 MHz 67 ns @30 MHz ( 4.5 to 5.5 V ) 143 ns @14 MHz ( 2.4 to 3.6 V ) 61 ms @32.768 kHz (2.4 to 3.6/4.5 to 5.5 V) 48K Byte ( 1M Byte ) 4K Byte ( 1M Byte ) 75 I/O pins (with programmable pull-up resistors) Eight pins are for inputs only. One 16-bit free-running counter Two compare output/capture input channels One 16-bit timer (auto reload/timer output) One 8-bit auto reload timer Three 8-bit auto reload timers Timers (These double as serial interface baud rate generators.) One watchdog timer (This doubles as an 8-bit auto reload timer.) One clock timer channel Four 8-bit PWM channels (These are configurable as two 16-bit PWM channels.) One UART channel Serial ports Analog-to-digital converter External interrupts Interrupt priorities Miscellaneous Flash ROM/One-time PROM versions One synchronous channel One channel switchable between UART and synchronous operation Eight 10-bit channels One non-maskable; six maskable Three levels Separate address and data busses Bus release function Dual clock operation MSM66Q573/MSM66P573 64K Byte MSM66573
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Semiconductor
MSM66573 Family
BLOCK DIAGRAM
TM0OUT TM0EVT CLKOUT XTOUT RXD0 TXD0 RXC0 TM3OUT TM3EVT RXD1 TXD1 RXC1 TXC1 TM4OUT SIOI3 SIOO3 SIOCK3 TM5EVT SIO3 (SYNC) SIO1 (UART/SYNC) 8bit Timer3/BRG ALU Control ACC SIO0 (UART) ALU Control Registers SSP LRB DSR TSR PSW PC CSR Peripheral System Control 16bit Timer0 CPU Core XT0 XT1 OSC0 OSC1 HOLD HLDACK RES
8bit Timer4/BRG
Memory Control Pointing Registers Local Registers
Instruction Decoder
8bit Timer5/BRG RAM 4K 8bit Timer6/WDT
Bus Port Control
EA ROM 48K/64K PSEN RD WR WAIT D0 to D7 A0 to A19 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12
PWMOUT0 PWMOUT2 PWMOUT1 PWMOUT3 TM9OUT TM9EVT CPCM0 CPCM1 CAP/CMP TBC 8bit Timer9 8bit PWM0 8bit PWM1
VREF AGND AI0 to AI7 NMI EXINT0 to EXINT5
RTC 10bit A/D Converter
Interrupt
Figure 1 MSM66573 Family Block Diagram
Port Control
16bit FRC
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Semiconductor
MSM66573 Family
PIN CONFIGURATION (TOP VIEW)
P10-3 SIOO3/P10-2 SIOI3/P10-1 SIOCK3/P10-0 TM3EVT/P7-5 TM3OUT/P7-4 RXC0/P7-2 GND TXD0/P7-1 RXD0/P7-0 AGND AI7/P12-7 AI6/P12-6 AI5/P12-5 AI4/P12-4 AI3/P12-3 AI2/P12-2 AI1/P12-1 AI0/P12-0 VREF VDD A19/P2-3 A18/P2-2 A17/P2-1 A16/P2-0 100 95 90 85 80 P10-4 P10-5 TM5EVT/P10-7 RXD1/P8-0 TXD1/P8-1 RXC1/P8-2 TXC1/P8-3 TM4OUT/P8-4 PWM2OUT/P8-6 PWM3OUT/P8-7 PWM0OUT/P7-6 PWM1OUT/P7-7 VDD GND HLDACK/P9-7 EXINT4/P9-0 EXINT5/P9-1 P9-2 P9-3 EXINT0/P6-0 EXINT1/P6-1 EXINT2/P6-2 EXINT3/P6-3 P6-4 P6-5 1 75
5 70
10 65
15 60
20 55
25 30 35 40 45 50
P1-7/A15 P1-6/A14 P1-5/A13 P1-4/A12 P1-3/A11 P1-2/A10 P1-1/A9 P1-0/A8 P4-7/A7 P4-6/A6 P4-5/A5 P4-4/A4 P4-3/A3 P4-2/A2 P4-1/A1 P4-0/A0 GND P0-7/D7 P0-6/D6 P0-5/D5 P0-4/D4 P0-3/D3 P0-2/D2 P0-1/D1 P0-0/D0
Figure 2 MSM66573 Family Pin Configuration (100-Pin Plastic TQFP)
P6-6 P6-7 P5-4/CPCM0 P5-5/CPCM1 P5-6/TM0OUT P5-7/TM0EVT RES NM1 EA VDD XT0 XT1 GND OSC0 OSC1 VDD P11-0/WAIT P11-1/HOLD P11-2/CLKOUT P11-3/XTOUT P11-6/TM9OUT P11-7/TM9EVT P3-1/PSEN P3-2/RD P3-3/WR
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Semiconductor
MSM66573 Family
PIN CONFIGURATION (TOP VIEW) (continued)
SIOCK3/P10-0 TM3EVT/P7-5 TM3OUT/P7-4 RXC0/P7-2 GND TXD0/P7-1 RXD0/P7-0 AGND AI7/P12-7 AI6/P12-6 AI5/P12-5 AI4/P12-4 AI3/P12-3 AI2/P12-2 AI1/P12-1 AI0/P12-0 VREF VDD A19/P2-3 A18/P2-2 100 95 90 85 1 80
SIOI3/P10-1 SIOO3/P10-2 P10-3 P10-4 P10-5 TM5EVT/P10-7 RXD1/P8-0 TXD1/P8-1 RXC1/P8-2 TXC1/P8-3 TM4OUT/P8-4 PWM2OUT/P8-6 PWM3OUT/P8-7 PWM0OUT/P7-6 PWM1OUT/P7-7 VDD GND HLDACK/P9-7 EXINT4/P9-0 EXINT5/P9-1 P9-2 P9-3 EXINT0/P6-0 EXINT1/P6-1 EXINT2/P6-2 EXINT3/P6-3 P6-4 P6-5 P6-6 P6-7
5 75
10 70
15 65
20 60
25 55
30 35 40 45 50
P2-1/A17 P2-0/A16 P1-7/A15 P1-6/A14 P1-5/A13 P1-4/A12 P1-3/A11 P1-2/A10 P1-1/A9 P1-0/A8 P4-7/A7 P4-6/A6 P4-5/A5 P4-4/A4 P4-3/A3 P4-2/A2 P4-1/A1 P4-0/A0 GND P0-7/D7 P0-6/D6 P0-5/D5 P0-4/D4 P0-3/D3 P0-2/D2 P0-1/D1 P0-0/D0 P3-3/WR P3-2/RD P3-1/PSEN
Figure 3 MSM66573 Family Pin Configuration (100-Pin Plastic QFP)
P5-4/CPCM0 P5-5/CPCM1 P5-6/TM0OUT P5-7/TM0EVT RES NM1 EA VDD XT0 XT1 GND OSC0 OSC1 VDD P11-0/WAIT P11-1/HOLD P11-2/CLKOUT P11-3/XTOUT P11-6/TM9OUT P11-7/TM9EVT
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Semiconductor
MSM66573 Family
PIN DESCRIPTIONS
Table 1 lists the function of each pin in the MSM66573 family. In the Type column, "I" indicates an input pin, "O" indicates an output pin, and "I/O" indicates an I/O pin. Table 1 Pin Descriptions
Function
Classification
Symbol Type Primary function 8-bit I/O port LED direct drive port Pull-up resistors can be specified for each individual bit P1_0/A8 to P1_7/A15 P2_0/A16 to P2_3/A19 P3_1/PSEN P3_2/RD P3_3/WR P4_0/A0 to P4_7/A7 P5_4/CPCM0 P5_5/CPCM1 P5_6/TM0OUT P5_7/TM0EVT P6_0/EXINT0 P6_1/EXINT1 P6_2/EXINT2 P6_3/EXINT3 P6_4 to P6_7 I/O 8-bit I/O port Pull-up resistors can be specified for each individual bit I/O I/O 8-bit I/O port Pull-up resistors can be specified for each individual bit 4-bit I/O port Pull-up resistors can be specified for each individual bit I/O O I I I I I -- I/O Capture 0 input/ Compare 0 output pin Capture 1 input/ Compare 1 output pin Timer 0 timer output pin Timer 0 external event input pin External interrupt 0 input pin External interrupt 1 input pin External interrupt 2 input pin External interrupt 3 input pin None I/O I/O I/O 8-bit I/O port Pull-up resistors can be specified for each individual bit 4-bit I/O port Pull-up resistors can be specified for each individual bit 3-bit I/O port LED direct drive port Pull-up resistors can be specified for each individual bit O O O O External program memory access Read strobe output pin External memory access Read strobe output pin External memory access Write strobe output pin External memory access Address output port O External memory access Address output port O External memory access Address output port Type I/O Secondary function External memory access Data I/O port P0_0/D0 to P0_7/D7 I/O
Port
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Semiconductor Table 1 Pin Descriptions (continued)
Function
Classification
MSM66573 Family
Symbol Type Primary function 7-bit I/O port Pull-up resistors can be specified for each individual bit Type I O I O I O O I/O 7-bit I/O port Pull-up resistors can be specified for each individual bit I O I/O I/O O O O I/O 5-bit I/O port Pull-up resistors can be specified for each individual bit I/O 7-bit I/O port Pull-up resistors can be specified for each individual bit I I O I/O I O I I/O 6-bit I/O port LED direct drive port P11_1/HOLD P11_2/CLKOUT P11_3/XTOUT P11_6/TM9OUT P11_7/TM9EVT P12_0/AI0 to P12_7/AI7 I 8-bit input port Pull-up resistors can be specified for each individual bit I O O O I I I Secondary function SIO0 receive data input pin SIO0 transmit data output pin SIO0 external clock input pin Timer 3 timer output pin Timer 3 external event input pin PWM0 output pin PWM1 output pin SIO1 receive data input pin SIO1 transmit data output pin SIO1 receive clock I/O pin SIO1 transmit clock I/O pin Timer 4 timer output pin PWM2 output pin PWM3 output pin External interrupt 4 input pin External interrupt 5 input pin HOLD mode output pin SIO3 transmit-receive clock I/O pin SIO3 receive data input pin SIO3 transmit data output pin Timer 5 external event input pin External data memory access wait input pin HOLD mode request input pin Main clock pulse output pin Sub clock pulse output pin Timer 9 timer output pin Timer 9 external event input pin A/D converter analog input port P7_0/RXD0 P7_1/TXD0 P7_2/RXC0 P7_4/TM3OUT P7_5/TM3EVT P7_6/PWM0OUT P7_7/PWM1OUT P8_0/RXD1 P8_1/TXD1 P8_2/RXC1 P8_3/TXC1 P8_4/TM4OUT P8_6/PWM2OUT P8_7/PWM3OUT P9_0/EXINT4 P9_1/EXINT5 P9_2, P9_3 P9_7/HLDACK P10_0/SIOCK3 P10_1/SIOI3 P10_2/SIOO3 P10_3 to P10_5 P10_7/TM5EVT P11_0/WAIT I/O
Port
--- None
--- None
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Semiconductor Table 1 Pin Descriptions (continued)
Classification
MSM66573 Family
Symbol VDD GND VREF AGND
Type I I I I I O Power supply pin
Function Connect all VDD pins to the power supply. GND pin Connect all GND pins to GND. Analog reference voltage pin Analog GND pin Sub clock oscillation input pin Connect to a crystal oscillator of f = 32.768 kHz. Sub clock oscillation output pin Connect to a crystal oscillator of f = 32.768 kHz. The clock output is opposite in phase to XT0.
Power supply
Oscillation
XT0 XT1
OSC0 OSC1
I O
Main clock oscillation input pin Connect to a crystal or ceramic oscillator. Or, input an external clock. Main clock oscillation output pin Connect to a crystal or ceramic oscillator. The clock output is opposite in phase to OSC0. Leave this pin unconnected when an external clock is used.
Reset Other
RES NMI EA
I I I
Reset input pin Non-maskable interrupt input pin External program memory access input pin If the EA pin goes to a low level, all program addresses of external program memory are accessed.
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Semiconductor
MSM66573 Family
ABSOLUTE MAXIMUM RATINGS
Parameter Digital power supply voltage Input voltage Output voltage Analog reference voltage Analog input voltage Power Dissipation Storage temperature Symbol VDD VI VO VREF VAI PD TSTG Ta = 70C 1 per package 1 per output -- GND = AGND = 0 V Ta = 25C Condition Rating -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to VREF 650 8 -50 to +150 Unit V V V V V mW mW C
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol MSM66572 MSM66573 Digital power supply voltage VDD MSM66Q573 MSM66P573 Analog reference voltage Analog input voltage Memory hold voltage VREF VAI VDDH MSM66572 MSM66573 Operating frequency fOSC MSM66Q573 MSM66P573 Ambient temperature Ta Condition fOSC 30 MHz fOSC 14 MHz fOSC 30 MHz fOSC 14 MHz fOSC 24 MHz fOSC 12 MHz -- -- fOSC = 0 Hz VDD = 4.5 to 5.5 V VDD = 2.4 to 3.6 V VDD = 4.5 to 5.5 V VDD = 2.7 to 3.3 V VDD = 4.5 to 5.5 V VDD = 2.7 to 3.6 V -- MOS load Fan out N TTL load P0, P3, P11 P1, P2, P4, P5 P6, P7, P8, P9, P10 Range 4.5 to 5.5 2.4 to 3.6 *1 4.5 to 5.5 2.7 to 3.3 4.5 to 5.5 2.7 to 3.6 *1 VDD - 0.3 to VDD AGND to VREF 2.0 to 5.5 2 to 30 2 to 14 2 to 30 2 to 14 2 to 24 2 to 12 -30 to +70 20 6 1 C -- -- -- MHz V V V V Unit
*1 In this data sheet, electrical characteristics are shown up to 3.3 V for low-voltage operation. Please contact Oki sales office to refer to the 3.6 V operation electrical characteristics.
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Semiconductor
MSM66573 Family
ALLOWABLE OUTPUT CURRENT VALUES
Parameter "H" output pin (1 pin) "H" output pins (sum total) "L" output pin (1 pin) Pin All output pins Sum total of all output pins P0, P3, P11 Other ports Sum total of P0, P3, P11 Sum total of "L" output pins (sum total) P1, P2, P4 Sum total of P5, P6, P9 Sum total of P7, P8, P10 Sum total of all output pins 140 S IOL -- -- 50 Symbol IOH S IOH IOL Min. -- -- -- Typ. -- -- -- Max. -2 -40 10 5 80 mA Unit
Note:
Connect the power supply voltage to all VDD pins and the ground voltage to all GND pins.
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Semiconductor
MSM66573 Family
ELECTRICAL CHARACTERISTICS
DC Characteristics (VDD = 4.5 to 5.5 V)
Parameter "H" input voltage "H" input voltage *2, *3, *4, *5, *6, *7 "L" input voltage "L" input voltage *2, *3, *4, *5, *6, *7 "H" output voltage "H" output voltage "L" output voltage "L" output voltage Input leakage current Input current Input current *1, *4 VOH *2 *1, *4 VOL *2 *3, *6 *5 *7 ILO Rpull CI CO IREF IDDS IDDH VO = VDD/0 V VI = 0 V f = 1 MHz, Ta = 25C During A/D operation When A/D is stopped VDD = 2 V, Ta = 25C* *8 fOSC = 30 MHz, No Load During XTCLK (32.768 kHz) operation IIH/IIL VI = VDD/0 V IO = -400 mA IO = -2.0 mA IO = -200 mA IO = -2.0 mA IO = 3.2 mA IO = 10.0 mA IO = 1.6 mA IO = 5.0 mA *1 VIL -- *1 VIH -- Symbol Condition Min. 0.44VDD 0.80VDD -0.3 -0.3 VDD - 0.4 VDD - 0.6 VDD - 0.4 VDD - 0.6 -- -- -- -- -- -- -- -- 25 -- -- -- -- -- -- -- -- -- (VDD = 4.5 to 5.5 V, Ta = -30 to +70C) Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 5 7 -- -- 0.2 1 -- -- -- Max. VDD + 0.3 VDD + 0.3 0.16VDD 0.2VDD -- -- -- -- 0.4 0.8 0.4 0.8 1/-1 1/-250 15/-15 10 100 -- -- 4 10 10 100 TBD TBD TBD mA mA kW pF mA mA mA mA V Unit
Output leakage current *1, *2, *4 Pull-up resistance Input capacitance Output capacitance Analog reference supply current Supply current (during STOP mode) Supply current (during HALT mode) Supply current
IDD
*1. Applicable to P0 *2. Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10 *3. Applicable to P12 *4. Applicable to P3, P11 *5. Applicable to RES
*6. Applicable to EA, NMI *7. Applicable to OSC0 *8. Ports used as inputs are at VDD or 0 V Other ports are unloaded
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Semiconductor DC Characteristics (VDD = 2.4 to 3.3 V)
MSM66573 Family
MSM66572/573 (VDD = 2.4 to 3.3 V, Ta = -30 to +70C) MSM66P573/Q573 (VDD = 2.7 to 3.3 V, Ta = -30 to +70C) Parameter "H" input voltage "H" input voltage *2, *3, *4, *5, *6, *7 "L" input voltage "L" input voltage *2, *3, *4, *5, *6, *7 "H" output voltage "H" output voltage "L" output voltage "L" output voltage Input leakage current Input current Input current *1, *4 VOH *2 *1, *4 VOL *2 *3, *6 *5 *7 ILO Rpull CI CO IREF IDDS IDDH VO = VDD/0 V VI = 0 V f = 1 MHz, Ta = 25C During A/D operation When A/D is stopped VDD = 2 V, Ta = 25C* *8 fOSC = 14 MHz, No Load During XTCLK (32.768 kHz) operation IIH/IIL VI = VDD/0 V IO = -400 mA IO = -2.0 mA IO = -200 mA IO = -1.0 mA IO = 3.2 mA IO = 5.0 mA IO = 1.6 mA IO = 2.5 mA *1 VIL -- *1 VIH -- Symbol Condition Min. 0.44VDD 0.80VDD -0.3 -0.3 VDD - 0.4 VDD - 0.8 VDD - 0.4 VDD - 0.8 -- -- -- -- -- -- -- -- 40 -- -- -- -- -- -- -- -- Supply current IDD -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 5 7 -- -- 0.2 1 -- -- -- Max. VDD + 0.3 VDD + 0.3 0.16VDD 0.2VDD -- -- -- -- 0.5 0.9 0.5 0.9 1/-1 1/-250 15/-15 10 200 -- -- 2 5 10 100 TBD TBD TBD mA mA kW pF mA mA mA mA V Unit
Output leakage current *1, *2, *4 Pull-up resistance Input capacitance Output capacitance Analog reference supply current Supply current (during STOP mode) Supply current (during HALT mode)
*1. Applicable to P0 *2. Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10 *3. Applicable to P12 *4. Applicable to P3, P11 *5. Applicable to RES
*6. Applicable to EA, NMI *7. Applicable to OSC0 *8. Ports used as inputs are at VDD or 0 V Other ports are unloaded
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Semiconductor AC Characteristics (VDD = 4.5 to 5.5 V) [1] External program memory control
MSM66573 Family
(VDD = 4.5 to 5.5 V, Ta = -30 to +70C) Parameter Cycle time Clock pulse width (HIGH level) Clock pulse width (LOW level) PSEN pulse width PSEN pulse delay time Address setup time Address hold time Instruction setup time Instruction hold time Read data access time Symbol tcyc tfWH tfWL tPW tPD tAS tAH tIS tIH tACC CL = 50 pF Condition fOSC = 30 MHz Min. 33.3 13 13 2 tf - 15 -- tf - 25 0 30 0 -- Max. -- -- -- -- 45 -- 9 -- -- 3 tf - 70*1 Note: tf = tcyc/2 ns Unit
tcyc
CPUCLK
tfWH
PSEN
tfWL
tPD
A0 to A19 PC0 to 19
tPW
tAS
D0 to D7 INST0 to 7
tAH
tACC
tIS
tIH
Bus timing during no wait cycle time *1: The read data access time (tACC) is (3 + 2n) tf - 70 when n wait cycles are inserted.
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Semiconductor [2] External data memory control
Parameter Cycle time Clock pulse width (HIGH level) Clock pulse width (LOW level) RD pulse width WR pulse width RD pulse delay time WR pulse delay time Address setup time Address hold time Read data setup time Read data hold time Read data access time Write data setup time Write data hold time Symbol tcyc tfWH tfWL tRW tWW tRD tWD tAS tAH tRS tRH tACC tWS tWH CL = 50 pF Condition fOSC = 30 MHz
MSM66573 Family
(VDD = 4.5 to 5.5 V, Ta = -30 to +70C) Min. 33.3 13 13 2 tf - 15 2 tf -15 -- -- tf - 25 tf - 3 30 0 -- 2 tf - 30 tf - 3 Max. -- -- -- -- -- 45 45 -- tf + 3 -- -- 3 tf - 70*1 -- tf + 3 Note: tf = tcyc/2 ns Unit
tcyc
CPUCLK
tfWH
RD
tfWL
tRD
A0 to A19
tRW
RAP0 to 19
tAS
D0 to D7 DIN0 to 7
tAH
tACC
WR
tRS
tRH
tWD
A0 to A19
tWW
RAP0 to 19
tAS
D0 to D7 DOUT0 to 7
tAH
tWS
tWH
Bus timing during no wait cycle time 14/24
Semiconductor [3] Serial port control Master mode
MSM66573 Family
(VDD = 4.5 to 5.5 V, Ta = -30 to +70C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 30 MHz Min. 33.3 4 tcyc 2 tf - 5 5 tf - 10 13 0 Max. -- -- -- -- -- -- Note: tf = tcyc/2 ns Unit
tcyc
CPUCLK
TXC/ RXC
tSCKC
SDOUT (TXD)
tSTMXH
SDIN (RXD)
tSTMXS
tSRMXS tSRMXH
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Semiconductor Slave mode
MSM66573 Family
(VDD = 4.5 to 5.5 V, Ta = -30 to +70C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 30 MHz Min. 33.3 4 tcyc 2 tf - 15 4 tf - 10 13 3 Max. -- -- -- -- -- -- Note: tf = tcyc/2 ns Unit
tcyc
CPUCLK
TXC/ RXC
tSCKC
SDOUT (TXD)
tSTMXH
SDIN (RXD)
tSTMXS
tSRMXS tSRMXH
Measurement points for AC timing (except the serial port)
VDD 2.0 V 0.8 V 2.0 V 0.8 V
0V
Measurement points for AC timing (the serial port)
VDD
0.8VDD 0.2VDD
0.8VDD 0.2VDD
0V
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Semiconductor AC Characteristics (VDD = 2.4 to 3.3 V) [1] External program memory control
MSM66573 Family
MSM66572/573 (VDD = 2.4 to 3.3 V, Ta = -30 to +70C) MSM66P573/Q573 (VDD = 2.7 to 3.3 V, Ta = -30 to +70C) Parameter Cycle time Clock pulse width (HIGH level) Clock pulse width (LOW level) PSEN pulse width PSEN pulse delay time Address setup time Address hold time Instruction setup time Instruction hold time Read data access time Symbol tcyc tfWH tfWL tPW tPD tAS tAH tIS tIH tACC CL = 50 pF Condition fOSC = 14 MHz Min. 71.4 28 28 2 tf - 20 -- tf - 40 0 60 0 -- Max. -- -- -- -- 75 -- 18 -- -- 3 tf - 120*2 Note: tf = tcyc/2 ns Unit
tcyc
CPUCLK
tfWH
PSEN
tfWL
tPD
A0 to A19 PC0 to 19
tPW
tAS
D0 to D7 INST0 to 7
tAH
tACC
tIS
tIH
Bus timing during no wait cycle time *2: The read data access time (tACC) is (3 + 2n) tf - 120 when n wait cycles are inserted.
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Semiconductor [2] External data memory control
MSM66573 Family
MSM66572/573 (VDD = 2.4 to 3.3 V, Ta = -30 to +70C) MSM66P573/Q573 (VDD = 2.7 to 3.3 V, Ta = -30 to +70C) Parameter Cycle time Clock pulse width (HIGH level) Clock pulse width (LOW level) RD pulse width WR pulse width RD pulse delay time WR pulse delay time Address setup time Address hold time Read data setup time Read data hold time Read data access time Write data setup time Write data hold time Symbol tcyc tfWH tfWL tRW tWW tRD tWD tAS tAH tRS tRH tACC tWS tWH CL = 50 pF Condition fOSC = 14 MHz Min. 71.4 28 28 2 tf - 20 2 tf - 20 -- -- tf - 40 tf - 6 60 0 -- 2 tf - 40 tf - 6 Max. -- -- -- -- -- 75 75 -- tf + 6 -- -- 3 tf - 120*2 -- tf + 6 Note: tf = tcyc/2 ns Unit
tcyc
CPUCLK
tfWH
RD
tfWL
tRD
A0 to A19
tRW
RAP0 to 19
tAS
D0 to D7 DIN0 to 7
tAH
tACC
WR
tRS
tRH
tWD
A0 to A19
tWW
RAP0 to 19
tAS
D0 to D7 DOUT0 to 7
tAH
tWS
tWH
Bus timing during no wait cycle time 18/24
Semiconductor [3] Serial port control Master mode
MSM66573 Family
MSM66572/573 (VDD = 2.4 to 3.3 V, Ta = -30 to +70C) MSM66P573/Q573 (VDD = 2.7 to 3.3 V, Ta = -30 to +70C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 14 MHz Min. 71.4 4 tcyc 2 tf - 10 5 tf - 20 21 0 Max. -- -- -- -- -- -- Note: tf = tcyc/2 ns Unit
tcyc
CPUCLK
TXC/ RXC
tSCKC
SDOUT (TXD)
tSTMXH
SDIN (RXD)
tSTMXS
tSRMXS tSRMXH
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Semiconductor Slave mode
MSM66573 Family
MSM66572/573 (VDD = 2.4 to 3.3 V, Ta = -30 to +70C) MSM66P573/Q573 (VDD = 2.7 to 3.3 V, Ta = -30 to +70C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 14 MHz Min. 71.4 4 tcyc 2 tf - 30 4 tf - 20 21 7 Max. -- -- -- -- -- -- Note: tf = tcyc/2 ns Unit
tcyc
CPUCLK
TXC/ RXC
tSCKC
SDOUT (TXD)
tSTMXH
SDIN (RXD)
tSTMXS
tSRMXS tSRMXH
Measurement points for AC timing (except the serial port)
VDD 2.0 V 0.8 V 2.0 V 0.8 V
0V
Measurement points for AC timing (the serial port)
VDD
0.8VDD 0.2VDD
0.8VDD 0.2VDD
0V
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Semiconductor A/D Converter Characteristics (VDD = 4.5 to 5.5 V)
MSM66573 Family
(Ta = -30 to +70C, VDD = VREF = 4.5 V to 5.5 V, AGND = GND = 0 V) Parameter Resolution Linearity error Differential linearity error Zero scale error Full-scale error Cross talk Conversion time Symbol n EL ED EZS EFS ECT tCONV Condition
Refer to measurement circuit of Fig.4 Analog input source impedance Ri 5 kW tconv = 10.7 ms Refer to measurement circuit of Fig.5 Set according to ADTM set data
Min. -- -- -- -- -- -- 10.7
Typ. 10 -- -- -- -- -- --
Max. -- 3 2 +3 -3 1 --
Unit Bit
LSB
ms/ch
A/D Converter Characteristics (VDD = 2.4 to 3.3 V)
(Ta = -30 to +70C, VDD = VREF = 2.4 to 3.3 V, AGND = GND = 0 V) Parameter Resolution Linearity error Differential linearity error Zero scale error Full-scale error Cross talk Conversion time Symbol n EL ED EZS EFS ECT tCONV Condition
Refer to measurement circuit of Fig.4 Analog input source impedance Ri 5 kW tconv = 13.7 ms Refer to measurement circuit of Fig.5 Set according to ADTM set data
Min. -- -- -- -- -- -- 27.4
Typ. 10 -- -- -- -- -- --
Max. -- 3 2 +3 -3 1 --
Unit Bit
LSB
ms/ch
For the MSM66P573, the A/D conversion time should be 32 ms or more.
Reference voltage 0.1 mF - + Analog input RI 47 mF +
VREF
VDD + 0.1 mF 47 mF
+5 V
AI0 to AI7 AGND CI GND 0V
RI (impedance of analog input source) 5 kW CI = 0.1 mF
Figure 4 Measurement Circuit 21/24
Semiconductor
MSM66573 Family
- + Analog input
5 kW AI0 AI1 0.1 mF to AI7
Cross talk is the difference between the A/D conversion results when the same analog input is applied to AI0 through AI7 and the A/D conversion results of the circuit to the left.
VREF or AGND
Figure 5 Cross Talk Measurement Circuit Definition of Terminology 1. Resolution Resolution is the value of minimum discernable analog input. With 10 bits, since 210 = 1024, resolution of (VREF - AGND) / 1024 is possible. Linearity error Linearity error is the difference between ideal conversion characteristics and actual conversion characteristics of a 10-bit A/D converter (not including quantization error). Ideal conversion characteristics can be obtained by dividing the voltage between VREF and AGND into 1024 equal steps. Differential linearity error Differential linearity error indicates the smoothness of conversion characteristics. Ideally, the range of analog input voltage that corresponds to 1converted bit of digital output is 1LSB = (VREF - AGND) / 1024. Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion range. Zero scale error Zero scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 000H to 001H. Full-scale error Full-scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 3FEH to 3FFH.
2.
3.
4.
5.
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Semiconductor
MSM66573 Family
PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.55 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSM66573 Family
(Unit : mm)
QFP100-P-1420-0.65-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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