 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Features * * * * * * * * * * * * * * * * Full Range of Matrices up to 700K Cells 0.5 m Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimized for Synthesis, Floor Plan and Automatic Test Generation (ATG) 3 and 5 Volts Operation: Single or Dual Supply Mode High Speed Performances: - 510 ps max. NAND2 Propagation Delay at 5V and FO = 1/4 FO max. - min. 760 MHz Toggle Frequency at 4.5V, 410 MHz at 2.7V Programmable PLL Available on Request High System Frequency Skew Control: - 220 MHz max. PLL for Clock Generation at 4.5V - Clock Tree Synthesis Software Low Power Consumption: - 2 W/Gate/MHz at 5V - 0.6 W/Gate/MHz at 3V Matrices with a Max of 582 Fully Programmable Pads Standard 3, 6, 12 and 24 mA I/Os Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator CMOS/TTL/PCI Interface ESD (2 kV) and Latch-up Protected I/O Wide Selection of MQFPs and CLGA Packages Up To 564 Pins High Noise and EMC Immunity: - I/O with Slew Rate Control - Internal Decoupling - Signal Filtering between Periphery and Core - Application Dependent Supply Routing and Several Independant Supply Sources Delivery in Die Form with 94.6 m Pad Pitch Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management Cadence(R), Mentor(R), Vital(R) and Synopsys(R) Reference Platforms EDIF and VHDL Reference Formats Available in Military and Space Quality Grades (SCC, MIL-PRF-38535) Latch-up Immune QML Q and V with SMD 5962-00B02 Rad Tolerant 500K Used Gates 0.5 m CMOS Sea of Gates MG2RT * * * * * * * Description The MG2RT series is a 0.5 micron, array based, CMOS product family. Several arrays up to 700K cells cover all system integration needs. The MG2RT is manufactured using a 0.5 micron drawn, 3 metal layer CMOS process. The base cell architecture of the MG2RT series provides high routability of logic with extremely dense compiled memories: RAM and DPRAM. ROM can be generated using synthesis tools. For instance, the largest array is capable of integrating 128K bits and DPRAM with 128K bits of ROM and over 300,000 random gates. Accurate control of clock distribution can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques are applied in the array and in the periphery: Three or more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level. The MG2RT is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Cadence, Mentor, Synopsys andVHDL are the reference front-end tools. Floor planning associated with timing-driven layout provides a short back-end cycle. Rev. 4115G-AERO-03/02 1 The MG2RT library allows straight forward migration from the MG1RT and MG1 Sea of Gates. A netlist based on this library can be simulated as either MG2RT or MG2RTP: for MG2, it must not use SEU-free cells. Table 1. List of Available MG2RT Matrix Type MG2044E MG2091E MG2140E MG2194E MG2265E MG2360E MG2480E MG2700E (1) Total Cells 44616 91464 140322 193800 264375 361680 481143 698523 Usable Gates 33000 68000 105000 145000 198000 271000 360000 524000 Maximum I/O 150 214 264 310 362 422 484 584 Total Pads 173 237 287 333 385 445 507 607 Note: 1. Check for availability. Libraries The MG2RT cell library has been designed to take full advantage of the features offered by both logic and test synthesis tools. Design testability is assured by the full support of SCAN, JTAG (IEEE 1149) and BIST methodologies. More complex macro functions are available in VHDL, such as: Two-wire Interface (TWI), UART, Timer. Block Generators Block generators are used to create a customer specific simulation model and metallisation pattern for regular functions like RAM, DPRAM, and FIFO. The basic cell architecture allows one bit per cell for RAM and DPRAM. The main characteristics of these generators are summarised below. Typical Characteristics (16 Kbits) at 5V Function RAM DPRAM Maximum Size (bits) 36K 36K Bits/Word 1-36 1-36 Access Time (ns) 8 8.6 Used Cells 20K 23K 2 MG2RT 4115G-AERO-03/02 MG2RT I/O Buffer Interfacing I/O Flexibility Inputs All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A level translator is located close to each buffer. Input buffers with CMOS or TTL thresholds are non-inverting and feature versions with and without hysteresis. The CMOS and TTL input buffers may incorporate pull-up or pull down terminators. For special purposes, a buffer allowing direct input to the matrix core is available. Several kinds of CMOS and TTL output drivers are offered: fast buffers with 3, 6, 12 and 24 mA drive at 5V, low noise buffers with 12 mA drive at 5V. Outputs Clock Generation and PLL Clock Generation Atmel offers 7 different types of oscillators: 5 high frequency crystal oscillator and 2 RC oscillators. For all devices, the mark-space ratio is better than 40/60 and the start-up time less than 10 ms. Frequency (MHz) Oscillators Xtal 7M Xtal 20M Xtal 50M Xtal 100M Xtal 32K RC 10M RC 32M Max 5V 12 28 70 130 Max 3V 7 17 40 75 32 10 32 Typical 5V 1.2 2.5 7 16 3 2 3 Consumption (mA) 3V 0.4 0.8 2 5 4 1 1.5 PLL (On Request) Check for availability. 3 4115G-AERO-03/02 Power Supply and Noise Protection The speed and density of the SCMOS3/2RT technology causes large switching current spikes for example when: * * either 16 high current output buffers switch simultaneously, or 10% of the 700 000 gates are switching within a window of 1 ns. Sharp edges and high currents cause some parisitic elements in the packaging to become significant. In this frequency range, the package inductance and series resistance should be taken into account. It is known that an inductor slows down the settling time of the current and causes voltage drops on the power supply lines. These drops can affect the behavior of the circuit itself or disturb the external application (ground bounce). In order to improve the noise immunity of the MG core matrix, several mechanisms have been implemented inside the MG arrays. Two kinds of protection have been added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers against the switching noise coming from the matrix. I/O Buffers Switching Protection Three features are implemented to limit the noise generated by the switching current: * * * The power supplies of the input and output buffers are separated. The rise and fall times of the output buffers can be controlled by an internal regulator. A design rule concerning the number of buffers connected on the same power supply line has been imposed. Matrix Switching Current Protection This noise disturbance is caused by a large number of gates switching simultaneously. To allow this without impacting the functionality of the circuit, three new features have been added: * * Decoupling capacitors are integrated directly on the silicon to reduce the power supply drop. A power supply network has been implemented in the matrix. This solution reduces the number of parasitic elements such as inductance and resistance and constitutes an artificial VDD and Ground plane. One mesh of the network supplies approximately 150 cells. A low pass filter has been added between the matrix and the input to the output buffer. This limits the transmission of the noise coming from the ground or the VDD supply of the matrix to the external world via the output buffers. * Power Consumption The power consumption of an MG2RT array is due to three factors: leakage (P1), core (P2) and I/O (P3) consumption. P = P1 + P2 + P3 Leakage (Standby) Power Consumption The consumption due to leakage currents is defined as: P1 = (VDD - VSS) * ICCSB * NCELL Where ICCSB is the leakage current through a polarized basic gate and NCELL is the number of used cells. 4 MG2RT 4115G-AERO-03/02 MG2RT Core Power Consumption The power consumption due to the switching of cells in the core of the matrix is defined as: P2 = N CELL * PGATE * C ACTIVITY * F Where NCELL is the number of used cells, F the data toggling frequency, which is equal to half the clock frequency for random data and P GATE is the power consumption per cell. PGATE = PCA + P CO C ACTIVITY is the fraction of the total number of cells toggling per cycle. PCA = C * (VDD - VSS)2/2 Capacitance Power C is the total output capacitance and may be expressed as the sum of the drain capacitance of the driver, the wiring capacitance and the gate capacitance of the inputs. Worst case value: PCA # 1.8 W/gate/MHz at 5V Commutation Power PCO = (VDD - VSS) * Idsohm Where Idsohm is the current flowing into the driver between supply and ground during the commutation. Idsohm is about 15% of the Pmos saturation current. Worst case value: Pco # 0.7 W/gate/MHz at 5V I/O Power Consumption The power consumption due to the I/Os is: P3 = Ni * C O * (VDD - VSS) 2 * Fi/2 With Ni equals to the number of buffers running at Fi and CO is the output capacitance. Note: If a signal is a clock, Fi = F, if it is a data with random values, Fi = F/4. 5 4115G-AERO-03/02 Table 2. Typical Power Consumption Example Matrix Used gates (70%) Frequency Standby Power Iccsb (125C) P1 = (VDD - VSS) * ICCSB * NCELL Core Power Power Consumption per Cell Cactivity P2 = NCELL * PGATE * Cactivity * F I/O Power Total Number of Buffers Number of Outputs and I/O Buffers (NI) Output Capacitance P3 = Ni * CO * (VDD - VSS) * Fi/2 Total Power P = P1 + P2 + P3 2.59W 0.81W 2 MG2700E at 5V 490K 10 MHz MG2700E at 3V 490K 10 MHz 1 nA 2.5 mW 1 nA 1.5 mW 2.7 W/Gate/MHz 20% 1960 mW 0.58 W/Gate/MHz 20% 570 mW 582 100 50 pF 625 mW 582 100 50 pF 220 mW 6 MG2RT 4115G-AERO-03/02 MG2RT Packaging Atmel offers a wide range of packaging options which are listed below: Pins(2) Packaging Package Type MLCC min/max 68 84 100 352 349 564 Lead Spacing (mils) 50 50 25.6 20 50 40 CERAMIC MQFP CLGA(1) Note: For plastic, call factory; this is a customer decision to use plastic packages in environmental conditions which are beyond those for which they have been developed. 1. Ceramic Land Grid Array: contact factory. 2. Contact Atmel local design centers to check the availability of the used matrix and the package. 7 4115G-AERO-03/02 Design Flows and Tools Design Flows and Modes A generic design flow for an MG2RT array is illustrated below. A top down design methodology is proposed which starts with high level system description and is refined in successive design steps. At each step, structural verification is performed which includes the following tasks: * * * * * * * * * * * Gate level logic simulation and comparison with high level simulation results. Design and test rule check. Power consumption analysis. Timing analysis (only after floor plan). System specification, preferably in VHDL form. Functional description at RTL level. Logic synthesis. Floor planning and bonding diagram generation. Test/Scan insertion, ATG and/or fault simulation. Physical cell placement, JTAG insertion and clock tree synthesis. Routing. The main design stages are: To meet the various requirements of designers, several interface levels between the customer and Atmel are possible. For each of the possible design modes a review meeting is required for data transfer from the user to Atmel. In all cases the final routing and verifications are performed by Atmel. The design acceptance is formalized by a design review which authorizes Atmel to proceed with sample manufacturing. 8 MG2RT 4115G-AERO-03/02 MG2RT Figure 1. MG2RT Design Flow System Specifications RTL Simulation Logic synthesis Floor Plan Bonding diagram Scan insertion ATG and Fault Simulation Placement JTAG insertion Clock Tree Synthesis Routing Backannotated Simulation Sign-off Samples Manufacturing and Test 9 4115G-AERO-03/02 Design Tool and Design Kits (DK) The basic content of a design kit is described in the table below. The interface formats to and from Atmel rely on IEEE or industry standard: * * * * * VHDL for functional descriptions VHDL or EDIF for netlists Tabular, log or .CAP for simulation results SDF (VITAL format) and SPF for back annotation LEF and DEF for physical floor plan information The design kit supported for several commercial tools are listed below. Design Kit Support * * * * Cadence (VHDL and gate) Mentor (VHDL and gate) Synopsys (VHDL and gate) Vital (VHDL and gate) Table 3. Design Kit Description Design Tool or library Design manual and libraries VHDL library for blocks Synthesis library Gate level simulation library Design rules analyser Power consumption analyser Floor plan library Timing analyser library Package and bonding software Scan path and JTAG insertion ATG and fault simulation library PIM MISS (1) Atmel Software Name Third Party Tools (1) (1) (1) (1) STAR COMET (1) (1) Note: 1. Refer to "Design kits cross reference tables" ATD-TS-WF-R0181 10 MG2RT 4115G-AERO-03/02 MG2RT Electrical Characteristics Absolute Maximum Ratings Ambient temperature under bias (TA) Military ...................................................... -55 to +125C Junction temperature..............................TJ < TA + 20C Storage temperature................................. -65 to +150C TTL/CMOS: Supply voltage VDD ................................... -0.5V to +7V I/O voltage ......................................-0.5V to VDD + 0.5V Note: Stresses above those listed may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended period may affect device reliability. DC Characteristics Table 4. Specified at VDD = +5V 10% Symbol Parameter Input LOW voltage CMOS input TTL input Input HIGH voltage CMOS input TTL input Output LOW voltage TTL Output high voltage CMOS TTL Schmitt trigger positive threshold CMOS input TTL input Schmitt trigger negative threshold CMOS input TTL input CMOS hysteresis 25C/5V TTL hysteresis 25C/5V Input leakage No pull up/down Pull up Pull down 3-State Output Leakage current Output Short circuit current IOS IOSN IOSP ICCSB ICCOP Leakage current per cell Operating current per cell 1.0 0.39 3.9 2.4 3.6 1.6 Min Typ Max 1.5 0.8 Unit Conditions VIL 0 0 V VIH 3.5 2.2 VDD VDD V VOL 0.4 V IOL = -12, 6, 3 mA(1) VOH V IOL = -12, 6, 3 mA(1) VT+ V VT- 1.2 1.0 1.9 0.6 V Delta V V IL -55 79 1 -69 125 5 -120 330 A A A A mA mA nA A/MHz BOUT12 VOUT = 4.5V VOUT = VSS IOZ 1 5 48 36 10.0 0.53 Note: 1. According buffer: Bout12, Bout6, Bout3. 11 4115G-AERO-03/02 Table 5. Specified at VDD = +3V 10% Symbol Parameter Input LOW voltage LVCMOS input LVTTL input Input HIGH voltage LVCMOS input LVTTL input Output LOW voltage TTL Output high voltage TTL Schmitt trigger positive threshold LVCMOS input LVTTL input Schmitt trigger negative threshold LVCMOS input LVTTL input CMOS hysteresis 25C/5V TTL hysteresis 25C/5V Input leakage No pull up/down Pull up Pull down 3-State Output Leakage current Output Short circuit current IOS IOSN IOSP ICCSB ICCOP Leakage current per cell Operating current per cell 0.6 0.2 -20 32 2.4 Min Typ Max 0.3 VDD 0.8 Unit Conditions VIL 0 0 V VIH 0.7 VDD 2.0 VDD VDD V VOL 0.4 V IOL= -6, 3, 1.5 mA(1) VOH V IOH= -4, 2, 1 mA(1) VT+ 2.2 1.2 V VT- 0.9 0.8 0.8 0.2 24 42 V Delta V V 1 -60 150 IL A A A A BOUT12 mA mA nA A/MHz VOUT = VDD VOUT = VSS IOZ 1 24 12 5 Note: 1. According buffer: Bout12, Bout6, Bout3. 12 MG2RT 4115G-AERO-03/02 MG2RT AC Characteristics Table 6. AC Characteristics TJ = 25C, Process typical (all values in ns) VDD Buffer BOUT12 Description Output buffer with 12 mA drive Load 60 pf Tphl Tplh BOUT3 Output buffer with 3 mA drive 60 pf Tphl Tplh BOUTQ Low noise output buffer with 12 mA drive 60 pf Tphl Tplh B3STA3 3-state output buffer with 3 mA drive 60 pf Tphl Tplh B3STA12 3-state output buffer with 12 mA drive 60 pf Tphl Tplh B3STAQ Low noise 3-state output buffer with 12 mA drive 60 pf Tphl 4.42 6.34 2.79 3.01 3.72 4.61 4.89 2.64 6.44 4.07 4.36 4.73 6.24 7.35 4.86 2.97 6.36 4.48 2.76 4.63 3.64 7.22 Transition Tplh 5V 2.53 3V 3.91 13 4115G-AERO-03/02 Table 7. AC Characteristics TJ = 25C, Process typical (all values in ns) VDD Cell BINCMOS Description CMOS input buffer Load 15 fan Tphl Tplh BINTTL TTL input buffer 16 fan Tphl Tplh INV Inverter 12 fan Tphl Tplh NAND2 2 - input NAND 12 fan Tphl Tplh Tphl FDFF D flip-flop, Clk to Q 8 fan Ts Th Tplh BUF4X High drive internal buffer 51 fan Tphl Tplh NOR2 2-Input NOR gate 8 fan Tphl OAI22 4-input OR AND INVERT gate Tplh 8 fan Tphl Tplh OSFF D flip-flop with scan input, Clk to Q Tphl 8 fan Ts Th 0.56 -0.34 0.8 -0.6 0.42 0.83 1.00 0.54 1.23 1.38 0.37 0.68 0.45 1.14 0.58 0.65 0.81 1.08 0.33 -0.12 0.76 0.44 -0.24 1.1 0.66 0.8 0.68 0.9 1.21 1.02 0.42 0.73 0.53 1.11 0.7 0.52 1.1 0.8 0.75 0.9 1.06 1.31 Transition Tplh 5V 0.77 3V 1.14 14 MG2RT 4115G-AERO-03/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 RF/Automotive Atmel Heilbronn Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Microcontrollers Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 ASIC/ASSP/Smart Cards Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Atmel Smart Card ICs Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Atmel (R), is a registered trademark of Atmel Corporation. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4115G-AERO-03/02 /xM |
Price & Availability of MG2RT
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |