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FUJITSU SEMICONDUCTOR
FR50 32-BIT MICROCONTROLLER MB91F364G Short specification
Release 4.2 05-Aug-2002 Fujitsu Ref. AEQ32091A
FUJITSU MICROELECTRONICS EUROPE GmbH European Microcontroller Design Centre (EMDC) Am Siebenstein 6 D-63303 Dreieich-Buchschlag
Fujitsu, EMDC
MB91F364G - Short specification
Copyright (c) 2001 Fujitsu Limited Tokyo, Japan, FUJITSU MICROELECTRONICS EUROPE GmbH and Fujitsu Microelectronics Inc. USA. All Rights Reserved. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. No part of this document may be copied or reproduced in any form or by any means or transferred to any third party without the prior consent of Fujitsu. The information contained in this document has been carefully checked and is believed to be entirely reliable. However, the information is preliminary and subject to change. Fujitsu and its subsidiaries assume no responsibility for inaccuracies.
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MB91F364G - Short specification
Revision History
Revision
1.0 1.2 1.5 1.6 1.7 1.8
Date
07-May-2001 10-Sep-2001 26-Oct-2001 6-Nov-2001 8-Nov-2001 2-Dec-2001
Name
ALan Br JF Br JF Br First Release
Item
add 1 more UART channel, remove 48 bits for time base timer, remove IRDA option from SIO Pin assignment updated after pinout meeting Update with regard to optional features Pinout changed for better ADC supply Add pinlist, add LED port in diagram, add IO map and vector table, add some references to the MB91360 hardware manual, add pinning in flash memory mode Interrupt table: Resource numbers removed; BDSUENA (BDSU enable) at addr. 0x01FF; Port R and Port P[3:2] changed to type "A"; I2C pad drawing added LIN-UART chapter added DAC added, outputs at pins 117 + 118 Flash mode pin table changed (A[20] added) Added "Flash Memory CPU Access" section I/O map: Initial values of FMCS and FMWT changed LIN-UART registers renamed: SCR0 --> SCR5 SCR1 --> SCR6 and so on, to disinguish from old UART reg's LIN-UART section: All user-relevant data added DAC port behaviour added Block structure updated (BDSU under eval.) Pin 64 changed to VSS (must NOT be connected in first engineering samples) IO-Map: OCS23 register entry added
2.0
07-Dec-2001
JF
2.2 2.3 2.4 2.6 2.7
20-Dec-2001 16-Jan-2002 21-Jan-2002 27-Jan-2002 12-Mar-2002
JF JF JF JF JF
2.9 3.0 3.2 4.1 4.2
04-Apr-2002 14-Jun-2002 08-July-2002 25-July-2002 05-Aug-2002
JF JF JF JF JF
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MB91F364G - Short specification
Table of Contents
1 MB91F364G Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 1.2 1.3 1.4 1.5 1.6 MB91F364G Block Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Core Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I/O Pins and Their Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I/O Circuit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2 3
Flash Memory Mode of MB91F364G . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Flash Memory CPU access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 3.2 Flash Control Status Register (FMCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Flash Wait Control Register (FMWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 5 6 7
Power-on Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Handling of Unused Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Emulation Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
LIN-UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.4 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Serial Mode Register (SMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Reception Data Register (RDR) and Transmission Data Register (TDR) . . 29 Extended Status/Control Register (ESCR) . . . . . . . . . . . . . . . . . . . . . . . . . 30 Extended Communication Control Register (ECCR) . . . . . . . . . . . . . . . . . . 32 Baud Rate Detection Using the ICU's. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Operation in asynchronous mode (Operation modes 0 and 1) . . . . . . . . . . 34 Operation in Synchronous Mode (Mode 2) . . . . . . . . . . . . . . . . . . . . . . . . . 36 Operation with LIN Function (mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Direct Access to Serial Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Data Format setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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MB91F364G - Short specification
7.5.6 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.7 7.8 7.8.1 7.8.2 7.8.3 7.8.4 7.8.5 7.9 7.9.1 7.9.2 7.9.3 7.10 7.10.1 7.10.2 7.11
Register / Flag bits summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Reception Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Transmission Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 LIN Synchronization Break Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 LIN Synchronization Field Edge Detection Interrupts . . . . . . . . . . . . . . . . . 42 Bus Idle Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Interrupt Generation and Flag Set Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Reception Interrupt and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Transmission Interrupt and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 LIN Synch Break Detection Interrupt and Flags. . . . . . . . . . . . . . . . . . . . . . 46 LIN Synch Field Detection Interrupt and Flags . . . . . . . . . . . . . . . . . . . . . . 46 Bus Idle Interrupt and Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Sampling Clock Edge Selection and clock delay . . . . . . . . . . . . . . . . . . . . . 47 Synchronous Start-Stop-Bit-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Continuous serial clock output enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 LIN Communication Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 UART as Master device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 UART as slave device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Summary of the Changes to previous UARTs . . . . . . . . . . . . . . . . . . . . . . . . 52
8
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.1 8.2 8.3 8.4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Clock Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Clock Modulator Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Appendix A I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Appendix B Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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MB91F364G - Short specification
1
1.1
MB91F364G Overview
MB91F364G Block Structure
4 MHz Oscillator Clock Modulator FR50 Core Watchdog Timer
User RAM 12 KB
D32 I-Bus 32
BDSU
Bit Search Module
The BDSU is a new optional feature, which cannot be emulated by MB91FV360GA. Its implementation is under evaluation.
Boot-ROM 2 KB Flash Memory 256 KB
32
Bus Converter
Voltage regulator
F-Bus X-Bus 32
F-bus RAM 4 KB R-Bus Adapter
16 R-Bus
User Logic Bus Interface
CAN (1ch)
SIO (1ch)
ICU (4ch)
Free Running Timer (2)
OCU (4ch)
LIN-UART/ U-timer (2ch)
UART/ U-timer (1ch)
DAC (2 ch) ADC (12 ch) I2C
Ext. Interrupt (8+NMI)
Prog. Pulse Generator (4ch) Calibration for 32kHz clock LED port (8ch) Real Time Clock (32kHz/4Mhz)
Reload Timer (3ch)
LIN-UART is a new feature which cannot be emulated by MB91FV360GA. The correct functionality cannot be guaranteed until evaluation has been carried out..
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MB91F364G - Short specification
1.2
Core Functionality
Feature 32-bit Fujitsu RISC Core FR30 software compatible Background debug support unit Features see BDSU spec. Remarks
Function FR50 Core
BDSU (optional)
This is a new optional module which cannot be emulated by MB91FV360GA. The implementation of this feature is under evaluation. initial value for oscillation stabilization time in mode MD="000": 32 ms at 4 MHz oscillation clock. Time starts after release of INITX
Clock module (clock control, clock divider, PLLs)
Setting of frequencies for CPU and peripherals
Watchdog
User RAM 12 kB F-bus RAM 4 kB Flash Memory 256 kB
Low power consumption modes: RTC mode: only the Real Time Clock and the oscillator are active (= STOP mode and bit 0 of STCR is set to 0) STOP mode: all internal circuits and the oscillation circuits are halted adjustable watchdog timer interval (between 220 and 226 system clock cycles) RAM for user data RAM for data and code sector architecture: sector 0: 64 kB sector 1: 32 kB sector 2: 8 kB sector 3: 8 kB sector 4: 16 kB | V 16 bit | sector | sector | sector | sector | sector 5: 64 kB 6: 32 kB 7: 8 kB 8: 8 kB 9: 16 kB | V 16 bit
see remark below table see remark below table Minimum 10000 program/erase cycles Minimum 10 years data retention Net read cycle time to the memory: 40 ns. For overall access time see MB91360 Hardware Manual. located on F-Bus The last two addresses of this flash memory 0FFFF8H and 0FFFFCH overlap with the fixed reset and fixed mode vectors. Writing to these addresses is not possible.
write access is 16 bit wide, read access can be 16 or 32 bit wide
Boot ROM 2 kB Interrupt Controller
1 non-maskable ext. interrupt channel, 8 external interrupt channels, 38 internal interrupts, 16 programmable priority levels
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MB91F364G - Short specification
Bit Search Module
Fixed Reset Vector Voltage Regulator
Searches a word for the position of the first "1" and "0" change bit, starting from the MSB. Performs the search in 1 cycle. Hardwired reset and mode vector Generates internal voltage of 3.3 V
code starts at 0F:4000H supply from an external regulator is also under consideration
Remark: Set bit 9 (SYNCR) of TBCR to 1 to enable the synchronization of the reset signal; a reset will be generated only after all bus accesses have been done. This avoids that erroneous data are written into the RAMs during reset.
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MB91F364G - Short specification
1.3
Features
Feature 16-bit PWM Timer 16 bit down counter, cycle and duty setting registers interrupt at triggering, cycle or duty match can be triggered by software or reload timer PWM operation and one-shot operation Clock disable internal prescaler allows fRES/1, fRES/4, fRES/16, fRES/64 as counter clock successive approximation, internal sample and hold circuit 10-bit resolution, 5 V operation, program selectable analogue input channels: single conversion mode continuous conversion mode stop conversion mode activation by software or external trigger can be selected Prescaling is done internally Clock disable R-2R D/A converter 10-bit resolution, 5 V operation Clock disable 16-bit reload timer, includes clock prescaler (fRES/21, fRES/ 23, fRES/25) can be programmed to be edge sensitive or level sensitive interrupt mask and request pending bits per channel highest priority of all interrupts required frequencies are 90-300 Hz Maximum allowed frequency for digital part of ADC is 32 MHz Remarks
Function PPG (4 channels)
ADC (12 channels)
DAC (2 channels) Basic Interval Timer (3 channels) External Interrupt (8 channels)
Non-maskable Interrupt (NMI) (1 channel)
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MB91F364G - Short specification
CAN (1 channel)
I2C for standard and fast mode
conforms to CAN specification version 2.0 A and B automatic re-transmission in case of error automatic transmission responding to remote frame prioritized 16 message buffer for data and IDs supports multiple messages flexible configuration of acceptance filtering: full bit compare / full bit mask / two partial bit masks supports up to 1 Mb/s Clock Disable master or slave transmission arbitration function clock synchronization function slave address and general call address detect function transfer direction detect function start condition repeat generation and detection function bus error detect function compatible to I2C standard and fast mode specification (operation up to 400 kHz, 10 bit addressing) includes clock divider functionality
The CAN module is internally connected to CS7X, appropriate settings are automatically done during startup when running the BootROM code.
SCL and SDA lines include optional noise filter. The noise filter allows the suppression of spikes in the range of 1 to 1.5 cycles of CLKP. Communication on the I2C bus between other connected devices is not possible if MB91F364G is switched off.
16-bit Input Capture (ICU) (4 channels)
16-bit Output Compare OCU (4 channels) Free running Timer (2 channels for ICU and OCU modules)
Clock disable rising edge, falling edge or rising & falling edge sensitive two 16-bit capture registers signals an interrupt at external event Clock disable signals an interrupt when a match with of 16-bit IO timer occurs an output signal can be generated Clock disable 16-bit free running timer, signals an interrupt when overflow or match with compare register_0 includes prescaler (fRES/22, fRES/24, fRES/26) timer data register has R/W access Clock disable
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MB91F364G - Short specification
Serial IO SIO Synchronous Serial Interface (1 channel) + SIO-Prescaler (1 channel)
Serial IO transfer can be started from MSB or LSB supports internal clock synchronized transfer and external clock synchronized transfer prescaler for shift clock allows: fRES/3, fRES/4, fRES/5, fRES/6, fRES/7, fRES/8 Clock disable serial I/O port for performing synchronous and asynchronous (start-stop synchronization) communication full duplex, double buffering supports multi-processor mode special features for LIN-bus systems variable data length (7/8 bit) 1 or 2 stop bits error detection function (parity, framing, overrun) interrupt function NRZ type transfer format baud rate generated by Baudrate Generator 15-bit timer to generate the required UART clock: fRES/21,...,~fRES/215 Clock disable
supports positive and negative clock edge synchronization
UART with LIN option (optional) (2 channels)
This is a new module which cannot be emulated by MB91FV360GA. The correct functionality cannot be guaranteed until evaluation has been carried out.
polarity of the port signals for receive and transmit is programmable
Baudrate Generator (1 per UART)
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MB91F364G - Short specification
UART (1 channel)
serial I/O port for performing asynchronous (start-stop synchronization) communication full duplex, double buffering supports multi-processor mode variable data length (7/8 bit) 1 or 2 stop bits error detection function (parity, framing, overrun) interrupt function NRZ type transfer format polarity of the port signals for receive and transmit is programmable
U-Timer (1 channel)
baud rate generated by U-Timer 16-bit timer to generate the required UART clock: fRES/25,...,~fRES/221 (asynchr. mode) Clock disable
Real Time Clock (RTC) (Watch Timer)
facility to correct oscillation deviation read/write accessible second/minute/ hour registers can signal interrupts every second/ minute/hour/day internal clock divider and prescaler provide exact 1s clock based on a 4 MHz or a 32 kHz clock input Clock disable prescaler value for 4 MHz is 1E847FH prescaler value for 32 kHz is 04000FH
Sub-clock/Calibration 32 KHz
LED Port (8 channels) Clock modulator
RTC module can be clocked either from 32kHz quartz or from 4 MHz quartz. Dynamic switching is not allowed. Additionally, a calibration of the RTC timer in 32 kHz operation, based on the more accurate 4 MHz clock timing, is possible. allows to source 14 mA at Vdd-0.8 V and sink 24 mA at Vss+0.8 V respectively
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MB91F364G - Short specification
1.4
Pin Assignment
SIO
LIN-UART
PPG
CAN
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 (#) 63 62 61
VDD BREAKX LTESTX VDDI VSS VCC3C OCPA3 OCPA2 OCPA1 SCK6 SOT6 SOT5 SCK5 OCPA0 SCK3 SOT3 SIN3 VSS SIN5 VSS VDD SIN6 VSS
Note: Pin 64 (VSS) must NOT be connected in first series of engineering samples.
VSS VDD
X0
Port H
PG
PM PQ
X1
AVSS, AVRL AVRH AVCC AN6 AN7 AN8 AN9 AN10 AN11
VSS VDD
VDD
MONCLK
HSTX NMIX SELCLK
SDA SCL SOT0 SIN0
2 AN1
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1
ADC
I2C UART
32kHz
VDD
AN5
VSS X1A
AN0
AN2 AN3 AN4
X0A
4 MHz
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
VDD PR0 PR1 PR2 PR3 PR4 PR5 PR6 PR7 VSS VDD LED0 LED1 LED2 LED3 VSS LED4 LED5 LED6 LED7 VSS VDD PO4 PO5 PO6 PO7 DA0 DA1
Port N
Port T
Port O
TX0 RX0 VSS
P.P
VCC3C VDD
VDDI
VDDI
INITX MD2 MD1 MD0 ATGX CPUTESTX TESTX VSS VDD OUT3 OUT2 OUT1
MB91F364G
Port L Port J
IN1 IN0 VSS VDD INT7 INT6 INT5
top view
Port O
INT4 INT3 INT2 INT1 INT0 VSS
External Interrupts
Port K
ICU
120-pin package FPT-120P-M21
OUT0 IN3 IN2
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
Port R
OCU
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Fujitsu, EMDC
MB91F364G - Short specification
1.5
I/O Pins and Their Functions
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Pin Name
I/O
General Purpose IO Port PH0 PH1 PH2 PH3 PH4 PH5
Circuit Type B B B B B B
Function
AN0 AN1 AN2 AN3 AN4 AN5 AVSS, AVRL AVRH AVCC AN6 AN7 AN8 AN9 AN10 AN11 VSS VDD SDA SCL SOT0 SIN0 HSTX NMIX SELCLK VDD MONCLK VSS
I/O I/O I/O I/O I/O I/O
ADC input 0 ADC input 1 ADC input 2 ADC input 3 ADC input 4 ADC input 5 AVSS, analog reference low
R
analog reference high AVCC
I/O I/O I/O I/O I/O I/O
PH6 PH7 PG0 PG1 PG2 PG3
B B B B B B
ADC input 6 ADC input 7 ADC input 8 ADC input 9 ADC input 10 ADC input 11
I/O I/O I/O I/O I I I
PM2 PM3 PQ1 PQ0
YA YA A A F E F
I2C SDA I2C SCL UART 0 SOT UART 0 SIN hardware standby non maskable interrupt select RTC clock
O
QB
modulated clock output
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MB91F364G - Short specification
Pin No 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
Pin Name
I/O
General Purpose IO Port I I
Circuit Type
Function
X1A X0A VDD X1 X0 VSS INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 VDD VSS IN0 IN1 IN2 IN3 OUT0 OUT1 OUT2 OUT3 VDD VSS TESTX CPUTESTX ATGX MD0
O I
32 kHz oscillator pin 32 kHz oscillator pin
O I
H H
4 MHz oscillator pin 4 MHz oscillator pin
I/O I/O I/O I/O I/O I/O I/O I/O
PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7
B B B B B B B B
external interrupt 0 external interrupt 1 external interrupt 2 external interrupt 3 external interrupt 4 external interrupt 5 external interrupt 6 external interrupt 7
I/O I/O I/O I/O I/O I/O I/O I/O
PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7
B B B B B B B B
ICU input 0 (see note 1) ICU input 1 (see note 1) ICU input 2 (see note 1) ICU input 3 (see note 1) OCU output 0 OCU output 1 OCU output 2 OCU output 3
I I I/O I PI3
E E A T
test input test input ADC trigger mode pin 0
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MB91F364G - Short specification
Pin No 58 59 60 61 62 63 64
Pin Name
I/O
General Purpose IO Port
Circuit Type T T U
Function
MD1 MD2 INITX VDD VCC3C VCC3C VSS (#)
I I I
mode pin 1 mode pin 2 inital pin
pins for regulator capacitance or for external supply of core voltage Don't connect to VSS in first ES series ! Leave open! See note 3 separate core supply
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
VDDI VDDI VDDI BREAKX VDD VSS RX0 TX0 OCPA0 OCPA1 OCPA2 OCPA3 VSS SIN5 SCK5 SOT5 SOT6 SCK6 SIN6 VDD VSS I/O I/O I/O I/O I/O I/O PT0 PT1 PT2 PT3 PT4 PT5 A A A A A A I/O I/O I/O I/O I/O I/O PP1 PP0 PO0 PO1 PO2 PO3 Q Q A A A A I BREAKX E
BDSU break pin
CAN RX CAN TX PPG output 0 PPG output 1 PPG output 2 PPG output 3
LIN-UART 5 SIN LIN UART 5 SCK LIN UART 5 SOT LIN UART 6 SOT LIN UART 6 SCK LIN UART 6 SIN
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MB91F364G - Short specification
Pin No 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115
Pin Name
I/O
General Purpose IO Port PN3 PN4 PN5
Circuit Type A A A SIO SIN
Function
SIN3 SOT3 SCK3 VSS LTESTX VDD PR0 PR1 PR2 PR3 PR4 PR5 PR6 PR7 VSS VDD LED0 LED1 LED2 LED3 VSS LED4 LED5 LED6 LED7 VSS VDD PO4 PO5 PO6
I/O I/O I/O
SIO SOT SIO SCK
I
LTESTX
E
test pin
I/O I/O I/O I/O I/O I/O I/O I/O
PR0 PR1 PR2 PR3 PR4 PR5 PR6 PR7
A A A A A A A A
port R 0 port R 1 port R 2 port R 3 port R 4 port R 5 port R 6 port R 7
I/O I/O I/O I/O
PJ0 PJ1 PJ2 PJ3
J J J J
LED port 0 LED port 1 LED port 2 LED port 3
I/O I/O I/O I/O
PJ4 PJ5 PJ6 PJ7
J J J J
LED port 4 LED port 5 LED port 6 LED port 7
I/O I/O I/O
PO4 PO5 PO6
A A A
port O 4 port O 5 port O 6
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Fujitsu, EMDC
MB91F364G - Short specification
Pin No 116 117 118 119 120
Pin Name
I/O
General Purpose IO Port PO7
Circuit Type A C C port O 7
Function
PO7 DA0 DA1 VSS VDD
I/O O O
See note 2 See note 2
Note 1: If the port L function register bits are cleared, the ICU input lines are connected with the LSYNC outputs of the LIN-UARTs. Please refer to section 7.4 Baud Rate Detection Using the ICUs. Note 2: The pins DA1 and DA0 are also used for digital test functions. To ensure proper system function, always write '0' to port P data direction register DDRP[3:2] and port P function register PFRP[3:2]. Note 3: Pin 064 (VSS) will be available after redesign. In the first ES series, this pin must be left open.
Circuit Type A B C E F H I J Q QB R T U YA
Description I/O, IOH=4 mA / IOL=4 mA, CMOS Automotive Schmitt-Trigger Input, STOP control I/O, IOH=4 mA / IOL=4 mA, CMOS Automotive Schmitt-Trigger Input, Analog Input, STOP control Analog output CMOS Schmitt-Trigger Input, 50K Pull-up CMOS Schmitt-Trigger Input 4 MHz Oscillator Pin 32 kHz Oscillator Pin I/O, IOH=14 mA / IOL = 24 mA, CMOS Automotive Schmitt-Trigger Input, STOP control (LED) I/O, IOH=4 mA / IOL=4 mA, CMOS Input, STOP control O, IOH=8 mA / IOL=8 mA, STOP control AVRH Input CMOS Input, can withstand VID for flash programming CMOS Schmitt-Trigger Input, 50K Pull-up, 3.3 V and 5 V inputs to core I/O, IOH=3mA / IOL=3mA (I2C), CMOS Schmitt Trigger Input, STOP control
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Fujitsu, EMDC
MB91F364G - Short specification
1.6
I/O Circuit Types
The new I/O circuit type YA is described below. For the other types please refer to the MB91360 Hardware Manua
Type
Circuit type
Remarks
Note: Symbols used in circuit types (Common to all circuit diagrams) P: P channel transistor N: N channel transistor R: Diffusion resistor
YA
P Digital output
N R VSS
Digital output
* I/O CMOS Schmitt-Trigger Input, STOP control , IOH = 3 mA, IOL = 3 mA, in I2C mode operating as open drain outputs
Digital inStop control
page 19 of 72
Fujitsu, EMDC
MB91F364G - Short specification
2
Flash Memory Mode of MB91F364G
To enter the flash memory mode set mode pins MD0 to MD2 to "111". In this mode, the pins correspond to those of the MBM29LV400C standard flash memory as shown in the following table.
MB91F364G Pin number 1 2 34 to 41 44 to 47 48 to 51 54 55 56 57 58 59 60 90 92 to 99 102 to 105 107 to 110 113 to 115 116 117 118 Normal function AN0 AN1 INT0 to INT7 IN0 to IN3 OUT0 to OUT3 TESTX CPUTESTX ATGX MD0 MD1 MD2 INITX LTESTX PR0 to PR7 LED0 to LED3 LED4 to LED7 PO4 to PO6 PO7 PP2 PP3 Flash Memory mode ATDINa BYTEX DQ8 to DQ15 DQ0 to DQ3 DQ4 to DQ7 OEX CEX RY/BYX HVDA9 HVDR5 HVDOE RSTX EQINa AQ0 to AQ7 AQ8 to AQ11 AQ12 to AQ15 AQ16 to AQ18 WEX AQ 20 TSTX b Function in Flash Memory mode Access Signal ATD switch 8/16 bit mode Data input/output Data input/output Data input/output Output Enable Chip Enable Ready/Busy output High Volt. A9 c High Volt. RESET c High Volt. OE
c
MBM29LV400C
BYTE DQ8 to DQ15 DQ0 to DQ3 DQ4 to DQ7 OE CE RY/BY A9 (VID) RESET (VID) OE (VID) RESET
Hardware Reset Access Signal EQ Address input Address input Address input Address input Write Enable Address input Flash Test
A0 to A7 A8 to A11 A12 to A15 A16 to A18 WE A 20
a.Pins 1 and 90 must be pulled low in Flash Memory Mode c.Functionality as described in the Data Sheet of MBM29LV400C. b.Pin 118 must be pulled high in Flash Memory Mode. AVRH must be tight to a high level. All other Pins can be left open during Flash Memory Mode.
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MB91F364G - Short specification
3
Flash Memory CPU access
This section overwrites parts of the chapter 31 Flash Memory in hardware manual. The flash interface of MB91F364G has changed initialisation of control registers. With operation initialization reset (RST), the flash control registers are set to guarantee flash access at 64 MHz CPU clock operation.
3.1
Flash Control Status Register (FMCS)
The initial value of bit FACCEN is 0 now, fast access is enabled. address
00007000H
bit 7 FACCEN R/W 0 0
bit6 ---R/W 1 1
bit 5 ---R/W 1 1
bit 4 RDYEG R 0 0
bit 3 RDY R X X
bit 2 RDYI R/W 0 0
bit 1 WE R/W 0 0
bit 0 LPM R/W 0 0
access initial value value after Boot ROM
Bit 7: FACCEN: FACC Output Enable Fast Flash Macro (used in MB91F364G): 0: Synchronous read access using ATDIN and EQIN signals - recommended setting 1: Asynchronous read access The other bits of FMCS match the HW manual.
3.2
Flash Wait Control Register (FMWT)
The initial value of bit FAC0 is 1 now, the length of FACC low pulse and ATDIN high pulse is 1 CLKB cycle. address 00007004H access initial value
value after Boot ROM Fast Flash Macro
bit 7 ----
bit6 ---R/W 0
bit 5 FAC1 R/W 0
bit 4 FAC0 R/W 1
bit 3 EQINH R/W 0
bit 2 WTC2 R/W 0
bit 1 WTC1 R/W 1
bit 0 WTC0 R/W 1
0
0
1
0
0
1
1
Bits 5,4: Fast Flash Macro : These bits control the length of the high pulse for the ATDIN signal. The changed initial value of FAC1=0 and FAC0=1 set FACC/ATDIN length to 1 CLKB cycle. The other bits of FMWT match the HW manual.
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Fujitsu, EMDC
MB91F364G - Short specification
4 5 6
6.1
Power-on Sequence Handling of Unused Input Pins Emulation Device
Overview
see MB91360 Hardware Manual
see MB91360 Hardware Manual
Besides for the UART with LIN option and for the support for background debugging MB91FV360GA can be used as emulation device for MB91F364G.
page 22 of 72
Fujitsu, EMDC
MB91F364G - Short specification
7
7.1
LIN-UART
Overview
The UART (Universal [A]synchronous Receiver and Transmitter) with LIN (Local Interconnect Network) Function is a general-purpose serial data communication interface for performing synchronous or asynchronous communication with external devices. The UART provides bidirectional communication function (normal mode), master-slave communication function (multiprocessor mode in master systems), and special features for LIN-bus systems (working both as master or slave device). This UART is similar to older UART modules but not software compatible.
Item Data buffer Serial Input Transfer mode Full-duplex 5 times oversampling in asynchronous mode - Clock synchronous (start-stop synchronization and start-stop-bitoption) - Clock asynchronous (using start-, stop-bits) - A dedicated baud rate generator is provided, which consists of a 15-bit-reload counter - An external clock can be input and also be adjusted by the reload counter - 7 bits (not in synchronous or LIN mode) - 8 bits Non-return to zero (NRZ) and return to zero (RZ) Clock synchronization to the falling edge of the start bit in asynchronous mode - Framing error - Overrun error - Parity error - Reception interrupt (reception complete, reception error detect) - Transmission interrupt (transmission complete) - Bus-Idle interrupt (belongs to reception interrupt) - LIN-Sync-break interrupt (belongs to rcp. interrupt) One-to-n communication (one master to n slaves) can be performed (This function is supported both for master and slave system). Function as Master- or Slave-UART Direct access possible - Operation as master device - Operation as slave device - Generation of LIN-Sync-break - Detection of LIN-Sync-break - Detection of start/stop edges in LIN-Sync-field connected to ICU The synchronous serial clock can be output continuously on the SCK pin for synchronous communication with start & stop bits Special synchronous Clock Mode for delaying clock (useful for SPI) Function
Baud rate
Data length Signal mode Start bit timing Reception error detection
Interrupt request
Master-slave communication function (multiprocessor mode) Synchronous mode Transceiving wires
LIN bus options
Synchronous serial clock Clock delay option
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Fujitsu, EMDC
MB91F364G - Short specification
7.2
Block Diagram
CLK Reload Counter
(OTO, EXT, REST)
transmission clock TSCK reception clock RSCK
RECEPTION CONTROL CIRCUIT TRANSMISSION CONTROL CIRCUIT
PE
ORE FRE TIE RIE LBIE LBD BIE RBI TBI reception IRQ
SCK
Pin
FL85
Interrupt Generation circuit
Start bit Detection circuit
Transmission Start circuit
SIN
Pin
INV (from ECCR)
SEDGE
Received Bit counter
Transmission Bit counter
TDRE
transm. IRQ
SOUT
Oversampling Unit Received Parity counter Transmission Parity counter
RDRF reception complete SIN SOUT
Pin
INV
SIN
LSYN (to ICU)
LIN break and Synch Field Detection circuit
Reception shift register
Transmission shift register
transmission start
LIN break generation circuit
Error Detection STR (to EI2OS)
PE ORE FRE
Bus idle Detection circuit RDR
LBD
LBR LBL1 LBL0
TDR
RBI TBI
Internal data bus
PE ORE FRE RDRF TDRE BDS RIE TIE
SSR register
MD1 MD0 (OTO) (EXT) (REST) UPCL SCKE SOE
SMR register
PEN P SBL CL A/D CRE RXE TXE
SCR register
LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES
ESCR register
INV LBR MS SPI SSM BIE RBI TBI
ECCR register
page 24 of 72
Fujitsu, EMDC
MB91F364G - Short specification
7.3
7.3.1
Registers
Register Addresses
MB91F364G containes 2 LIN-UARTS named "UART5" and "UART6". UART5 is connected with the pins SIN5, SCK5, SOT5. UART6 is connected with the pins SIN6, SCK6, SOT6. The registers are nammed accordingly in the I/O map and have the following addresses:
UART5 Address: 0198H 019AH 0198H 0198H UART6 Address: 01A0H 01A2H 01A4H 01A6H +0 SCR5 (Serial Control Register) SSR5 (Serial Status Register) ESCR5 (Extended Status/Control R.) BGR15 (Baud Rate Generator R. 1) +0 SCR6 (Serial Control Register) SSR6 (Serial Status Register) ESCR6 (Extended Status/Control R.) BGR16 (Baud Rate Generator R. 1) +1 SMR5 (Serial Mode Register) RDR/TDR5 (Rx, Tx Data Register) ECCR5 (Extended Comm. Contr. R.) BGR05 (Baud Rate Generator R. 0) +1 SMR6 (Serial Mode Register) RDR/TDR6 (Rx, Tx Data Register) ECCR6 (Extended Comm. Contr. R.) BGR06 (Baud Rate Generator R. 0)
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Fujitsu, EMDC
MB91F364G - Short specification
7.3.2
Serial Control Register (SCR)
15
14
13
12
11
10
9
8
Initial value 00000000B
R/W R/W R/W R/W R/W W R/W R/W
bit8 TXE 0 1 bit9 RXE 0 1 bit10 CRE* 0 1 bit11 AD 0 1 bit12 CL*2 0 1 bit13 SBL*3 0 1 bit14 P 0 1 bit15 R/W W : : : Readable and writable Write only (read returns always "0") Initial value PEN*4 0 1 Parity disabled Parity enabled Parity Enable Parity setting Even Parity enabled Odd Parity enabled 1 stop bit 2 stop bits Stop bit length 7 bits 8 bits Character (Data frame) Length Address / Data bit Read Received data bit Received address bit Write Write data bit to be sent Write address bit to be sent RMW-Read Read data bit to be sent Read address bit to be sent ignored Clear all reception errors (PE, FRE, ORE) always 0 Clear Reception errors Write Read Reception enable Disable Reception Enable Reception Transmission enable Disable Transmission Enable Transmission
* Clearing
the reception errors resets the reception finite state machine, so that it is ready to detect a new startbit (resp. a new data frame in mode 2) then.
*2 Character length is fixed to 8 bits in mode 2 and mode 3 (LIN), setting it to "0" in these modes has no effect *3 Stop bit length is fixed to 1 in mode 3 (LIN), setting it to "1" in this mode has no effect *4 Parity is only provided in mode 0 or in mode 2 if SSM is enabled. Setting it to "1" in all other cases has no effect
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Fujitsu, EMDC
MB91F364G - Short specification
7.3.3
Serial Mode Register (SMR)
7
6
5
4
3
2
1
0
Initial value 00000000B
R/W R/W R/W R/W W
W R/W R/W
bit0 SOE 0 1 bit1 SCKE 0 1 bit2 UPCL 0 1 bit3 REST 0 1 bit4 EXT 0 1 bit5 OTO 0 1 bit6 MD0 0 One-to-one external clock Input enable Use ext. Clock with Baud Rate Generator (Reload C.) Use external Clock as is bit7 MD1 0 0 1 1 Operation Mode Setting Mode 0: Asynchronous normal Mode 1: Asynchronous Multiprocessor Mode 2: Synchronous Mode 3: Asynchronous LIN External Serial Clock Source enable Use internal Baud Rate Generator (Reload Counter) Use external Serial Clock Source ignored Restart Counter Restart dedicated Reload Counter write read always 0 UART programmable clear (Software Reset) write ignored Reset UART read always 0 Serial Clock Output enable External Serial Clock Input Internal Serial Clock Output Serial Output enable disable SOT3 pin (high Z) enable SOT3 pin (TxData)
R/W W
: : :
Readable and writable Write only (read returns always "0") Initial value
1 0 1
page 27 of 72
Fujitsu, EMDC
MB91F364G - Short specification
7.3.4
Serial Status Register (SSR)
15
14
13
12
11
10
9
8
Initial value 00001000B
R
R
R
R
R R/W R/W R/W
bit8 TIE 0 1 bit9 RIE 0 1 bit10 BDS* 0 1 bit11 TDRE 0 1 bit12 RDRF 0 1 bit13 FRE 0 1 bit14 ORE 0 1 bit15 PE Parity error No parity error occurred A parity error occurred during reception Overrun error No overrun error occurred An overrun error occurred during reception Framing error No framing error occurred A framing error occurred during reception Reception data register full Reception data register is empty Reception data register is full Transmission data register empty Transmission data register is full Transmission data register is empty Bit direction setting send / receive LSB first send / receive MSB first Reception Interrupt enable Disables Reception Interrupt Enables Reception Interrupt Transmission Interrupt enable Disables Transmission Interrupt Enables Transmission Interrupt
R/W R
: : :
Readable and writable Flag is read only, write to it has no effect Initial value
0 1
* BDS is fixed to "0" in mode 3 (LIN), setting it to "1" in this mode has no effect
page 28 of 72
Fujitsu, EMDC
MB91F364G - Short specification
7.3.5
Reception Data Register (RDR) and Transmission Data Register (TDR)
7
6
5
4
3
2
1
0
Initial values RDR : 0 0 0 0 0 0 0 0 B TDR : 1 1 1 1 1 1 1 1
B
R/W R/W R/W R/W R/W R/W R/W R/W
bit8 R/W Read Write Data Registers Read from Reception Data Register Write to Transmission Data Register
R/W
:
Readable and writable
page 29 of 72
Fujitsu, EMDC
MB91F364G - Short specification
7.3.6
Extended Status/Control Register (ESCR)
15
14
13
12
11
10
9
8
Initial value 0 0 0 0 0 X 0 0B
R/W R/W R/W R/W R/W R/W R/W R/W
bit8 SCES 0 1 bit9 CCO 0 1 bit10 SIOP 0 1 bit11 SOPE 0 1 bit12 LBL0 0 1 0 1 bit14 LBD write 1 0 bit15 LBIE 0 1 R/W X : : : Readable and writable Indeterminate Initial value LIN break detection Interrupt enable LIN break interrupt disable LIN break interrupt enable ignored Clear LIN break detected flag LIN break detected read LIN break detected No LIN break detected Enable Serial Output pin direct Access Serial Output pin direct access disable Serial Output pin direct access enable bit 13 LBL1 0 0 1 1 LIN break length LIN break length 13 bit times LIN break length 14 bit times LIN break length 15 bit times LIN break length 16 bit times Serial Input / Output Pin Access write (if SOPE = "1") SOT3 is forced to "0" SOT3 is forced to "1" read reading the actual value of SIN3 Continuous Clock Output (Mode 2) Continuous Clock Output disabled Continuous Clock Output enabled Sampling Clock Edge Selection (Mode 2) Sampling on rising clock edge (normal) Sampling on falling clock edge (inverted clock)
* Description of the interaction of SOP and SIOP:
SOPE 0 1 SIOP R R/W Writing to SIOP has no effect write "0" or "1" to SOUT Reading from SIOP returns current value of SIN returns current value of SIN
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Fujitsu, EMDC
MB91F364G - Short specification
"1" is the initial value of SIOP, if enabling SOPE. If a Read-Modify-Write cycle is active, the SIOP flag returns the value of the Serial Output pin (SOUT) in the read cycle.
page 31 of 72
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MB91F364G - Short specification
7.3.7
Extended Communication Control Register (ECCR)
7
6
5
4
3
2
1
0
Initial value 0 0 0 0 0 0 X XB
-
W R/W R/W R/W R/W R
R
bit0 TBI 0 1 bit1 RBI 0 1 bit2 BIE 0 1 bit3 SSM 0 1 bit4 SCDE 0 1 bit5 MS 0 1 bit6 LBR 0 1 bit7 INV Invert Serial Data Format Data format NRZ Data format RZ 0 1 ignored Generate LIN break Set LIN break write read always read "0" Master / Slave function in mode 2 Master mode (generating serial clock) Slave mode (receiving external serial clock) Serial Clock Delay enable in mode 2 disable clock delay enable clock delay Synchronous start/stop bits in mode 2 No start/stop bits in synchronous mode 2 Enable start/stop bits in synchronous mode 2 Bus idle interrupt enable disable Bus idle interrupt enable Bus idle interrupt Reception bus idle Reception is ongoing no reception activity Transmission bus idle Transmission is ongoing no transmission activity
R/W R W X
: : : : :
Readable and writable Flag is read only Flag is write only Indeterminate Initial value
page 32 of 72
Fujitsu, EMDC
MB91F364G - Short specification
7.4
Baud Rate Detection Using the ICU's
The LIN-UARTs provide the signal LSYN that can be connected to the ICU so that LSYN's pulse length can be measured to derive the baud rate. The connection of the LSYN signals to the ICUs is controlled by the Port L function register PFRL (address 0415H), bits PFRL[3:0]:
Pin IN0
LIN-UART5 LSYN
Pin IN1
1 0 S PFRL[0]
IN
ICU0
FREE RUN TIMER0 1 0 S PFRL[1]
IN
ICU1
Pin IN2
LIN-UART6 LSYN
Pin IN3
1 0 S PFRL[2]
IN
ICU2
FREE RUN TIMER1 1 0 S PFRL[3]
IN
ICU3
If the PFR bit is set, the ICU is connected to its input pin IN. If the PFR bit is cleared, the pin IN is in port mode (PortL[3:0]), and the LIN-UARTs are connected to the ICU. The user has to take into account that: * ICU0 and ICU1 share one free running timer (prescaler), ICU2 and ICU3 share the other one. * The free running timers can be cleared by enabling this function in OCU0/OCU2 !
page 33 of 72
Fujitsu, EMDC
MB91F364G - Short specification
7.5
Operation modes
The LIN-UART operates in four different modes, which are determined by the MD0- and the MD1-bit of the Serial mode control register (SMCR). Mode 0 and 2 are used for bidirectional serial communication, mode 1 for master/slave communication and mode 3 for LIN master/slave communication.
Operation mode 0 1 2 3 normal mode multiprocessor normal mode LIN mode 8 7 or 8 + 1** 8 Data length parity disabled parity enabled 7 or 8 Synchronization of mode asynchronous asynchronous synchronous asynchronous Length of stop bit 1 or 2 1 or 2 0, 1 or 2 1 data bit direction* L/M L/M L/M L
* means the data bit transfer format: LSB or MSB first ** "+1" means the indicator bit of the address/data selection in the multiprocessor mode, instead of parity. Note: Mode 1 operation is now supported both for master or slave operation of the UART in a master-slave connection system. In Mode 3 the UART function is locked to 8N1-Format, LSB first. If the mode is changed, the UART cuts off all possible transmission or reception and awaits then new action. The MD1 and MD0 bit of the Serial Mode Register (SMR) determine the operation mode of the UART as shown in the following table:
MD1 0 0 1 1 MD0 0 1 0 1 Mode 0 1 2 3 Description Asynchronous (normal mode) Asynchronous (multiprocessor mode) Synchronous (normal mode) Asynchronous (LIN mode)
7.5.1
Operation in asynchronous mode (Operation modes 0 and 1)
Transfer data format: Generally each data transfer in the asynchronous mode operation begins with the start bit (low-level on bus) and ends with at least one stop bit (high-level). The direction of the bit stream (LSB first or MSB first) is determined by the BDS-Bit of the Serial Status Register (SSR). The parity bit (if enabled) is always placed between the last data bit and the (first) stop bit. In operation mode 0 the length of the data frame can be 7 or 8 bits, with or without parity, and 1 or 2 stop bits. In operation mode 1 the length of the data frame can be 7 or 8 bits with a following address-/data-selection bit instead of a parity bit. 1 or 2 stop bits can be selected. The calculation formula for the bit length of a transfer frame is: Length = 1 + d + p + s (d = number of data bits [7 or 8], p = parity [0 or 1], s = number of stop bits [1 or 2])
page 34 of 72
Fujitsu, EMDC
MB91F364G - Short specification
* Operation mode 0
ST D0 D1 D2 D3 D4 D5 D6 D7/P
**
SP SP
Operation mode 1
ST
D0
D1
D2
D3
D4
D5
D6
D7 A/D
SP
* D7 (bit 7) if parity is not provided and data length is 8 bits P (parity) if parity is provided and data length is 7 bits ** only if SBL-Bit of SCR is set to 1
ST: Start Bit SP: Stop Bit A/D: Address/data selection bit in mode 1 (multiprocessor mode)
Note: If BDS-Bit of the Serial Status Register (SSR) is set to "1", then the bit stream processes as: D7, D6, ... , D1, D0, (P). During Reception both stop bits are detected, if selected. But the Reception data register full (RDRF) flag will go "1" at the first stop bit, but the bus idle flag (RBI of ECCR) goes "1" after the second stop bit if no further start bit is detected. (The second stop bit belongs to "bus activity", although it is just mark level.)
Transmission Operation: If the Transmission Data Register Empty (TDRE) flag bit of the Serial Status Register (SSR) is "1", transmission data is allowed to be written to the Transmission Data Register (TDR). When data is written, the TDRE flag goes "0". If the transmission operation is enabled by the TXE-Bit ("1") of the Serial Control Register (SCR), the Data is written next to the transmission shift register and the transmission starts at the next clock cycle of the serial clock, beginning with the start bit. Thereby the TDRE flag goes "1", so that new data can be written to the TDR. If transmission interrupt is enabled (TIE = 1), the interrupt is simply generated by the TDRE flag. Note, that the initial value of the TDRE flag is "1", so that in this case if TIE is set to "1" an interrupt will occur immediately.
Reception Operation: Reception operation is performed every time it is enabled by the Reception Enable (RXE) flag bit of the SCR. If a start bit is detected, a data frame is received according to the format specified by the SCR. By occurring errors, the corresponding error flags are set (PE, ORE, FRE). However after the reception of the data frame the data is transferred from the serial shift register to the Receive Data Register (RDR) and the Receive Data Register Full (RDRF) flag bit of the SSR is set. The data then has to be read by the CPU. By doing so, the RDRF flag is cleared. If reception interrupt is enabled (RIE = 1), the interrupt is simply generated by the RDRF. Note: Only when the RDRF flag bit is set the Reception Data Register (RDR) contains valid data.
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MB91F364G - Short specification
Stop Bit, Error Detection, and Parity: For transmission, 1 or 2 stop bits can be selected. During reception, if selected, both stop bits are checked, to set the reception bus idle (RBI) flag of the ECCR correctly not until after the second stop bit. In mode 0 parity, overrun, and framing error can detected. In mode 1, overrun and framing error can be detected. Parity is not provided. By setting the Parity Enable (PEN) bit of the Serial Control Register (SCR) the UART provides parity calculation (during transmission) and parity detection and check (during reception) in mode 0 (and mode 2 if the SSM bit of the ECCR is set). Even parity is set, if the P flag bit of the SCR is cleared, odd parity if the flag bit is set.
7.5.2
Operation in Synchronous Mode (Mode 2)
Transfer data format: In the synchronous mode, 8-bit data is transferred with no start or stop bits if the SSM bit of the Extended Communication Control Register (ECCR) is 0. To the data format in mode 2 belongs a special clock signal. The figure below illustrates the data format during a transmission in the synchronous operation mode.
Transmission data writing
Reception data sample edge (ESCR: SCES = 0)
Transmitting and receiving clocks (normal) Transmitting clock (SCDE) Transmission and reception data 0 LSB 1 1 0 1 Data 0 0 1 MSB
Mark level Mark level Mark level
Clock Supply: In clock synchronous mode (I/O extended serial), the number of the transmission and reception bits has to be equal to the number of clock cycles. Note, that if start/stop bits communication is enabled, the number of clock cycles has to match with the quantity for the additional start and stop bit(s). If the internal clock (dedicated reload counter) is selected, the data receiving synchronous clock is generated automatically if data is transmitted. If external clock is selected, be sure, that the transmission side of the Transmission Data Register contains data and then clock cycles for each bit to sent have to be generated and supplied from outside. The mark level ("H") must be retained before transmission starts and after it is complete. Setting the SCDE bit of ECCR delays the transmitting clock signal about 50 ns to make sure, that the transmission data is valid and stable at any falling clock edge. (Necessary, if the receiving device samples the data at rising or falling clock edge).
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MB91F364G - Short specification
If the Serial Clock Edge Select (SCES) bit of the ESCR is set, the UART's clock is inverted and thus samples the reception data at the falling clock edge. In this case be sure, that the serial data is valid at the falling serial clock edge.
Error Detection: If no Start/Stop bits are selected (ECCR: SSM = 0) only overrun errors are detected. Communication: For initialization the synchronous mode following settings have to be done: Braud Rate Generator Registers (BGR0/1): Set the desired reload value for the dedicated Baud Rate Reload Counter Serial Mode Control Register (SMR): MD1, MD0: "10b" (Mode 2) SCKE: "1" for dedicated Baud Rate Reload Counter "0" for external clock input SOE: "1" for transmission; "0" for reception Serial Control Register (SCR): RXE, TXE: one of these flag bit is set to "1" PEN: no parity provided - Value: don't care P, SBL, A/D: no parity, no stop bit(s), no Address/Data selection - Value: don't care CL: automatically fixed to 8-bit data - Value: don't care CRE: "1" (the error flag is cleared for initialization, possible transmission or reception will cut off) Serial Status Register (SSR): BDS: "0" for LSB first, "1" for MSB first RIE: "1" if interrupts are used; "0" if not TIE: "1" if interrupts are used; "0" if not Extended Communication Register (ECCR): SSM: "0" if no start/stop bits are desired (normal); "1" for adding start/stop bits (special) MS: "0" for master mode (UART generates the serial clock); "1" for slave mode (UART receives serial clock from the master device) To start the communication, write data into the Transmission Data Register (TDR). To receive data, disable the Serial Output Enable (SOE) bit of the SMR and write dummy data to TDR. Note: Because of the bidirectional function of the SCK pin, transmission and reception at the same time is not possible!
page 37 of 72
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MB91F364G - Short specification
7.5.3
Operation with LIN Function (mode 3)
The UART can be used either for LIN-Master devices or LIN-Slave devices. For this LIN function a special mode (3) is provided. Setting the UART to mode 3, configure the data format to 8N1-LSB-first format. UART as LIN master: In LIN master mode the master determines the baud rate of the whole sub bus, i. e. the slaves have to synchronize to the master. Therefore nothing special baud rate settings have to be done. Writing a "1" into the LBR bit of the Extended Status/Communication Register (ECCR) generates a 13 - 16 bit times low-level on the SOUT pin, which is the LIN synchronization break and the start of a LIN message. Thereby the TDRE flag of the Serial Status Register (SSR) goes "0" and is reset to "1" after the break, and generates a transmission interrupt for the CPU (if TIE of SSR is "1"). The length of the Synchronization break to be sent can be determined by the LBL1/0 bits of the ESCR as follows:
LBL1 0 0 1 1 LBL0 0 1 0 1 Length of Break 13 Bit times 14 Bit times 15 Bit times 16 Bit times
The Synch Field can be sent as a simple 0x55-Byte after the LIN break. To prevent a transmission interrupt, the 0x55 can be written to the TDR just after writing the "1" to the LBR bit, although the TDRE flag is "0". The internal transmission shifter waits until the LIN break has finished and shifts then the TDR value out. In this case no interrupt is generated after the LIN break and before the start bit. UART as LIN slave: In LIN slave mode the UART has to synchronize to the master's baud rate. If Reception is disabled (RXE = 0) but LIN break Interrupt is enabled (LBIE = 1) the UART will generate an reception interrupt, if a synchronization break of the LIN master is detected, and indicates it with the LBD flag of the ESCR. Writing a "0" to this bit clears the interrupt. The next goal is to analyze the baud rate of the LIN master. The first falling edge of the Synch Field is detected by the UART. The UART signals it then to the Input Capture Unit (ICU) via a rising edge of the internal LSYN connection. The fifth falling edge resets the LSYN signal. The time in which the LSYN signal was "1" is then the actual baud rate of the LIN master multiplied by 8. The figure below shows a typical start of a LIN message frame and the behavior of the UART:
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MB91F364G - Short specification
Serial clock Serial Input (LIN bus) LBD LSYN
(internal connection to ICU) LBR cleared by CPU
Synch break (e. g. 14 Tbit)
Synch field
7.5.4
Direct Access to Serial Bus Operation
The UART provides the ability for the Programmer to access directly to serial input or output pin. The software can always monitor the incoming serial data by reading the SIOP bit of the ESCR. If setting the Serial Output Pin direct access Enable (SOPE) bit of the ESCR the software can force the SOUT pin to a desired value. Note, that this access is only possible, if the transmission shift register is empty (i. e. no transmission activity). In LIN mode this function can be used for "reading back the own transmission" and used for error handling if something is physically wrong with the single-wire LIN-bus. Note: Write the desired value to the SIOP pin before enabling the output pin access, to prevent undesired peaks.
7.5.5
Data Format setting
The INV bit of the Extended Communication Control Register (ECCR) inverts the serial data, if it is set to "1". This means that the signal mode is "return to zero" (RZ). Otherwise the signal mode for SIN and SOT ist "non return to zero" (NRZ, initial value). The following graphic illustrates the two settings for INV: SIN (NRZ) INV = 0 SIN (RZ) INV = 1 SOT (NRZ) INV = 0 SOT (RZ) INV = 1
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
Note, that the INV bit can be set in all operation modes, including LIN mode 3.
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MB91F364G - Short specification
7.5.6
Register / Flag bits summary
In the UART FL84 the settings of the Register bits, which affect the transmission and reception behavior are depending on the current determined mode. Thus, trying to set a senseless value to a flag bit (e. g. Parity enable in LIN mode 3) does not affect the UART behavior. Reading from this pretended wrong set bit returns nevertheless the correct value. The following table illustrates all possible setting for all UART modes:
Stop bit length Byte length A/D bit Bit direction
Mode
Parity none, odd or even none, odd or even -
SCES
SCDE
SSM
INV
0 1 2 (SSM = 0) 2 (SSM = 1) 3 (LIN)
1 or 2
7 or 8
yes LSB or MSB first
yes
yes
0 yes
-
-
1 or 2
8
LSB first
yes
yes
1
1
-
-
-
-
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MB91F364G - Short specification
7.6
UART Interrupts
The UART uses both reception and transmission interrupts. For the following causes an interrupt can be generated: - Receive data is transferred to the Reception Data Register (RDR), or a reception error occurs. - Transmission data is transferred from the Transmission Data Register (TDR) to the transmission shift register. - A LIN-synch break is detected - bus idle is detected The following table shows the interrupt control bits and causes of the interrupt:
Reception/ transmission/ ICU
Interrupt request flag bit RDRF ORE FRE PE
Flag Register SSR SSR SSR SSR ESCR ESCR SSR ICS01 ICS01
Operation mode 0 x x x x x x x x x x x x x 1 x x x 2 x x * * 3 x x x
Interrupt cause receive data is written to RDR Overrun error Framing error Parity error LIN synch break detected no bus activity Empty transmission register 1st falling edge of LIN synch field 5th falling edge of LIN synch field
Interrupt cause enable bit
When Interrupt request flag bit is cleared Receive data is read
SSR / RIE ESCR / LBIE ECCR / BIE SSR / TIE ICS01/ ICE0 ICS01/ ICE0
"1" is written to clear rec. error bit (SSR/CRE) "0" is written to ESCR/LBD Receive data / Send data Transfer data is written disable ICE0 temporary disable ICE0
Reception
LBR TBI & RBI
x x x x x
Transmission Input Capture Unit
TDRE ICP0 ICP0
x = used / supported
* = only available if SSM is set to "1"
7.6.1
Reception Interrupt
If one of the following events occurs in reception mode, the corresponding flag bit of the Serial Status Register (SSR) is set to "1": - Data reception is complete, i. e. the received data was transferred from the serial input shift register to the Reception Data Register (RDR): RDRF - Overrun error, i. e. RDRF = 1 and RDR was not read by the CPU: ORE - Framing error, i. e. A stop bit was expected, but a "0"-bit was received: FRE - Parity error, i. e. a wrong parity bit was detected: PE If at least one of these flag bits above go "1" and the reception interrupt is enabled (SSR: RIE = 1), a reception interrupt request is generated.
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MB91F364G - Short specification
If the Reception Data Register (RDR) is read, the RDRF flag is automatically cleared to "0". Note that this is the only way to reset the RDRF flag. The error flags are cleared to "0", if a "1" is written to the Clear Reception Error (CRE) flag bit of the Serial Control Register (SCR). The RDR contains only valid data if the RDRF flag is "1" and no error bits are set. Note, that the CRE flag is "write only" and by writing a "1" to it, it is internally held to "1" for one CPU clock cycle.
7.6.2
Transmission Interrupt
If transmission data is transferred from the Transmission Data Register (TDR) to the transfer shift register (this happens, if the shift register is empty), the Transmission Data Register Empty (TDRE) flag bit of the Serial Status Register (SSR) is set to "1". In this case an interrupt request is generated, if the Transmission Interrupt Enable (TIE) bit of the SSR was set to "1" before. Note, that the initial value of the TDRE (after hardware or software reset) is "1". So an interrupt is generated immediately then, if the TIE flag is set to "1". Also note, that the only way to reset the TDRE flag is writing data to the RDR.
7.6.3
LIN Synchronization Break Interrupt
This paragraph is only relevant, if the UART operates in mode 0 or 3. If the bus (serial input) goes "0" (dominant) for more than 13 bit times, the LIN Break Detected (LBD) flag bit of the Extended Status/Control Register (ESCR) is set to "1". Note, that in this case after 9 bit times the reception error flags are set to "1", therefore the RIE flag has to set to "0" or the RXE flag has to set to "0", if only a LIN synch break detect is desired. In the other case a reception error interrupt would be generated first, and the interrupt handler routine has then to wait for LBD = 1. The interrupt and the LBD flag are cleared after writing a "1" to the LBD flag. This makes it sure, that the CPU has detected the LIN synch break, because of the following procedure of adjusting the serial clock to the LIN master.
7.6.4
LIN Synchronization Field Edge Detection Interrupts
This paragraph is only relevant, if the UART operates in mode 0 or 3 as a LIN slave. After a LIN break detection the next falling edge of the reception bus is indicated by the UART. Simultaneously the internal LSYN signal (which is connected to the ICU) is set to "1". The LSYN signal is reset to "0" after the fifth falling edge of the LIN Synchronization Field. In both cases the ICU generates an interrupt, if "both edge detection" is enabled. The difference of the ICU counter values is then the serial clock multiplied by 8. Dividing it by 8 results in the new detected and calculated baud rate for the dedicated reload counter (FL85). There is no need to restart the reload counter, because it is automatically reset if a falling edge of a start bit is detected (SEDGE).
7.6.5
Bus Idle Interrupt
If there is no reception activity on the SIN pin, the RBI flag bit of the ECCR goes "1". The TBI flag bit respectively goes "1", when no data is transmitted. If the Bus Idle Interrupt Enable bit (BIE) of the ECCR is set and both bus idle flag bits (TBI and RBI) are "1", an interrupt is generated. Note: The TBI flag goes also "0" if there is no bus activity, but a "0" is written to the SIOP bit, if SOPE is "1".
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MB91F364G - Short specification
7.6.6
Software Reset
In case of malfunction of the UART there is the possibility to reset only the UART instead of resetting the whole MCU. The Software Reset/UART Programmable Clear (UPCL) bit (no. 2) in the SMR provides such function. Writing a "1" into this bit, resets the UART immediately. There is no need to reset this bit to "0", because one clock reset-"high"-level is generated automatically. Note, that possible transmission or reception will cut off. The register values are saved, but the clock of the dedicated reload counter (FL85) is restarted. The programmer should be careful with this function. It is recommended, that any write commands to the UART's SMR should masked with "0xfb" before to prevent accidentally lost of data. An alternative to resetting the UART state without restarting the reload counter (FL85) is to disable the reception (RXE = 0) or transmission (TXE = 0) function temporary. The reception and/or the transmission control circuits will "reset" internally. Another alternative is changing the UART's operation mode temporary. This will have the same effect. To reset the Reception Finite State Machine only, simply write a "1" to the CRE bit of the SCR.
7.7
Clock Synchronization
In asynchronous mode the UART detects a falling edge of a start bit and generates a signal (SEDGE) to restart the baud rate reload counter (FL85). This ensures that the serial data is sampled in the middle of the bit time.
CLKP
SIN (oversampled) SIN to reception shifter SEDGE (internal signal)
Reload Counter Restart
start bit
data bit
Data sampling time
RSCK (reception clock)
clock phase cut off bit time
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MB91F364G - Short specification
7.8
7.8.1
Interrupt Generation and Flag Set Timing
Reception Interrupt and Flags
Generally a reception interrupt is generated, if the received data is complete (RDRF = 1) or reception errors have occurred (PE, ORE, or FRE) and the Reception Interrupt Enable (RIE) flag bit of the Serial Status Register (SSR) was set to "1". These interrupts are generated if the first stop bit is detected in mode 0 or 1 (except parity error), or the last data bit was read in mode 2. Note: If a reception error has occurred, the Reception Data Register (RDR) contains invalid data in each mode.
Receive data (mode 0/3) Receive data (mode 1) Receive data (mode 2) PE*, FRE RDRF ORE** (if RDRF = "1")
ST ST
D0 D0 D0
D1 D1 D1
D2 D2 D2
.... .... ....
D5 D6 D4
D6 D7 D5
D7/P A/D D6
SP SP D7
ST ST D0
reception interrupt occurs * The PE flag cannot be used in mode 1 or 3 ST: Start Bit SP: Stop Bit A/D: Mode 1 (multi processor) address/data selecti
Note: The example above shows not all possible reception options for mode 0 and 3. Here it is: "7p1" and "8N1" (p = "E" or "O"). **ORE only occurs, if the reception data is not read by the CPU (RDRF = 1) and another data frame is read:
Receive data RDRF ORE
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MB91F364G - Short specification
7.8.2
Transmission Interrupt and Flags
A transmission interrupt is generated, when the next data to be send is ready to be written to the Transmission Data Register (TDR), i. e. the TDR is empty, and the transmission interrupt is enabled by setting the Transmission Interrupt Enable (TIE) bit of the Serial Status Register (SSR) to "1". The Transmission Data Register Empty (TDRE) flag bit of the SSR indicates an empty TDR. Because the TDRE bit is "read only", it only can cleared by writing data into the TDR. The following figure demonstrates the transmission operation and flag set timing for the three modes of the UART:
transmission interrupt occurs Mode 0, 1 or 3: write to TDR TDRE serial output
transmission interrupt occurs
ST D0 D1 D2 D3 D4 D5 D6 D7
P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP A/D A/D
transmission interrupt occurs Mode 2: write to TDR TDRE serial output
ST: Start bit
transmission interrupt occurs
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4
D0 ... D7: data bits
P: Parity
SP: Stop bit
A/D: Address/data selection bit (mode1)
Note: The example above shows not all possible transmission options for mode 0. Here it is: "8p1" (p = "E" or "O"). Parity is not provided in mode 3.
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MB91F364G - Short specification
7.8.3
LIN Synch Break Detection Interrupt and Flags
If a LIN synchronization break is detected in the slave mode, the LIN Break Detected (LBD) Flag of the ESCR is set to "1". This causes an interrupt, if the LIN Break Interrupt Enable (LBIE) flag bit is set.
Serial clock 0 12 3 4 cycle # Receive data
5 6 7 8 9 10 11 12 13 14 15
FRE (RXE = 1) LBD (RXE = 0) Reception interrupt occurs, if RXE = 1 Reception interrupt occurs, if RXE = 0
The figure above demonstrates the LIN synch break detection and flag set timing. Note, that if reception is enabled (RXE = 1) and reception interrupt is enabled (RIE = 1) the Reception Data Framing Error (FRE) flag bit of the SSR will cause an reception interrupt 5 bit times ("8N1") earlier than the LIN break interrupt, so it is recommended to turn off RXE, if a LIN break is expected. LBD is only supported in operation mode 0 and 3.
7.8.4
LIN Synch Field Detection Interrupt and Flags
After a LIN synch break detection the next falling edge on the serial input (SIN) sets the LSYN signal, which is internally connected to the Input Capture Unit (ICU). The fifth falling edge resets the LSYN signal. Therefore the ICU has to set to "both edge detection". The value of the ICU counter register after the first Interrupt has to be stored. The value after the second interrupt minus the first value is then the serial clock time multiplied by 8.
Synch Break Receive data LSYN
(to ICU)
Synch Field
Identifier
IRQ from ICU Interrupt cleared by CPU
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MB91F364G - Short specification
7.8.5
Bus Idle Interrupt and Flags
If both the serial input shift register and the serial output register are empty a bus idle interrupt is generated, if the Bus Idle Interrupt Enable (BIE) bit of the ECCR is set. The following figure illustrates the bus idle interrupt generation and the flag set timing:
Transmission data Reception data TBI RBI IRQ
: Start bit
: Stop bit
: Data bit
Note, the RBI flag goes also "1" if there is reception activity (reception bus is "0") but reception is disabled (RXE = 0). This is also valid if transmission is disabled (TXE = 0), but SOPE is "1" and writing "0" to SIOP.
7.9
7.9.1
Special features
Sampling Clock Edge Selection and clock delay
The Sampling Clock Edge Selection bit (SCES) of the ESCR determine in mode 2 the time when a reception bit is sampled to the reception shift register. This bit also inverts the generated clock signal, if the UART is in master mode 2. Setting the SCDE bit of the ECCR delays the clock signal for approx. 40 - 62 ns (depending on the MCU clock speed). The following figure illustrates this:
page 47 of 72
Fujitsu, EMDC
MB91F364G - Short specification
Serial Clock Signal (SCES = 0, SCDE = 0)
Serial Clock Signal (SCES = 1, SCDE =0)
Serial Clock Signal (SCES = 0, SCDE = 1)
Serial Clock Signal (SCES = 1, SCDE =1)
Delay
Data bits (here: LSB first) or
D0
D1
D2
D3
D4
D5
D6
D7
: Sampling clock edge
=
1
= MCU clock cycle
7.9.2
Synchronous Start-Stop-Bit-Mode
In synchronous operation mode 2 the SSM bit of the ECCR adds start-, stop-, and (if enabled) a parity bit to the data stream like in mode 0. Therefore all additional bits are clocked too:
reception or transmission clock (SCES = 0, CCO = 0): reception or transmission clock (SCES = 1, CCO = 0): data stream (SSM = 1) (here: no parity, 1 stop bit)
ST SP
mark level
mark level
data frame
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MB91F364G - Short specification
7.9.3
Continuous serial clock output enable
If the CCO bit of the ESCR is set and the UART is in mode 2, the serial clock is output directly to the SCK pin, synchronized to the shifter clocks. This is useful when using start stop bits in synchronous mode.
reception or transmission clock (SCES = 0, CCO = 1): reception or transmission clock (SCES = 1, CCO = 1): data stream (SSM = 1) (here: no parity, 1 stop bit)
ST SP
data frame
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Fujitsu, EMDC
MB91F364G - Short specification
7.10
7.10.1
LIN Communication Function
UART as Master device
The following flowchart example demonstrate how to process with a LIN bus system, if the UART acts as the bus master device:
START
Initialization: Set Operat. mode 3 (8N1 data format)
TIE = 0, RIE = 0
Send Message? N Y
Send Synch Break: write "1" to ECCR: LBR; TIE = 1; Send Synch Field: TDR = 0x55
Send Sleep Mode TDR = 0x80 TIE = 0
Wake up from CPU? TDRE = 1 Transm. Interrupt N
Y
Send Wake up signal RIE = 0 TIE = 1 TDR = 0x80
RIE = 1 Send Sleep Mode?Y N N Send Identify Field: TDR = Id 0x00, 0x80, or 0xC0 received? Y RIE = 0
Write to slave? N
Y
TIE = 1 Write data to slave TIE = 0
Errors occurred? N Y
TIE = 0 RIE = 1 Read data from slave RIE = 0
Error Handler
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MB91F364G - Short specification
7.10.2
UART as slave device
The following flowchart example demonstrate how to process with a LIN bus system, if the UART acts as a slave device:
START A B
Initialization: Set Operat. mode 3 (8N1 data format) C RIE = 0; LBIE = 1; RXE = 0 Errors occurred? Y N E
Slave address N match? Y
C
waiting (slave action) LBD = 1 LIN break interrupt
Master wants to N send data? Y
Awaiting message from LIN master. Write "0" to LBD to clear interrupt Enable ICU interrupt (both edges) 0x80 received? (sleep mode) Y N waiting (slave action) ICU Interrupt Read ICU value and store it. Clear Interrupt. B S
Receive data + checksum
RIE = 0 TIE = 1 Calculate checksum Send data
(on next page) TIE = 0
C Errors occurred? Y N
waiting (slave action) ICU Interrupt Read ICU value. Calculate new baud rate. Set it to Reload Counter (FL85). Clear Interrupt.
C
E
Error handler
C Receive identifier RIE = 1; RXE = 1
A
continued next page
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continuation from previous page
S
Wake up from CPU? N
Y
Send Wake up signal RIE = 0 TIE = 1 TDR = 0x80
TIE = 0 RIE = 1
N
0x00, 0x80, or 0xC0 received?
Y
RIE = 0
C
7.11 *
-- -- -- --
Summary of the Changes to previous UARTs
Special LIN features with Interrupt Generation Direct Access to the Serial Input / Output Pins (SIN, SOUT) Reception Sampling Clock Edge Selection (SCES) (Clock inversion) Continuos Serial Clock Output for mode 2 with start/stop bits
Additional Extended Status/Control Register (ESCR), which provides:
*
Additional Extended Communication Control Register (ECCR), which provides: -- -- -- -- -- Reception Sampling Clock Edge Selection (SCES) (Clock inversion) SPI-Mode bit (SCDE; Delaying the Serial Clock Output) Start-Stop-Bit-Option in synchronous mode (SSM) Master and Slave communication in synchronous mode 2 (MS) Bus idle interrupt generation with two separate flag bits for Transmission Idle and Reception Idle
*
Changes in the Serial Mode Register (SMR): -- A new mode (3) is added for LIN-slave function and for fixing the data format to "8N1", LSB first -- Clock Select bits were removed and replaced with control bits for the reload counter (see extra specification for details)
* *
Communication Prescaler Control Register (CPCR) was removed and replaced with two registers for the reload counter (BGR1, BGR0) Master and Slave function in Multiprocessor Mode (mode 1) is now provided
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MB91F364G - Short specification
*
Flag bits which belong to transmission/reception format always return "correct" values. For example: If the programmer tries to set the Parity flag in mode 3 (LIN), the PEN flag nevertheless will return a "0" Exceptions: In mode 1 the parity flag is always set (used to send / receive the AD bit). In mode 2 the parity flag can be set but is sent or received only if SSM is "1"
* * * * *
Now also the second stop bit is checked during reception, if SBL is "1" UART provides a fife time oversampling in asynchronous mode UART generates a SEDGE (Start bit falling Edge detection) signal for the dedicated Baud Rate Generator to synchronize the Reception Clock to the incoming data UART provides hence version 2.0 NRZ and RZ signal mode. RMW functionallity of the AD bit provided for CPU bit manipulation instructions.
This UART is not software compatible to older UART modules
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MB91F364G - Short specification
8
8.1
Electrical specification
Absolute Maximum Ratings
see MB91360 Hardware Manual
8.2
Operating Conditions
Symbol a VDD VDDC min. -40 4.75 3.1 typ. max. 85 5.25 3.5 Unit C V V Condition
Parameter Operating temperature Supply voltage - Digital supply - Core supply
5 3.3
int. regulator used int. regulator not used (under investigation!)
For the other parameters see MB91360 Hardware Manual
8.3
Clock Settings
The maximum allowed core clock (CLKB) frequency setting is 32 MHz. For settings of the others clocks see MB91360 Hardware Manual.
8.4
T.B.D.
Clock Modulator Settings
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MB91F364G - Short specification
9
Package
The package FPT-120P-M21 will be used for MB91F364G.
The thermal resistance of this package is 30 degr. C/W when used on a muli-layer board with separate power and ground planes.
Thermal resistance [degr. C/W]
theta-ja (junction to ambient) 0 m/s 30 1 m/s 27 3 m/s 25
theta-jc (junction to case)
5
The maximum allowed ambient temperature is 85 degr. C, the maximum allowed junction temperature is 125 degr.C. Under these conditions a maximum power consumption of (125 degr. C - 85 degr. C) / 30 C/W = 1.33 W is allowed. The user must make sure that the maximum ambient temperature is not exceeded. For other details about the package see Fujitsu Semiconductor Package Data Book.
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MB91F364G - Short specification
Appendix A I/O Map
Version 1.4, 2000/03/13
Table A lists the addresses for the registers used by the internal peripheral functions of the MB91FV360G.
* How to Read the I/O Map
Register Address +0 000014H PDRG [R/W]
XXXXXXXX
+1 PDRH [R/W]
XXXXXXXX
+2 PDRI [R/W]
----XXXX
+3 --
Internal peripheral Port data register
Read/write attribute Register initial value after a reset (bit initial values) "1": initial value "1", "0": initial value "0", "x": initial value "X" (indeterminate), "--" indicates non-existent bits Register name (The register in column 1 is at location 4n, the register in column 2 at 4n+1, and so on.) Location of far left of register (+0). +1, +2, and +3 each increment the location by one. When performing word access, the register in column 1 is placed at the MSB end of the data. Precautions: * Do not use RMW instructions on registers containing write-only (W) bits.
RMW instructions(RMW:read-modify-write) AND Rj, @Ri OR Rj, @Ri EOR Rj, @Ri ANDH Rj, @Ri ORH Rj, @Ri EORH Rj, @Ri ANDB Rj, @Ri ORB Rj, @Ri EORB Rj, @Ri BANDL #u4, @Ri BORL #u4, @Ri BEORL #u4, @Ri BANDH #u4, @Ri BORH #u4, @Ri BEORH #u4, @Ri
*
The data in reserved areas and areas marked "" is indeterminate. Do not use those areas !
Register Address +0
000000H 00000CH
Block +1
Reserved
+2
+3
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MB91F364G - Short specification
Register Address +0
000010H 000014H 000018H 00001CH 000020H | 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H 000058H 00005CH 000060H 000064H 000068H 00006CH 000080H 000084H 000088H SMCS0 [R/W] 00000010 - - - - 00-0 EIRR [R/W] 00000000 DICR [R/W] -------0 ENIR [R/W] 00000000 HRCL [R/W] 0 - - 11111 ELVR [R/W] 00000000 00000000 CLKR2 [R/W] - - - - - 000 reserved PDRG [R/W] XXXXXXXX PDRK [R/W] XXXXXXXX PDRO [R/W] XXXXXXXX PDRS [R/W] XXXXXXXX
Block +1
PDRH [R/W] XXXXXXXX PDRL [R/W] XXXXXXXX PDRP [R/W] - - XXXXX PDRT --XXXXXX Reserved
+2
PDRI [R/W] X---X--PDRM [R/W] - - - - XXXX PDRQ [R/W] - - XXXXX
+3
PDRJ [R/W] XXXXXXXX PDRN [R/W] - - XXXXXX PDRR [R/W] XXXXXXXX R-bus Port Data Register
Ext int/NMI DLYI/I-unit RTC Reload Timer 0
TMRLR0 [W] XXXXXXXX XXXXXXXX ________ TMRLR1 [W] XXXXXXXX XXXXXXXX ________ TMRLR2 [W] XXXXXXXX XXXXXXXX ________ SSR0 [R/W] 00001 - 00 ULS0 [R/W] - - - - 0000 SIDR0 [R/W] XXXXXXXX --------
TMR0 [R] XXXXXXXX XXXXXXXX TMCSR0 [R/W] - - - - 0000 - - - 00000 TMR1 [R] XXXXXXXX XXXXXXXX TMCSR1 [R/W] - - - - 0000 - - - 00000 TMR2 [R] XXXXXXXX XXXXXXXX TMCSR2 [R/W] - - - - 0000 - - - 00000 SCR0 [R/W] 00000100 -------DRCL0 [W] -------Reserved SMR0 [R/W] 00 - - 0 - 0 -------UTIMC0 [R/W] 0 - - - 0 - 01
Reload Timer 1
Reload Timer 2
UART0
UTIM0/UTIMR0 [R/W] 00000000 00000000
U-TIMER 0
SES0 [R/W] - - - - - - 00 Reserved
SDR0 [R/W] 00000000
SIO 0
page 57 of 72
Fujitsu, EMDC
MB91F364G - Short specification
Register Address +0 +1 +2 +3 Block
00008CH 000090H 000098H 00009CH 0000A0H 0000A4H 0000A8H 0000ACH 0000B0H 0000B4H 0000B8H 0000BCH 0000C0H 0000C4H 0000C8H
CDCR0 [R/W] 0 - - - 1111
Reserved Reserved
Reserved
Reserved
SIO 0 Prescaler
ADMD [R/W,W] - - - X0000
ADCH [R/W] 00000000
ADCS [R/W,W] 0000 - - 00 ADBL [R/W] -------0 DADR0 [R/W] - - - - - - XX XXXXXXXX DDBL [R/W] -------0 IOTDBL1 [R/W] - - - - - 000 ICS23 [R/W] 00000000
A/D Converter
ADCD [R/W] 000000XX XXXXXXXX DACR [R/W] - - - - - 000 DADR1 [R/W] - - - - - - XX XXXXXXXX IOTDBL0 [R/W] - - - - - 000 ICS01 [R/W] 00000000
DAC
Input Capture 0,1,2,3
IPCP0 [R] XXXXXXXX XXXXXXXX IPCP2 [R] XXXXXXXX XXXXXXXX OCS01 [R/W] - - - 0 - - 00 0000 - - 00 OCCP0 [R/W] XXXXXXXX XXXXXXXX OCCP2 [R/W] XXXXXXXX XXXXXXXX
IPCP1 [R] XXXXXXXX XXXXXXXX IPCP3 [R] XXXXXXXX XXXXXXXX OCS23 [R/W] - - - 0 - - 00 0000 - - 00 OCCP1 [R/W] XXXXXXXX XXXXXXXX OCCP3 [R/W] XXXXXXXX XXXXXXXX Reserved Output Compare 0,1,2.3
TCDT0 [R/W] XXXXXXXX XXXXXXXX TCDT1 [R/W] XXXXXXXX XXXXXXXX Reserved
________
TCCS0 [R/W] - 0000000 TCCS1 [R/W] - 0000000
Free Running Counter 0 for ICU/OCU Free Running Counter 1 for ICU/OCU
0000CCH
________
0000D0H 0000F0H
page 58 of 72
Fujitsu, EMDC
MB91F364G - Short specification
Register Address +0
0000F4H 0000F8H 0000FCH 000100H 000114H 000118H 00011CH 000120H 000124H 000128H 00012CH 000130H 000134H 000138H 00013CH 000140H 000160H PTMR0 [R] 11111111 11111111 PDUT0 [W] XXXXXXXX XXXXXXXX PTMR1 [R] 11111111 11111111 PDUT1 [W] XXXXXXXX XXXXXXXX PTMR2 [R] 11111111 11111111 PDUT2 [W] XXXXXXXX XXXXXXXX PTMR3 [R] 11111111 11111111 PDUT3 [W] XXXXXXXX XXXXXXXX GCN10 [R/W] 00110010 00010000 WTHR [R/W] - - - 00000
Block +1
WTDBL [R/W] -------0
+2
+3
Real Time Clock (WatchTimer)
WTCR [R/W] 00000000 000 - 0000
WTBR [R/W] - - XXXXXX XXXXXXXX XXXXXXXX WTMR [R/W] - - 000000 WTSR [R/W] - - 000000
Reserved
PDBL0 [R/W] - - - 00000 Reserved
GCN20 [R/W] - - - - 0000
PWM Control 0
PCSR0 [W] XXXXXXXX XXXXXXXX PCNH0 [R/W] 0000000 PCNL0 [R/W] 000000 - 0
PWM0
PCSR1 [W] XXXXXXXX XXXXXXXX PCNH1 [R/W] 0000000 PCNL1 [R/W] 000000 - 0
PWM1
PCSR2 [W] XXXXXXXX XXXXXXXX PCNH2 [R/W] 0000000 PCNL2 [R/W] 000000 - 0
PWM2
PCSR3 [W] XXXXXXXX XXXXXXXX PCNH3 [R/W] 0000000 Reserved PCNL3 [R/W] 000000 - 0
PWM3
page 59 of 72
Fujitsu, EMDC
MB91F364G - Short specification
Register Address +0
000164H 000168H 00016CH 000170H 000174H 000178H 00017CH 000180H 000184H 000188H 00018CH 000190H 000194H 000198H 00019CH 0001A0H 0001A4H 0001A8H | 0001F8H 0001FCH
IBCR2 [R/W]
Block +1 +2
CMPR [R/W] ----1001 1---0001 CMLS1 [R/W] 01110111 1111111 CMLS3 [R/W] 01110111 1111111 CMLT1 [R/W] 11110100 00000010 CMLT3 [R/W] -----100 00000010 CMTS [R/W] --000001 01111111 Reserved
+3
Clock Modulation
CMCR [R/W] 11111111 0000000 CMLS0 [R/W] 01110111 1111111 CMLS2 [R/W] 01110111 1111111 CMLT0 [R/W] -----100 00000010 CMLT2 [R/W] -----100 00000010 CMAC [R/W] 11111111 1111111
00000000
ITMKH [R/W]
IBSR2 [R] 00000000 ITMKL [R/W]
ITBAH [R/W]
- - - - - - 00
ISMK [R/W]
ITBAL [R/W] 00000000
ISBA [R/W]
I2C
00 - - - - 11
IDARH [-] 00000000
11111111
IDAR2 [R/W]
01111111
ICCR2 [R/W]
- 0000000 IDBL2 [R/W] -------0 Calibration Unit of 32kHz oscillator
00000000
- 0011111
CUCR [R/W] -------- ---0--00 CUTR1 [R] -------- 00000000 SCR5 [R/W,W] 00000000 ESCR5 [R/W} 00000X00 SCR6 [R/W,W] 00000000 ESCR6 [R/W} 00000X00 SMR5 [R/W,W] 00000000
ECCR5 [R/W,R,W]
CUTD [R/W] 10000000 00000000 CUTR2 [R] 00000000 00000000 SSR5 [R/W,R] 00001000 BGR15 [R/W] -0000000 SSR6 [R/W,R] 00001000 BGR16 [R/W] -0000000
RDR5/TDR5 [R/W]
LIN UART0
00000000 BGR05 [R/W] 00000000
RDR6/TDR6 [R/W]
-00000XX SMR6 [R/W,W] 00000000
ECCR6 [R/W,R,W]
LIN UART1
00000000 BGR06 [R/W] 00000000
-00000XX
Reserved
F362MD [R/W] 00000000
SFR [R/W] -------0 SFR_BDEN
F362 Mode, Special Function Register (BDSU enable)
page 60 of 72
Fujitsu, EMDC
MB91F364G - Short specification
Register Address +0
000200H | 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H 000404H 000408H 00040CH 000410H 000414H 000418H 00041CH 000420H | 00043CH DDRG [R/W] 00000000 DDRK [R/W] 00000000 DDRO [R/W] 00000000 DDRS [R/W] 00000000 PFRG [R/W] 00000000 PFRK [R/W] 00000000 PFRO [R/W] 00000000 PFRS [R/W] 00000000
Block +1
________
+2
+3
Reserved
BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDRH [R/W] 00000000 DDRL [R/W] 00000000 DDRP [R/W] ----0000 DDRT [R7W] --000000 PFRH [R/W] 00000000 PFRL [R/W] 00000000 PFRP [R/W] 00000000 PFRT [R/W] --000000 ________ PFRI [R/W] ----0--PFRM [R/W] ----0000 PFRQ [R/W] --000000 PFRJ [R/W] 00000000 PFRN [R/W] --000000 PFRR [R/W] 00000000 DDRI [R/W] ----0--DDRM [R/W] ----0000 DDRQ [R/W] --000000 DDRJ [R/W] 00000000 DDRN [R/W] --000000 DDRR [R/W] 00000000
Bit Search Module
R-bus Port Direction Register
R-bus Port Function Register
Reserved
page 61 of 72
Fujitsu, EMDC
MB91F364G - Short specification
Register Address +0
000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH 000470H | 00047CH 000480H 000484H 000488H | 00063CH RSRR [R/W] 10000000 CLKR [R/W] 00000000 ICR00 [R/W] ---11111 ICR04 [R/W] ---11111 ICR08 [R/W] ---11111 ICR12 [R/W] ---11111 ICR16 [R/W] ---11111 ICR20 [R/W] ---11111 ICR24 [R/W] ---11111 ICR28 [R/W] ---11111 ICR32 [R/W] ---11111 ICR36 [R/W] ---11111 ICR40 [R/W] ---11111 ICR44 [R/W] ---11111
Block +1
ICR01 [R/W] ---11111 ICR05 [R/W] ---11111 ICR09 [R/W] ---11111 ICR13 [R/W] ---11111 ICR17 [R/W] ---11111 ICR21 [R/W] ---11111 ICR25 [R/W] ---11111 ICR29 [R/W] ---11111 ICR33 [R/W] ---11111 ICR37 [R/W] ---11111 ICR41 [R/W] ---11111 ICR45 [R/W] ---11111
+2
ICR02 [R/W] ---11111 ICR06 [R/W] ---11111 ICR10 [R/W] ---11111 ICR14 [R/W] ---11111 ICR18 [R/W] ---11111 ICR22 [R/W] ---11111 ICR26 [R/W] ---11111 ICR30 [R/W] ---11111 ICR34 [R/W] ---11111 ICR38 [R/W] ---11111 ICR42 [R/W] ---11111 ICR46 [R/W] ---11111
+3
ICR03 [R/W] ---11111 ICR07 [R/W] ---11111 ICR11 [R/W] ---11111 ICR15 [R/W] ---11111 ICR19 [R/W] ---11111 ICR23 [R/W] ---11111 ICR27 [R/W] ---11111 ICR31 [R/W] ---11111 ICR35 [R/W] ---11111 ICR39 [R/W] ---11111 ICR43 [R/W] ---11111 ICR47 [R/W] ---11111 Interrupt Control unit
________
STCR [R/W] 00110011 WPR [W] XXXXXXXX
TBCR [R/W] X0000X00 DIVR0 [R/W] 00000011
CTBR [W] XXXXXXXX DIVR1 [R/W] 00000000
Clock Control unit
________
Reserved
page 62 of 72
Fujitsu, EMDC
MB91F364G - Short specification
Register Address +0
000640H 000644H 000648H 00064CH 000650H 000654H 000658H 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H | 0007F8H 0007FCH ________ CHE 11111111
Block +1 +2 +3
T-unit Note: only use registers required for the controlling of the CS7X area and to avoid overlapping CSnX areas, other registers have no funcion ASR0 [W] 00000000 00000000 ASR1 [W] 00000000 00000000 ASR2 [W] 00000000 00000000 ASR3 [W] 00000000 00000000 ASR4 [W] 00000000 00000000 ASR5 [W] 00000000 00000000 ASR6 [W] 00000000 00000000 ASR7 [W] 00000000 00000000 AMD0 [R/W] -00XX111 AMD4 [R/W] --XXXXXX CSE 11000011 ________ ________ ________ AMD1 [R/W] -XXXXXXX AMD5 [R/W] --XXXXXX ________ AMR0 [W] 11111000 11111111 AMR1 [W] 00000000 00000000 AMR2 [W] 00000000 00000000 AMR3 [W] 00000000 00000000 AMR4 [W] 00000000 00000000 AMR5 [W] 00000000 00000000 AMR6 [W] 00000000 00000000 AMR7 [W] 00000000 00000000 AMD2 [R/W] --XXXXXX AMD6 [R/W] -XXXXXXX ________ AMD3 [R/W] --XXXXXX AMD7 [R/W] -XXXXXXX ________ ________ ________ Reserved
MODR [W] XXXXXXXX
________
________
Mode Register
page 63 of 72
Fujitsu, EMDC
MB91F364G - Short specification
Register Address +0
000800H 000804H 000808H 00080CH 000810H 000814H 000818H 00081CH 000820H 000824H 000828H 00082CH 000830H 000834H 000840H | 006FFCH 007000H 007004H FMCS [R/W] 0110X000 FMWT [R/W] --010011 ________ ________
Block +1 +2 +3
BDSU
BCTRL [R/W] 00000000 -0000000 00000000 00000000 BSTAT [R/W] 00000000 1---0000 ---------------
BIA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BIA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BIA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BIA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BIAM0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BIAM1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BOA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BOA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BOAM [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BDT0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BDT1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BDTM [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reserved
________ ________
________ ________
Flash Memory Control Register
page 64 of 72
Fujitsu, EMDC
MB91F364G - Short specification
Register Address +0
007008H | 03CFFCH 03D000H | 03FFFCH 040000H | 040FFCH 041000H | 0FEFFC 050000H | 0507FCH 050800H | 0BFFFCH 0C0000H | 0DFFFC 0E0000H | 0EFFFC 0F0000H | 0F3FFCH 0F4000H | 0F7FFCH 0F8000H | 0FFFF4H 0FFFF8H 0FFFFCH Sector 0 64 KB ________ reserved ________ Reserved
Block +1
________
+2
+3
Reserved
User RAM 12 kB (D-Bus) Fast RAM 4 kB (F-Bus)
Boot ROM 2 kB (F-Bus)
Sector 5 64 KB
Flash Memory 256 K on F-Bus
Sector 1 32 KB
Sector 6 32 KB
Sector 2 8 KB
Sector 7 8 KB
Sector 3 8 KB
Sector 8 8 KB
Sector 4 16 KB
Sector 9 16 KB
FMV [R] 06 00 00 00H FRV [R] 00 05 00 00H
Fixed Reset/Mode Vector
Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown above will be read.
page 65 of 72
Fujitsu, EMDC
MB91F364G - Short specification
Register Address +0
100000H 100004H 100008H 10000CH 100010H 100014H 100018H 10001CH 100020H 100024H 100028H 10002CH | 100048H 10004CH 100050H 100054H 100058H 10005CH 100060H 100064H
Block +1 +2 +3
CAN 0 Remark: Address range for CAN 0 to CAN 3 depends on chip select range. Mentioned addresses are default values, determined by boot ROM contents. BVALR0 [R/W] 00000000 00000000 TCANR0 [W] 00000000 00000000 RCR0 [R/W] 00000000 00000000 ROVRR0 [R/W] 00000000 00000000 CSR0 [R/W] 00000000 00000001 RTEC0 [R] 00000000 00000000 IDER0 [R/W] XXXXXXXX XXXXXXXX RFWTR0 [R/W] XXXXXXXX XXXXXXXX TREQR0 [R/W] 00000000 00000000 TCR0 [R/W] 00000000 00000000 RRTRR0 [R/W] 00000000 00000000 RIER0 [R/W] 00000000 00000000 LEIR0 [R/W] 000-0000 BTR0 [R/W] -1111111 11111111 TRTRR0 [R/W] 00000000 00000000 TIER0 [R/W] 00000000 00000000
AMSR0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX AMR00 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX AMR10 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX GENERAL PURPOSE RAM [R/W]
IDR00 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR10 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR20 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR30 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR40 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR50 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR60 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX
page 66 of 72
Fujitsu, EMDC
MB91F364G - Short specification
Register Address +0
100068H 10006CH 100070H 100074H 100078H 10007CH 100080H 100084H 100088H 10008CH 100090H 100094H 100098H 10009CH 1000A0H 1000A4H 1000A8H 1000ACH
Block +1 +2 +3
CAN 0 IDR70 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR80 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR90 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR100 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR110 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR120 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR130 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR140 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR150 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX DLCR00 [R/W] -------- ----XXXX DLCR20 [R/W] -------- ----XXXX DLCR40 [R/W] -------- ----XXXX DLCR60 [R/W] -------- ----XXXX DLCR80 [R/W] -------- ----XXXX DLCR100 [R/W] -------- ----XXXX DLCR120 [R/W] -------- ----XXXX DLCR140 [R/W] -------- ----XXXX DLCR10 [R/W] -------- ----XXXX DLCR30 [R/W] -------- ----XXXX DLCR50 [R/W] -------- ----XXXX DLCR70 [R/W] -------- ----XXXX DLCR90 [R/W] -------- ----XXXX DLCR110 [R/W] -------- ----XXXX DLCR130 [R/W] -------- ----XXXX DLCR150 [R/W] -------- ----XXXX
DTR00 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR10 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1000B4H
page 67 of 72
Fujitsu, EMDC
MB91F364G - Short specification
Register Address +0
1000BCH
Block +1 +2 +3
CAN 0 DTR20 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR30 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR40 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR50 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR60 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR70 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR80 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR90 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR100 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR110 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR120 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR130 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR140 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR150 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CREG0 [R/W] 00000000 00000110
1000C4H
1000CCH
1000D4H
1000DCH
1000E4H
1000ECH
1000F4H
1000FCH
100104H
10010CH
100114H
10011CH
100124H
10012CH
page 68 of 72
Fujitsu, EMDC
MB91F364G - Short specification
Appendix B Interrupt Vectors
This appendix lists the interrupt vector table. The interrupt vector table lists the interrupt vectors and interrupt control registers assigned to each MB91360 interrupt. MB91F364G has no DMA controller. Therefore, the RN column stays empty.
Interrupt
Interrupt number Decimal Hexadecimal 00 01 02 03 04 05 06 07
Interrupt level*1 Setting Register Register address -
Interrupt vector*2 Offset 0x3FC 0x3F8 0x3F4 0x3F0 0x3EC 0x3E8 0x3E4 0x3E0 Default Vector address 0x000FFFFC 0x000FFFF8 0x000FFFF4 0x000FFFF0 0x000FFFEC 0x000FFFE8 0x000FFFE4 0x000FFFE0 RN
Reset Mode vector System reserved System reserved System reserved System reserved System reserved Co-processor fault trap *4 Co-processor error trap *4 INTE instruction *4 Instruction break exception *4 Operand break trap *4 Step trace trap *4 NMI interrupt(tool)*4 Undefined instruction exception NMI request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3
0 1 2 3 4 5 6 7
8
08
-
-
0x3DC
0x000FFFDC
9 10
09 0A
-
-
0x3D8 0x3D4
0x000FFFD8 0x000FFFD4
11 12 13 14 15 16 17 18 19
0B 0C 0D 0E 0F 10 11 12 13
-
FH fixed
0x3D0 0x3CC 0x3C8 0x3C4 0x3C0 0x3BC 0x3B8 0x3B4 0x3B0
0x000FFFD0 0x000FFFCC 0x000FFFC8 0x000FFFC4 0x000FFFC0 0x000FFFBC 0x000FFFB8 0x000FFFB4 0x000FFFB0
ICR00 ICR01 ICR02 ICR03
0x440 0x441 0x442 0x443
page 69 of 72
Fujitsu, EMDC
MB91F364G - Short specification
External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 Reload Timer 0 Reload Timer 1 Reload Timer 2 CAN 0 RX CAN 0 TX/NS Not used on MB91F364G
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32
ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34
0x444 0x445 0x446 0x447 0x448 0x449 0x44A 0x44B 0x44C 0x44D 0x44E 0x44F 0x450 0x451 0x452 0x453 0x454 0x455 0x456 0x457 0x458 0x459 0x45A 0x45B 0x45C 0x45D 0x45E 0x45F 0x460 0x461 0x462
0x3AC 0x3A8 0x3A4 0x3A0 0x39C 0x398 0x394 0x390 0x38C 0x388 0x384 0x380 0x37C 0x378 0x374 0x370 0x36C 0x368 0x364 0x360 0x35C 0x358 0x354 0x350 0x34C 0x348 0x344 0x340 0x33C 0x338 0x334
0x000FFFAC 0x000FFFA8 0x000FFFA4 0x000FFFA0 0x000FFF9C 0x000FFF98 0x000FFF94 0x000FFF90 0x000FFF8C 0x000FFF88 0x000FFF84 0x000FFF80 0x000FFF7C 0x000FFF78 0x000FFF74 0x000FFF70 0x000FFF6C 0x000FFF68 0x000FFF64 0x000FFF60 0x000FFF5C 0x000FFF58 0x000FFF54 0x000FFF50 0x000FFF4C 0x000FFF48 0x000FFF44 0x000FFF40 0x000FFF3C 0x000FFF38 0x000FFF34
PPG 0/1 PPG 2/3 Not used on MB91F364G
35 36 37 38 39 40 41
ICU 0/1 OCU 0/1 ICU 2/3 OCU 2/3 ADC Timebase Overflow Free Running Counter 0 Free Running Counter 1 SIO 0
42 43 44 45 46 47 48 49 50
page 70 of 72
Fujitsu, EMDC
MB91F364G - Short specification
Not used on MB91F364G UART 0 RX UART 0 TX LIN UART 0 RX LIN UART 0 TX LIN UART 1 RX LIN UART 1 TX I2C Not used on MB91F364G RTC (Watchtimer) / Calibration Unit Not used on MB91F364G Delayed interrupt activation bit System reserved *3 System reserved *3 Security vector System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by the INT instruction.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255
33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF
ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 -
0x463 0x464 0x465 0x466 0x467 0x468 0x469 0x46A 0x46B 0x46C 0x46D 0x46E 0x46F -
0x330 0x32C 0x328 0x324 0x320 0x31C 0x318 0x314 0x310 0x30C 0x308 0x304 0x300 0x2FC 0x2F8 0x2F4
0x000FFF30 0x000FFF2C 0x000FFF28 0x000FFF24 0x000FFF20 0x000FFF1C 0x000FFF18 0x000FFF14 0x000FFF10 0x000FFF0C 0x000FFF08 0x000FFF04 0x000FFF00 0x000FFEFC 0x000FFEF8 0x000FFEF4 0x000FFEF0 0x000FFEEC 0x000FFEE8 0x000FFEE4 0x000FFEE0 0x000FFEDC 0x000FFED8 0x000FFED4 0x000FFED0 0x000FFECC 0x000FFEC8 0x000FFEC4 0x000FFEC0 0x000FFEBC to 0x000FFC00
(ICR51) (ICR52) (ICR53) (ICR54) (ICR55) (ICR56) (ICR57) (ICR58) (ICR59) (ICR60) (ICR61) (ICR62) (ICR63) -
0x473 0x474 0x475 0x476 0x477 0x478 0x479 0x47A 0x47B 0x47C 0x47D 0x47E 0x47F -
0x2F0 0x2EC 0x2E8 0x2E4 0x2E0 0x2DC 0x2D8 0x2D4 0x2D0 0x2CC 0x2C8 0x2C4 0x2C0 0x2BC to 0x000
page 71 of 72
Fujitsu, EMDC
MB91F364G - Short specification
The ICRs are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is provided for each interrupt request. *2 The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR). The TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value (0x000FFC00). The TBR is initialized to this value by a reset.After execution of the internal boot ROM TBR is set to 0x00FFC00. *3 Used by REALOS *4 System reserved
*1
Remarks: The 1-Kbyte area from the address specified in TBR is the EIT vector area. Each vector consists of four bytes. The following formula shows the relationship between the vector number and vector address. vctadr= TBR + vctofs = TBR + (3FCH - 4 x vct) vctadr: Vector address vctofs : Vector offset vct : Vector number
page 72 of 72

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