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19-3441; Rev 0; 10/04
Dual-Flash-Pin Electronics/Supervoltage Switch Matrix
General Description
The MAX9960 dual-flash-pin electronics/supervoltage switch matrix replaces most of the relays and switches commonly needed to connect system resources to each of two pins in a flash memory or SOC ATE system (Figure 1). The device provides seven switches per channel to select up to four independent sources: the pin electronics (PE), two parametric measurement units (PMUs) or other Kelvin analog resources, and a flash memory programming supervoltage (FV HH _). The force-and-sense PMU switches are independently controlled, enabling their use to connect two non-Kelvin resources in place of each PMU or Kelvin resource. Each MAX9960 contains two complete seven-switch channels with fully independent controls. The MAX9960 features signal path switches with wide 600MHz bandwidth, low 3 series resistance, and low 8pF shunt capacitance over a voltage range compatible with common pin electronics ICs. An on-chip voltage-doubling buffer with selectable 1x or 2x gain generates the flash supervoltage, allowing a 6.5V DAC reference input to generate up to a maximum of 13V for flash-memory programming levels. When switching from the FVHH_ to PE_ or from PE_ to FVHH_, the device-under-test (DUT_) voltage behaves monotonically. Switching transitions between the PE_ and FVHH_ inputs are typically less than 350ns. The MAX9960 operates over a commercial 0C to +70C temperature range, and is available in the 48-pin thin QFN package (7mm x 7mm x 0.80mm) with an exposed pad on the bottom for heat removal. Dual Supervoltage Switch Arrays 3, 8pF, 600MHz Bandwidth Pin Electronics Paths 13V Flash Programming Paths On-Chip 1x and 2x Selectable Gains 2 Kelvin PMU Paths Fast Switching: 350ns (typ) Monotonic Slew Rate When Switching Between PE_ and FVHH_
Features
MAX9960
Ordering Information
PART MAX9960BCTM TEMP PIN-PACKAGE* RANGE 0oC to +70oC 48 Thin QFN-EP** (7mm x 7mm x 0.8mm) PKG CODE T4877-6
*See full package information at the end of this data sheet. **EP = Exposed pad.
Pin Configuration
PE/FVHHEN1 PMUSAEN1 PMUFAEN1 PMUSA1 PMUSB1 TOP VIEW PMUFBEN1 PMUSBEN1
DUT1
N.C.
PE1
VSS
48 47 46 45 44 43 42 41 40 39 38 37 PE/FVHHSEL1 GND VL V+ VSS N.C. VDD VSS V+ 1 2 3 4 5 6 7 8 9 36 35 34 33 32 31 PMUFA1 PMUFB1 VSS FVHHIN1 FVHHREF1 VDD VDD FVHHREF2 FVHHIN2 VSS PMUFB2 PMUFA2
Applications
Flash Memory Automatic Test Equipment SOC Automatic Test Equipment
VSS 30 29 28 27 26 25 VSS
MAX9960
VL 10 GND 11 PE/FVHHSEL2 12
13 14 15 16 17 18 19 20 21 22 23 24 PMUFAEN2 PE/FVHHEN2 PMUSAEN2 PMUFBEN2 PMUSBEN2 PMUSA2 PMUSB2 DUT2 N.C. PE2 VSS
QFN THIN 7mm x 7mm 0.8mm
________________________________________________________________ Maxim Integrated Products
1
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Dual-Flash-Pin Electronics/Supervoltage Switch Matrix MAX9960
ABSOLUTE MAXIMUM RATINGS
V+ to GND ..............................................................-0.3V to +26V VDD to GND .........................................................-0.3V to +16.5V VSS to GND............................................................-6.5V to +0.3V VL to GND.................................................................-0.3V to +6V V+ to VSS .............................................................................+32V Digital Inputs.....................................(GND - 0.3V) to (VL + 0.3V) FVHHIN_ ....................................................(the higher of -4V and (VSS - 0.3V)) to (the lower of +10V and (VDD + 0.3V)) All Other Pins ...................................(VSS - 0.3V) to (VDD + 0.3V) Continuous Current, PE_ ................................................120mA Continuous Current, PMUS_ _ ..........................................10mA Continuous Current, PMUFA_ + PMUFB_ + (FVHH_ Path) ................................................................45mA Peak Current (100ns), PE_ .............................................300mA Peak Current (100ns), PMUS__ ........................................20mA Peak Current (100ns), PMUFA_ + PMUFB_ + (FVHH_ Path) ................................................................70mA Package Continuous Power Dissipation (TA = +70C) 48-Pin QFN-EP, on Single-Layer Board (derate 27.8mW/C above +70C) .............................2222mW 48-Pin QFN-EP, on Multilayer Board (derate 40.0mW/C above +70C) .............................3200mW Operating Temperature Range...............................0C to +70C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering 10s) ..................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, TA = +25C, unless otherwise noted. Specifications at TA = 0C and TA = +70C are guaranteed by design and characterization. Typical values are at TA = +25C, unless otherwise noted.) (Figure 1)
PARAMETER DC CHARACTERISTICS PE_ PATH VDUT_ = +2.5V, ISW = -40mA to +40mA, TA = 0C to +30C (Note 1) VDUT_ = +2.5V, ISW = -40mA to +40mA, TA = +30C to +70C (Note 1) VDUT_ = 0 to +5V (Note 1) VDUT_ = +2.5V, ISW = -40mA to +40mA 2.5 2.5 -0.6 -0.5 -3.5 -40 FVHH_ = -1.5V to (VDD - 1.5V), IHH_ = -10mA to +10mA (Notes 1, 2) 3.0 3.5 4.2 +0.6 +0.5 +8.0 +40 V mA SYMBOL CONDITIONS MIN TYP MAX UNITS
On-Resistance
RON
On-Resistance Flatness Ch1 to Ch2 Resistance Match Signal Voltage Range Operating DC Current Range FVHH_ PATH On-Resistance Operating Voltage Range Operating DC Current Range FORCE PATHS On-Resistance Operating Voltage Range Operating DC Current Range SENSE PATHS On-Resistance
RFLAT(ON) RMATCH VPE ISW
RON FVHH_ ISW
32 -1.5 -10
100 VDD 1.5 +10
V mA
RON VPMUF ISW
VPMUF_ _ = -4.25V to +14.5V, IPMUF_ _ = -25mA to +25mA (Note 1) -4.25 -25 VPMUS_ _ = -4.25V to +14.5V, IPMUS_ _ = -1mA to +1mA (Note 1)
70 +14.5 +25
V mA
RON
1250
2
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Dual-Flash-Pin Electronics/Supervoltage Switch Matrix
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, TA = +25C, unless otherwise noted. Specifications at TA = 0C and TA = +70C are guaranteed by design and characterization. Typical values are at TA = +25C, unless otherwise noted.) (Figure 1)
PARAMETER Operating Voltage Range Operating DC Current Range FVHH_ BUFFERS DC Output Current Current Limit Operating Voltage Range IODC ILIM FVHH FVHH = -1.5V to (VDD - 1.5V) DUT_ sourcing current DUT_ sinking current FVHHREF_ = 0 (Note 2) FVHHREF_ = 0; no load; relative to 2-point line between VDUT_ = 0 and +13V; measured at VDUT_ = +3.25V, +6.5V, and +9.75V FVHHREF_ = 0, no load, VDUT_ = 0 to +13V (Note 3) VDUT_ = 0 to +13V, FVHHREF_ = 0, TCASE = +30C to +50C FVHHIN_ = -1.5V to +7.5V, FVHHREF_ = open (Note 4) Measured with FVHHIN_ = +5V, FVHHREF_ = 0 Switches S1, S2, S6, S7 open; VDUT_ = -4.25V to +14.5V S1 closed; S2, S6, S7 open; VDUT_ = -3.5V to +8V S2, S4, S6 closed; S1, S3, S5, S7 open; VDUT_ = -4.25V to +14.5V S2, S5, S7 closed; S1, S3, S4, S6 open; VDUT_ = -4.25V to +14.5V S4, S6 open; VPMUFA_ = -4.25V to +14.5V; measured at PMUFA_ with PMUSA_ externally connected to PMUFA_ S5, S7 open; VPMUFB_ = -4.25V to +14.5V; measured at PMUFB_ with PMUSB_ externally connected to PMUFB_ -25 -1.5 0.4 10 +15 -25 -1.5 +25 -15 VDD 1.5V mA mA V SYMBOL VPMUS ISW CONDITIONS MIN -4.25 -1 TYP MAX +14.5 +1 UNITS V mA
MAX9960
Linearity Error
LER_FVHH
-2
+2
mV
Gain Output Offset Output Offset Temperature Coefficient Input Bias Current Gain Resistor Ground Gain Resistor Current LEAKAGE (Notes 5, 6) DUT_ Leakage, Disabled PE_ Leakage PMUA_ Path Leakage, Enabled PMUB_ Path Leakage, Enabled
GFVHH
1.98 -50
2.00
2.02 +50
V/V mV mV/C
VOS_FVHH FVHHREF_ = 0, VDUT_ = +12V, no load TC_VOS IFVHH FVHHREF IVHHREF
0.2 +25 +0.5
A V mA
ILEAK_OFF ILEAK_PE ILEAK_PMU
A_ON
-1 -1 -1 -1
+1 +1 +1 +1
nA nA nA nA
ILEAK_PMU
B_ON
PMUA_ Path Leakage, Disabled
ILEAK_PMU
A_OFF
-1
+1
nA
PMUB_ Path Leakage, Disabled
ILEAK_PMU
B_OFF
-1
+1
nA
DIGITAL INPUTS (PMUF_EN_, PMUS_EN_, PE/FVHHEN_, PE/FVHHSEL_) Input High Voltage Input Low Voltage VIH VIL +2.3 +0.4 V V
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Dual-Flash-Pin Electronics/Supervoltage Switch Matrix MAX9960
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, TA = +25C, unless otherwise noted. Specifications at TA = 0C and TA = +70C are guaranteed by design and characterization. Typical values are at TA = +25C, unless otherwise noted.) (Figure 1)
PARAMETER Input Voltage Range Input Current POWER SUPPLIES Positive Supply Negative Supply High Voltage Supply Logic Supply Quiescent Positive Supply Current VDD VSS V+ VL V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, FVHHIN_ = +6.5V, FVHHREF_ = 0, all digital inputs = +2.3V, no loads V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, FVHHIN_ = +6.5V, FVHHREF_ = 0, all digital inputs = +2.3V, no loads V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, FVHHIN_ = +6.5V, FVHHREF_ = 0, all digital inputs = +2.3V, no loads V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, FVHHIN_ = +6.5V, FVHHREF_ = 0, all digital inputs = +2.3V, no loads (Note 1) 14.5 -6.00 23 3.0 15 -5 24 3.3 16.0 -4.25 25 3.6 V V V V SYMBOL VIN IIH, IIL VIN = -0.2V to VL CONDITIONS MIN -0.2 -10 TYP MAX VL +10 UNITS V A
(IDD, I+)
10
mA
Quiescent Negative Supply Current
ISS
8.5
mA
Quiescent Logic Supply Current
IVL
2
mA
Quiescent Power Dissipation
PDQ
200
mW
AC CHARACTERISTICS SWITCHING TIMES BETWEEN PE_ AND FVHH_ PATHS (Note 7) (Figure 3) Switch PE_ to FVHH_ FVHH_ Settling Time Switch FVHH_ to PE_ PE_ Settling Time PE_ TO FVHH_ Overshoot/Undershoot PE_ to FVHH_ Preshoot Minimum Switching Slew Rate PE_ Switch On-Time FVHH_ Switch On-Time SRMIN tON_1 tON_2,3 Over 20% to 80% region VPE_ = +5V from 47 source FVHHIN_ = +2.5V, FVHHREF_ = 0 SWITCHING TIMES, SAME PATH (Note 8) (Figure 2) 150 350 ns ns tON_FVHH tS_FVHH tON_PE tS_PE Settling to within larger of 1% step voltage or 50mV of final value +5V to +7V transition 0 to +13V transition Settling to within larger of 1% step voltage or 50mV of final value 275 350 500 300 500 100 150 10 425 425 500 ns ns ns ns mV mV V/s
4
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Dual-Flash-Pin Electronics/Supervoltage Switch Matrix
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, TA = +25C, unless otherwise noted. Specifications at TA = 0C and TA = +70C are guaranteed by design and characterization. Typical values are at TA = +25C, unless otherwise noted.) (Figure 1)
PARAMETER PMUF_ _ Switch On-Time PMUS_ _ Switch On-Time PE_, FVHH_, PMUF_ _, PMUS_ _ Switch Off-Times SYMBOL tON_2,4 tON_2,5 tON_6 tON_7 tOFF CONDITIONS VPMUF_ _ = +5V VPMUS_ _ = +5V MIN TYP 150 300 700 MAX UNITS ns ns ns
MAX9960
CAPACITANCE AND BANDWIDTH (Note 5) Capacitance, All Paths Disconnected CDUT_OFF All switches disconnected, for frequencies greater than 2MHz (Note 9) Switch S1 closed, all others open, for frequencies greater than 2MHz CDUT_PE Switch S1 closed, all others open, for frequencies less than 1kHz Switch S1 closed, all others open, for frequencies greater than 2MHz (Note 9) S2, S4, and S6 closed; all others open (Note 9) S2, S5, and S7 closed; all others open (Note 9) 20 8 pF 50 2 35 35 10 10 10 10 5 5 600 pF pF pF pF pF pF pF pF pF MHz pF
Capacitance, PE_ Path Connected (Note 9)
Unit-to-Unit Variation, PE_ Path Connected Capacitance, PMUFA_ and PMUSA_ Path Connected Capacitance, PMUFB_ and PMUSB_ Path Connected Capacitance, PMUFA_ Path Disconnected Capacitance, PMUFB_ Path Disconnected Capacitance, PMUSA_ Path Connected Capacitance, PMUSB_ Path Connected Capacitance, PMUSA_ Path Disconnected Capacitance, PMUSB_ Path Disconnected PE_ Signal Bandwidth FVHH_ BUFFER Slew Rate
CDUT_PE CDUT_PMUA CDUT_PMUB
CPMUFA_OFF S4 open, measured at PMUFA_ (Note 9) CPMUFB_OFF S5 open, measured at PMUFB_ (Note 9) CPMUSA_ON CPMUSB_ON S6 closed, all others open, measured at PMUSA_ (Note 9) S7 closed, all others open, measured at PMUSB_ (Note 9)
CPMUSA_OFF S6 open, measured at PMUSA_ (Note 9) CPMUSB_OFF S7 open, measured at PMUSB_ (Note 9) f3DB Only PE_ path enabled (Note 10) FVHHREF_ = 0, (gain = 2), FVHHIN_ stepped from 0 to +5V and +5V to 0 CDUT_ = 200pF to within 0.1% of step voltage, after FVHHIN_ changes CDUT_ = 4000pF to within 0.1% of step voltage, after FVHHIN_ Changes (Note 11)
SRFVHH
5 25
V/s
Settling
tS
s 50
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Dual-Flash-Pin Electronics/Supervoltage Switch Matrix MAX9960
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, TA = +25C, unless otherwise noted. Specifications at TA = 0C and TA = +70C are guaranteed by design and characterization. Typical values are at TA = +25C, unless otherwise noted.) (Figure 1) V+ should be at least 8V above VDD to guarantee specified path resistance values. When the FVHH_ buffer is configured for a gain of +1 (FVHHREF_ open), the output voltage range is limited to -1.5V to +7.5V. Note 3: FVHH_ buffer gain is typically +1, when FVHHREF_ is open. Note 4: FVHHREF_ is tested by repeating the FVHH_ path resistance tests over the variation of FVHHREF_. For each value of FVHHREF_, FVHHIN_ is adjusted to FVHHIN_ = (FVHH_ + FVHHREF_) / 2. Note 5: All measurements taken at DUT_, except where noted. Note 6: These specifications are guaranteed by design and characterization. In addition, these specifications will be production tested with min/max test limits of 10nA. Note 7: Voltage source driving PE_ has 47 source resistance. PE_ = 0 to +5.0V, FVHH_ = +7 to +13V. Measured from 50% point of input logic to 90% of analog swing. Note 8: All unused switches open, unless otherwise noted. Measured from 50% point of input logic to 90% of analog swing. Note 9: Unless otherwise noted, measured at DUT_. No external connections to any of the switched analog pins--PE_, DUT_, PMUFA_, PMUFB_, PMUSA_, or PMUSB_--except as needed to make measurement. Note 10: ZDUT_ = 50; equivalent bandwidth calculated from measured DUT_ rise and fall time with PE_ stimulated by a 3V step with 1ns 10% to 90% rise/fall time. Note 11: The maximum load for FVHH buffer is 4000pF. Note 1: Note 2:
Typical Operating Characteristics
(V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, TA = +25C, unless otherwise noted.)
PE PATH RESISTANCE vs. VOLTAGE
MAX9960 toc01
FORCE PATH RESISTANCE vs. VOLTAGE
MAX9960 toc02
SENSE PATH RESISTANCE vs. VOLTAGE
IPATH = 1mA 900 PATH RESISTANCE () 800 700 600 500 400 300 200
MAX9960 toc03
8 IPATH = 40mA 7 PATH RESISTANCE () 6 5 4 3 2 1 0
80 IPATH = 25mA 70 PATH RESISTANCE () 60 50 40 30 20 10 0
1000
-3.50 -2.35 -1.20 -0.05 1.10 2.25 3.40 4.55 5.70 6.85 8.00 VOLTAGE (V)
-5.0 -2.5
0
2.5
5.0
7.5 10.0 12.5 15.0
-5.0 -2.5
0
2.5
5.0
7.5 10.0 12.5 15.0
VOLTAGE (V)
VOLTAGE (V)
6
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Dual-Flash-Pin Electronics/Supervoltage Switch Matrix MAX9960
Typical Operating Characteristics (continued)
(V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, TA = +25C, unless otherwise noted.)
FVHH_ PATH RESISTANCE vs. VOLTAGE
MAX9960 toc04
PE PATH RESISTANCE vs. TEMPERATURE
MAX9960 toc05
LEAKAGE CURRENT vs. TEMPERATURE
PMUA VDUT_ = +14.5V PMUB VDUT_ = +14.5V
MAX9960 toc06
100 90 PATH RESISTANCE () 80 70 60 50 40 30 20 10 -5.0 -2.5 0 2.5 5.0 IPATH = 10mA
8 7 PATH RESISTANCE () 6 5 4 3 2 1 0
IPATH = 40mA VPE_ = +2.25V
0.5 0.4 0.3 LEAKAGE (nA) 0.2 0.1 0 -0.1 -0.2 PE, VDUT_ = +8V 0 10 20 30 40 50 60
7.5 10.0 12.5 15.0
0
10
20
30
40
50
60
70
70
VOLTAGE (V)
TEMPERATURE (C)
TEMPERATURE (C)
PE_ TO FVHH_ TRANSITIONS
MAX9960 toc07
PE_ TO FVHH_ TRANSITIONS
DUT_
MAX9960 toc08
DUT_
V = 1V/div
PE/VHHSEL_ 0 0 t = 250ns/div VPE_ = +5V, FVHH_ = +7V
V = 2V/div
PE/VHHSEL_
t = 250ns/div VPE_ = 0V, FVHH_ = +13V
FVHH_ SLEW
MAX9960 toc09
FVHH BUFFER OUTPUT OFFSET vs. TEMPERATURE
1.5 1.0 OFFSET (mV) 0.5 0 -0.5 -1.0
MAX9960 toc10
NO LOAD FVHHREF_ = 0 DUT_ V = 2V/div FVHHIN_
2.0
0
-1.5 -2.0 t = 500ns/div 0
FVHHIN_ = 0 FVHHREF_ = 0 10 20 30 40 50 60 70
TEMPERATURE (C)
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Dual-Flash-Pin Electronics/Supervoltage Switch Matrix MAX9960
Pin Description
PIN 1 2, 11 3, 10 4, 9 5, 8, 20, 24, 27, 34, 37, 41 6, 22, 39 7, 30, 31 12 13 14 15 16 17 18 19 21 23 25 26 28 29 32 33 35 36 38 40 42 43 NAME PE/FVHHSEL1 GND VL V+ VSS N.C. VDD PE/FVHHSEL2 PE/FVHHEN2 PMUFAEN2 PMUSAEN2 PMUFBEN2 PMUSBEN2 PMUSA2 PMUSB2 DUT2 PE2 PMUFA2 PMUFB2 FVHHIN2 FVHHREF2 FVHHREF1 FVHHIN1 PMUFB1 PMUFA1 PE1 DUT1 PMUSB1 PMUSA1 FUNCTION PE1 or FVHH1 Select. Selects either PE1 or FVHH1 to be connected to DUT1. Force low to select PE1, force high to select FVHH1. Ground Logic Power Supply. Nominally 3.3V. Analog Positive Gate-Drive Power Supply. Nominally 24V. Analog Negative Power Supply. Nominally -5V. No Connection. Make no connection to this pin. Analog Positive Power Supply. Nominally 15V. PE2 or FVHH2 Select. Selects either PE2 or FVHH2 to be connected to DUT2. Force low to select PE2, force high to select FVHH2. PE2 and FVHH2 Enable. Enables PE2 and FVHH2 to be connected to DUT2, as determined by PE/FVHHSEL2. Force low to enable signal path, force high to disable the signal path. PMUFA2 Enable. Controls the connection of PMUFA2 to DUT2. Force low to connect PMUFA2 to DUT2, force high to disconnect PMUFA2 from DUT2. PMUSA2 Enable. Controls the connection of PMUSA2 to DUT2. Force low to connect PMUSA2 to DUT2, force high to disconnect PMUSA2 from DUT2. PMUFB2 Enable. Controls the connection of PMUFB2 to DUT2. Force low to connect PMUFB2 to DUT2, force high to disconnect PMUFB2 from DUT2. PMUSB2 Enable. Controls the connection of PMUSB2 to DUT2. Force low to connect PMUSB2 to DUT2, force high to disconnect PMUSB2 from DUT2. Sense A Analog Output for Channel 2. Kelvin feedback output for the channel 2 force A path. Sense B Analog Output for Channel 2. Kelvin feedback output for the channel 2 force B path. Analog I/O for Channel 2. Connects to the DUT. Analog I/O for Channel 2. Connects to the pin electronics I/O. Analog Input Force A for Channel 2. Connects to an external DC resource such as a PMU. Analog Input Force B for Channel 2. Connects to an external DC resource such as a PMU. Analog Supervoltage Input for Channel 2. The voltage applied to FVHHIN2 is amplified as determined by FVHHREF2 (see the Functional Block Diagram). Analog Gain-Setting Input for Channel 2. Sets the gain of the FVHH2 buffer. Analog Gain-Setting Input for Channel 1. Sets the gain of the FVHH1 buffer. Analog Supervoltage Input for Channel 1. The voltage applied to FVHHIN1 is amplified as determined by FVHHREF1 (see the Functional Block Diagram). Analog Input Force B for Channel 1. Connects to an external DC resource such as a PMU. Analog Input Force A for Channel 1. Connects to an external DC resource such as a PMU. Analog I/O for Channel 1. Connects to the pin electronics I/O. Analog I/O for Channel 1. Connects to the DUT. Sense B Analog Output for Channel 1. Kelvin feedback output for the channel 1 force B path. Sense A Analog Output for Channel 1. Kelvin feedback output for the channel 1 force A path.
8
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Dual-Flash-Pin Electronics/Supervoltage Switch Matrix MAX9960
Pin Description (continued)
PIN 44 45 46 47 48 -- NAME PMUSBEN1 PMUFBEN1 PMUSAEN1 PMUFAEN1 PE/FVHHEN1 EP FUNCTION PMUSB1 Enable. Controls the connection of PMUSB1 to DUT1. Force low to connect PMUSB1 to DUT1, force high to disconnect PMUSB1 from DUT1. PMUFB1 Enable. Controls the connection of PMUFB1 to DUT1. Force low to connect PMUFB1 to DUT1, force high to disconnect PMUFB1 from DUT1. PMUSA1 Enable. Controls the connection of PMUSA1 to DUT1. Force low to connect PMUSA1 to DUT1, force high to disconnect PMUSA1 from DUT1. PMUFA1 Enable. Controls the connection of PMUFA1 to DUT1. Force low to connect PMUFA1 to DUT1, force high to disconnect PMUFA1 from DUT1. PE1 and FVHH1 Enable. Enables PE1 and FVHH1 to be connected to DUT1, as determined by PE/FVHHSEL1. Force low to enable signal path, force high to disable the signal path. Exposed Pad for Heat Removal. Internally biased to VSS. Connect to VSS or leave floating.
Detailed Description
PE_ FVHHIN_
MAX9960
FVHH_ S3 R R S4 S2
S1 DUT_
FVHHREF_ PMUFA_ PMUFAEN_ PMUFB_ PMUFBEN_
S5
PE/FVHHEN_ PE/FVHHSEL_ S6 PMUSA_ PMUSAEN_ S7 PMUSB_ PMUSBEN_ ONE OF TWO CHANNELS SHOWN. LOGIC ZERO AT SWITCH = SWITCH CLOSED.
The MAX9960 is a dual analog switch matrix featuring two Kelvin PMU paths, a PE path, and a flash programming supervoltage circuit that allows testing of flash memory using standard PE devices. It makes possible, without the use of relays, a fully functional pin with both AC and DC capabilities. The signal path switches feature 600MHz bandwidth, 3 series resistance, and 8pF shunt capacitance over a voltage range compatible with common pin-electronics ICs. The voltage-doubling buffer, with selectable 1x or 2x gain, generates the 13V flash memory programming level from a 6.5V input. Configure the switches using digital inputs PMUFAEN_, PMUSAEN_, PMUFBEN_, PMUSBEN_, PE/FVHHEN_, and PE/FVHHSEL_ as indicated in Tables 1 and 2. The switching speed between PE_ and FVHH_ paths is less than 350ns typical (Figure 3), and during switching, DUT_ behaves monotonically.
FVHH Buffer Load Capacitance
The maximum load capacitance for the FVHH buffer is 4000pF. While this amount of load capacitance is not expected during normal operation, an application may call for the buffer to be connected to a highly capacitive PMU path occasionally for calibration purposes. No damage to the MAX9960 will result as a consequence of this condition.
Figure 1. Functional Block Diagram
Supervoltage FVHH Buffer Gain
The FV HH buffer gain can be selected using FVHHREF_. If FVHHREF_ is grounded, the gain of the buffer is +2. If FVHHREF_ is left floating, the buffer gain is +1.
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Dual-Flash-Pin Electronics/Supervoltage Switch Matrix MAX9960
Table 1. Switch Control, All Possible Combinations
PMUFAEN_ 0 X X X X X PMUFBEN_ X 0 X X X X PMUSAEN_ X X 0 X X X PMUSBEN_ X X X 0 X X PE/FVHHEN_ X X X X 0 0 PE/FVHHSEL_ X X X X 1 0 DUT_ PMUFA_ path connected PMUFB_ path connected PMUSA_ path connected PMUSB_ path connected FVHH_ path connected PE_ path connected Every path is disconnected
All other combinations
Table 2. Switch Control, Use Cases
PMUFAEN_ 1 1 0 1 0 1 0 1 0 PMUFBEN_ 1 1 1 0 1 0 1 0 0 PMUSAEN_ 1 1 0 1 0 1 0 1 0 PMUSBEN_ 1 1 1 0 1 0 1 0 0 PE/FVHHEN_ 0 0 1 1 0 0 0 0 0 PE/FVHHSEL_ 0 1 X X 0 0 1 1 0 PE_ FVHH_ PMUFA_ + PMUSA_ PMUFB_ + PMUSB_ PE_ + PMUFA_ + PMUSA_ PE_ + PMUFB_ + PMUSB_ FVHH_ + PMUFA_ + PMUSA_ FVHH_ + PMUFB_ + PMUSB_ PE_ + PMUFA_ + PMUSA_ + PMUFB_ + PMUSB_ DUT_
Power-Supply Considerations
The MAX9960 requires four power-supply voltages, typically V+ = +24V, VDD = +15V, VSS = -5V, and VL = +3.3V. Use a 0.1F bypass capacitor close to each supply pin, and provide bulk bypassing where power enters the circuit board. The MAX9960 does not require any special power-up sequencing.
MAX9960
PMUS_ _
PMUF_ _
Chip Information
TRANSISTOR COUNT: 2020 PROCESS: BiCMOS
FVHHIN_ 47 PE_ FVHH_ DUT_
1k
200pF
Figure 2. Switching Time Test Circuit
10
______________________________________________________________________________________
Dual-Flash-Pin Electronics/Supervoltage Switch Matrix MAX9960
PE _ TO FVHH_ TRANSITION
MINIMUM SWITCHING SLEW RATE
OVERSHOOT
SETTLING
PRESHOOT
VFVHH_ 90%
OVERSHOOT SETTLING 10% VPE_ PRESHOOT tON_FVHH tS_FVHH tON_PE tS_PE
PE/FVHHSEL_
Figure 3. PE_ - FVHH_ and FVHH_ - PE_ Transition and Settling Timing
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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