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19-3437; Rev 1; 12/04
10.7Gbps, +3.3V, Compact VCSEL Driver
General Description
The MAX3975 is a +3.3V driver designed to directly modulate common-anode vertical cavity surface emitting lasers (VCSELs) at data rates up to 10.7Gbps. The driver output can be connected directly to the VCSEL, requiring no external components for biasing. With a 2.5mm x 2.5mm chip-scale package (UCSPTM), transmit disable, output-current monitor, and 0C to +85C operation, the MAX3975 is ideal for 850nm XFP/XENPAK transceivers. The MAX3975 delivers 3mA to 12mA of modulation current, with 1.5mA to 10mA of bias current (peak current 22mA). Typical switching time is 28ps (20% to 80%) with 8ps of deterministic jitter. 2.5mm x 2.5mm Chip-Scale Package (5 x 5 Array UCSP) Single +2.97V to +3.63V Supply Voltage 28ps Switching Time DC-Coupled Output 3mA to 12mA Modulation Current 1.5mA to 10mA Bias Current
Features
MAX3975
Output Disable Circuit Output-Current Monitor
Applications
10 Gigabit Ethernet Transceivers XFP/XENPAK/X2/XPAK Optical Transceivers SONET VSR Optical Transmitters 10 Gigabit Fibre-Channel Transceivers
B VEE C MONITOR N.C. TOP VIEW A VCC IN1 2
Pin Configuration
3 4 5
DISABLE
IN+
VEE
N.C.
MODSET
Ordering Information
PART MAX3975UBA-T TEMP RANGE 0C to +85C PIN-PACKAGE 20 UCSP-20 (2.5mm x 2.5mm) PKG CODE B25-4
MAX3975
BIASSET
D VCC E VCC VCC OUT UCSP VEE VEE N.C. N.C. VEE
UCSP is a trademark of Maxim Integrated Products, Inc.
Typical Application Circuit
+3.3V SAFETY AND POWER SEQUENCING
0.1F 50 IN+
VCC
MAX3992 SIGNAL CONDITIONER
0.1F 50 IN-
MAX3975
MODSET BIASSET MONITOR DISABLE
OUT 50
VCSEL TOSA
DS1862* CONTROLLER IC
MOD_DR BIAS_DR AUX1_MON IMD
REPRESENTS A CONTROLLED-IMPEDANCE TRANSMISSION LINE *FUTURE PRODUCT
________________________________________________________________ Maxim Integrated Products
VEE
1k
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
10.7Gbps, +3.3V, Compact VCSEL Driver MAX3975
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (VCC) .................................-0.5V to +4.5V Voltage at IN+, IN- ........................(VCC - 1.75V) to (VCC + 0.5V) Differential Input Voltage (IN+ - IN-) ...................................1.5V Voltage at DISABLE................................... -0.5V to (VCC + 0.5V) Voltage at MODSET, BIASSET ............................. -0.5V to +2.0V Voltage at MONITOR................................................-0.5V to VCC Continuous Current at OUT.................................................30mA Voltage at OUT ........................................................................4V Continuous Power Dissipation (TA = +85C) 20-Bump UCSP (derate 10.0mW/C above +85C) ....650mW Operating Junction Temperature.....................................+150C Storage Temperature Range .............................-55C to +150C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC - VOUT-MIN - 1.2V) (VCC = +2.97V to +3.63V, RLOAD = 50, IMOD + IBIAS , TA = 0C to +85C. Typical values are at VCC = +3.3V, 50 IBIAS = 6.0mA, IMOD = 6.0mA, and TA = +25C, unless otherwise noted.)
PARAMETER POWER SUPPLY
SYMBOL
CONDITIONS IBIAS = 10mA, IMOD = 12mAP-P, DISABLE = low
MIN
TYP
MAX
UNITS
106 55 34 42 1000 42 12 50 50
135 70 50 58 250 mVP-P mVP-P 58 3 mA mA mA
Power-Supply Current (Includes Bias and Modulation Currents)
ICC
IBIAS = 1.5mA, IMOD = 3mAP-P, DISABLE = low DISABLE = high
SIGNAL INPUT Input Impedance Input Sensitivity Input Overload LASER MODULATION Output Resistance Minimum Modulation Maximum Modulation Modulation Current When DISABLE = High Voltage at OUT Deterministic Jitter Random Jitter Output Switching Time Current Gain from MODSET to OUT LASER BIAS Minimum Bias Current Maximum Bias Current Current Gain from BIASSET to OUT Bias-Set Current Threshold for Disable Output Current when Disabled (Note 5) IBIASSET 10A or DISABLE = high 10 IBIAS-MIN IBIAS-MAX 10 10 25 250 1.5 mA mA mA/mA A A VOUT DJ RJ tR, tF RT IMOD-MIN IMOD-MAX VIN = 1000mVP-P (Note 1) (Note 2) (Notes 1, 3) (Note 1) 20% to 80% (Notes 1, 4) 0.7 8 0.35 28 10 18 0.8 36 VIN-MIN VIN-MAX Single ended (Figure 2) (Figure 2)
100
250
AP-P V psP-P psRMS ps mA/mA
2
_______________________________________________________________________________________
10.7Gbps, +3.3V, Compact VCSEL Driver MAX3975
ELECTRICAL CHARACTERISTICS (continued)
(VCC - VOUT-MIN - 1.2V) (VCC = +2.97V to +3.63V, RLOAD = 50, IMOD + IBIAS , TA = 0C to +85C. Typical values are at VCC = +3.3V, 50 IBIAS = 6.0mA, IMOD = 6.0mA, and TA = +25C, unless otherwise noted.)
PARAMETER MONITOR OUTPUT MONITOR Gain MONITOR Offset Error MONITOR Gain Variation DISABLE INPUT Input High Voltage Input Low Voltage Input Resistance Input Current
SYMBOL
CONDITIONS RMONITOR = 1k
MIN
TYP 16
MAX
UNITS mA/mA
-25 -30 VCC and temperature only 2.0 8
+25 +30
A %
V 0.8 V k A 76 100 +100
RDIS -0.3V < VDISABLE < (VCC + 0.3V)
50 -100
LASER CURRENT PROGRAMMING Reference Voltage at BIASSET and MODSET Gain Matching of IBIAS and IMOD VBG (Note 6) -25 1.2 +25 V %
Guaranteed by design and characterization using the circuit shown in Figure 1. VOUT is the minimum instantaneous voltage at the output (not the average voltage). Measured at 10.7Gbps with a pattern equivalent to 223 - 1 PRBS. Measured at 2.5Gbps with a 0101 repeating pattern. Programming a bias set current (IBIASSET) below the threshold disables the output currents. Bias Gain Note 6: Gain Matching = 100 x - 1 Modulation Gain Note 1: Note 2: Note 3: Note 4: Note 5: Measured under the following conditions: IMOD = 12mA, IBIAS = 4mA IMOD = 3mA, IBIAS = 4mA IMOD = IBIAS = 4mA IMOD = IBIAS = 8mA.
_______________________________________________________________________________________
3
10.7Gbps, +3.3V, Compact VCSEL Driver MAX3975
VPOS [1.2V, 1.5V] VCC
VOLTAGE
VINVIN+
125mVP-P MIN 500mVP-P MAX
MAX3975
OUT
IOUT Z0 = 50
OSCILLOSCOPE
(VIN+) - (VIN-)
250mVP-P MIN 1000mVP-P MAX
50 VEE VNEG [-2.43V, -1.77V], VPOS = 1.2V VNEG [-2.13V, -1.47V], VPOS = 1.5V EQUIVALENT CIRCUIT VPOS [2.97V, 3.63V] VCC VPOS [2.97V, 3.63V] VL [1.2V, 1.5V]
TIME CURRENT IOUT IMOD
Figure 2. Required Input Signal and Output Polarity
MAX3975
OUT
IOUT Z0 = 50
RLOAD = 50
VEE
Figure 1. AC Characterization Circuit
Typical Operating Characteristics
(VCC = +2.97V to +3.63V, RLOAD = 50, TA = 0C to +85C. Typical values are at VCC = +3.3V, IBIAS = 6.0mA, IMOD = 6.0mA, and TA = +25C, unless otherwise noted.)
10.3Gbps OPTICAL EYE DIAGRAM (PAVG = -2.0dBm, OMA = 471WP-P, 223 - 1 PRBS) (ADVANCED OPTICAL COMPONENTS VCSEL TOSA HFE6190-561)
MAX3975 toc03
10.3Gbps ELECTRICAL EYE DIAGRAM (IBIAS = 4mA, IMOD = 5mA, 223 - 1 PRBS)
MAX3975 toc01
10.3Gbps ELECTRICAL EYE DIAGRAM (IBIAS = 10mA, IMOD = 12mA, 223 - 1 PRBS)
MAX3975 toc02
16ps/div
16ps/div
14ps/div 8GHz FILTER, 24% 10GbE MASK MARGIN
4
_______________________________________________________________________________________
10.7Gbps, +3.3V, Compact VCSEL Driver MAX3975
Typical Operating Characteristics (continued)
(VCC = +2.97V to +3.63V, RLOAD = 50, TA = 0C to +85C. Typical values are at VCC = +3.3V, IBIAS = 6.0mA, IMOD = 6.0mA, and TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE (INCLUDES IBIAS AND IMOD)
MAX3975 toc04
DETERMINISTIC JITTER vs. MODULATION CURRENT
30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 3
MAX3975 toc05
RANDOM JITTER vs. MODULATION CURRENT
1.8 1.6 RANDOM JITTER (psRMS) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
MAX3975 toc06
200 180 160 SUPPLY CURRENT (mA) 140 120 100 80 60 40 20 0 -40 -20 0 20 40 60 80 IBIAS = 10mA IMOD = 12mA
2.0
10.7Gbps 23 2 - 1 PRBS EQUIVALENT PATTERN
IBIAS = 6mA IMOD = 7.5mA
IBIAS = 1.5mA IMOD = 3mA
DETERMINISTIC JITTER (psP-P)
100
4
5
6
7
8
9
10
11
12
3
4
5
6
7
8
9
10
11
12
TEMPERATURE (C)
MODULATION (mA)
MODULATION (mA)
BIAS CURRENT vs. RBIASSET
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0.1k 1k RBIASSET () 10k 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAX3975 toc07
MODULATION CURRENT vs. RMODSET
12 11 10 9 8 7 6 5 4 3 2 1 0 0.1k 1k RMODSET () 10k 100k 0
MAX3975 toc08
BIAS CURRENT vs. IBIASSET
MAX3975 toc09
MODULATION CURRENT (mA)
BIAS CURRENT (mA)
BIAS CURRENT (mA)
100k
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 IBIASSET (mA)
MODULATION CURRENT vs. IMODSET
12 11 10 9 8 7 6 5 4 3 2 1 0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 IMODSET (mA) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
MAX3975 toc10
MONITOR CURRENT vs. IOUT
MAX3975 toc11
MONITOR GAIN vs. TEMPERATURE (IBIAS AND IMOD REMAIN CONSTANT)
19 MONITOR GAIN (mA) 18 17 16 15 14
MAX3975 toc12
20
MODULATION CURRENT (mA)
MONITOR CURRENT (mA)
IOUT = IBIAS + IMOD / 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IOUT (mA)
13 12 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
_______________________________________________________________________________________
5
10.7Gbps, +3.3V, Compact VCSEL Driver MAX3975
Typical Operating Characteristics (continued)
(VCC = +2.97V to +3.63V, RLOAD = 50, TA = 0C to +85C. Typical values are at VCC = +3.3V, IBIAS = 6.0mA, IMOD = 6.0mA, and TA = +25C, unless otherwise noted.)
TRANSMITTER ENABLE
MAX3975 toc13
TRANSMITTER DISABLE
MAX3975 toc14
DISABLE
DISABLE
IOUT
IOUT
1s/div
1s/div
S11 vs. FREQUENCY (DIFFERENTIAL)
MAX3975 toc15
S22 vs. FREQUENCY (SINGLE ENDED)
-5 -10 -15 S22 (dB) -20 -25 -30 -35 -40 -45 -50
MAX3975 toc16
0 -5 -10 DIFFERENTIAL S11 (dB) -15 -20 -25 -30 -35 -40 -45 -50 0 2 4 6 8
0
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
FREQUENCY (GHz)
FREQUENCY (GHz)
6
_______________________________________________________________________________________
10.7Gbps, +3.3V, Compact VCSEL Driver MAX3975
Pin Description
PIN A1, D1, E1, E2 A2 A3 A4 A5, B1, D5, E4, E5 B2, B4, D2, D4 B5 NAME VCC INDISABLE IN+ VEE N.C. FUNCTION +3.3V Supply Voltage. All VCC pins must be connected to the supply voltage. Negative Data Input. Includes 50 to VCC on-chip termination resistor. Transmitter Disable, TTL Compatible. Total VCSEL current is low when this pin is set to a TTL high (asserted) or left open. VCSEL current is enabled when this input is set to a TTL low (deasserted). Positive Data Input. Includes 50 to VCC on-chip termination resistor. Supply Ground. All VEE pins must be connected to the supply ground. No Connection. These pins must be soldered to the circuit board but should not be electrically connected to any circuit nodes (left floating). Modulation Current Set Pin, Analog. A resistor connected from this pin to VEE sets the desired modulation current. Modulation current can also be programmed with a current-sinking digital-to-analog converter (DAC) or voltage DAC with series resistor. See Figure 4. VCSEL DC Current Monitor, Analog. Current from this output is proportional to the VCSEL DC current. Connect to VEE if not required in the application. Bias Current Set Pin, Analog. A resistor connected from this pin to ground sets the desired bias current. Bias current can also be programmed with a current-sinking DAC or voltage DAC with series resistor. See Figure 4. Programming a current below the bias-set current threshold disables the driver output. Modulation and Bias Current Output (Current Flows from VCSEL to OUT). Connect to VCSEL cathode.
DISABLE VCC VCC V RDIS
MODSET
C1
MONITOR
C5 E3
BIASSET OUT
MAX3975
VCC 50 IN-
VCC
OUT
VCC IN+ IMOD 50 VBG VCC VBG IBIAS IMONITOR
MODSET RMODSET
BIASSET RBIASSET
MONITOR RMONITOR
Figure 3. Functional Diagram _______________________________________________________________________________________ 7
10.7Gbps, +3.3V, Compact VCSEL Driver MAX3975
Detailed Description
The MAX3975 VCSEL driver consists of a high-speed modulator with programmable modulation and bias currents, transmitter disable circuit, and output-current monitor (Figure 3). The MAX3975 operates from a +3.3V supply and provides a 50 output termination, 3mA to 12mA of modulation, and 1.5mA to 10mA of bias current, allowing operation with a variety of 10Gbps VCSELs. IBIAS = IBIASSET x 10 The control current is programmed with a resistor from BIASSET to VEE. The control current can also be programmed with a current-sinking DAC or voltage DAC with series resistor as shown in Figure 4. Programming a set current below the bias-set current threshold disables the driver output.
Transmitter Disable
The MAX3975 is equipped with a transmitter disable control (DISABLE). The DISABLE input is a TTL-compatible, low-current digital input. When DISABLE is set to TTL high (asserted) or left open, both the modulation and bias currents are disabled. The modulation and bias currents are enabled when DISABLE is set to TTL low (deasserted), and IBIASSET is above the disable threshold.
Modulation Circuit
The modulation circuitry consists of an input buffer, a current mirror, and a high-speed current switch. The modulator drives up to 12mA of modulation with a 50 VCSEL load. The amplitude of the modulation current at OUT (IMOD) is linearly proportional to the control current at MODSET and is given by the relationship: IMOD = IMODSET x 10 The control current is programmed with a resistor from MODSET to VEE. The control current can also be programmed with a current-sinking DAC or voltage DAC with series resistor as shown in Figure 4.
Output Current Monitor
The MONITOR is a current output that provides an indication of the VCSEL DC current. Connecting a resistor (RMONITOR) from the MONITOR output to VEE gives the following relationship: VMONITOR = (1/16) x (IBIAS + (IMOD / 2)) x RMONITOR where, (IBIAS + (IMOD / 2)) = VCSEL DC current. The voltage at the monitor output must be less than 2.18V for compliance. The recommended range for RMONITOR is 500 to 1.2k, with 1k being typical. MONITOR must be connected to VEE if not required in the application.
Biasing Circuit
The biasing circuitry consists of a current mirror that is connected to the driver output. Bias and modulation currents are combined internally, eliminating the need for an external bias inductor. The biasing circuit provides up to 10mA of bias current with a 50 VCSEL load. The bias current at OUT (IBIAS) is linearly proportional to the control current at BIASSET and is given by the relationship:
+3.3V VCC VBG OR VBG
+3.3V VCC VBG OR
+3.3V VCC
VEE
MODSET OR BIASSET IMODSET OR IBIASSET
VEE
MODSET OR BIASSET IMODSET OR IBIASSET CURRENTSINKING DAC
VEE
MODSET OR BIASSET IMODSET OR IBIASSET V -V ISET = BG DAC RSET VOLTAGE DAC
DIGITAL OR ANALOG VARIABLE RESISTOR
RMODSET OR RBIASSET
RSET
Figure 4. Bias and Modulation Current Controls 8 _______________________________________________________________________________________
10.7Gbps, +3.3V, Compact VCSEL Driver MAX3975
Table 1. Optical Power Relations
PARAMETER Average Power Extinction Ratio Optical Power of a 1 Optical Power of a 0 Optical Modulation Amplitude Laser Slope Efficiency Modulation Current Bias Current SYMBOL PAVG Er P1 P0 OMA IMOD IBIAS RELATION PAVG = (P0 + P1) / 2
OPTICAL OUTPUT
PO P1 AVERAGE POWER (PAVG) THRESHOLD CURRENT (ITH) P0 DC-COUPLED LASER MODULATION OPTICAL MODULATION AMPLITUDE (OMA)
E r = P1 / P0 Er = (2PAVG + OMA) / (2PAVG - OMA) P1 = 2PAVG Er / (Er +1) P0 = 2PAVG / (Er + 1) OMA = P1 - P0 = 2PAVG (Er - 1) / (Er + 1) = OMA / IMOD IMOD = OMA / IBIAS = ITH + (P0 x )
CURRENT INPUT
I
BIAS CURRENT (IBIAS) MODULATION CURRENT (IMOD)
Note: Assuming a 50% average input duty cycle and mark density.
DC CURRENT (IBIAS + (IMOD / 2))
Figure 5. Optical Power Relations
Design Procedure
Interfacing with VCSELs
The MAX3975 modulating output (OUT) is optimized to interface directly to the cathode of a common-anode VCSEL. No external components are required between the VCSEL cathode and the driver output. A 50 controlled-impedance transmission line with minimal length should be used between the VCSEL and the driver output. The VCSEL should be a high-speed, high-efficiency laser that requires low modulation current and generates a low voltage swing. Use a broadband supply filter at the VCSEL anode. The minimum instantaneous voltage at OUT is 0.7V. To obtain fast edge transitions and low jitter, a VCSEL, supply voltage, and packaging technology must be selected that ensures V OUT is within the operating range of the driver output.
Programming the Bias Current
For a desired laser average optical power, PAVG, the required bias current can be calculated based on the laser slope efficiency () and threshold current (ITH) using the equations in Table 1. To program the desired bias current, connect a resistor from BIASSET to VEE. See the Bias Current vs. RBIASSET graph in the Typical Operating Characteristics to select the value of RBIASSET that corresponds to the required bias current. When using an external DAC as shown in Figure 4, see the Bias Current vs. I BIASSET graph in the Typical Operating Characteristics.
Closed-Loop Operation
Closed-loop power control can be implemented by using a controller IC as shown in the Typical Application Circuit on page 1. The controller IC monitors the photodiode current then adjusts the resistance/current seen by the BIASSET pin to maintain average power of the optical output over temperature and laser lifetime. Optical modulation amplitude (OMA) control is achieved by using a temperature indexed lookup table to control the resistance/current seen by the MODSET pin. The time constant from MODSET/BIASSET to OUT is typically 175ns.
Programming the Modulation Current
For a desired optical modulation amplitude (OMA), the required modulation current can be calculated based on the laser slope efficiency () using the equations in Table 1. To program the desired modulation current, connect a resistor from MODSET to VEE. See the Modulation Current vs. R MODSET graph in the Typical Operating Characteristics to select the value of RMODSET that corresponds to the required modulation current. When using an external DAC as shown in Figure 4, see the Modulation Current vs. IMODSET graph in the Typical Operating Characteristics.
_______________________________________________________________________________________
9
10.7Gbps, +3.3V, Compact VCSEL Driver MAX3975
Safety and Power Sequencing
For safety fault protection and proper power sequencing, use a low on-resistance MOSFET between the VCSEL power supply and the VCSEL anode, as shown in the Typical Application Circuit. A power-on-reset circuit and the safety fault signal of the controller IC (if applicable) should control the MOSFET gate. The power-on-reset circuit should be designed to disable the VCSEL when the driver supply voltage is below 2.9V. This prevents the VCSEL from producing excessive optical output while the driver powers up/down. ommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the Application Note: UCSP--A Wafer-Level Chip-Scale Package available on Maxim's website at www.maximic.com/ucsp.
Applications Information
Interface Models
Figures 6, 7, 8, and 9 show simplified input and output circuits.
UCSP Assembly Considerations
The MAX3975 is packaged in a 2.5mm x 2.5mm, chipscale package (5 x 5 UCSP). Five of the solder ball positions (B3, C2, C3, C4, D3) are not populated (package code B25-4). For the latest application details on UCSP construction, dimensions, tape carrier information, PC board techniques, bump-pad layout, and recESD STRUCTURES VCC
50
50
IN+ ESD STRUCTURES VCC VCC VCC INRDIS ESD STRUCTURES
DISABLE
VEE VEE VEE
Figure 8. Simplified Data Input Structure
VCC
Figure 6. Simplified DISABLE Input Structure
VCC VCC ESD STRUCTURES
V
ESD STRUCTURES
RT OUT
MONITOR
ESD STRUCTURES
VEE VEE VEE
VEE
VEE
VEE
Figure 7. Simplified MONITOR Output Structure 10
Figure 9. Simplified Data Output Structure
______________________________________________________________________________________
10.7Gbps, +3.3V, Compact VCSEL Driver
Layout Considerations
Design a broadband supply filter that provides low impedance between 10kHz and 15GHz. Use controlledimpedance transmission lines to interface to the highspeed input and output of the MAX3975. The parasitic capacitance at BIASSET and MODSET must be less than 20pF to ensure stability of the current controls.
Chip Information
TRANSISTOR COUNT: 1387 PROCESS: SiGe Bipolar
MAX3975
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
25L, UCSP.EPS
PACKAGE OUTLINE, 5x5 UCSP 21-0096 H
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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