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19-2630; Rev 0; 10/02
6.25Gbps, 1.8V PC Board Equalizer
General Description
The MAX3785 6.25Gbps equalizer operates from a single 1.8V supply and compensates for transmissionmedium losses encountered with FR4 transmission lines. Optimized for low-voltage, high-density, DC-coupled interconnections between the line card and switch card, the MAX3785 enables a system upgrade path while maintaining a legacy rate of 2.5Gbps to 3.125Gbps. Roughly the size of two 0603 passive components, the MAX3785 easily provides placement and routing flexibility. The MAX3785 is comprised of an equalizer, limiting amplifier, and output driver. For data rates of 3.2Gbps and lower, the MAX3785 equalizes signals for spans up to 40in of FR4 board material. For data rates up to 6.25Gbps, the MAX3785 compensates for 30in of FR4 board material. The MAX3785 is coding independent, functioning equally well for 8b/10b or scrambled signals. The MAX3785 features DC-coupled current-mode logic (CML) data inputs and outputs. It is packaged in a tiny 1.5mm 1.5mm chip-scale package (USCPTM). o Single 1.8V Supply o Very Low Power, 60mW o Spans 30in with FR4 at 6.25Gbps o Operates from 1.0Gbps to 6.4Gbps o Coding Independent, 8b/10b or Scrambled o DC-Coupled CML Inputs and Outputs o Small 1.5mm x 1.5mm Footprint
Features
MAX3785
Ordering Information
PART MAX3785UBL TEMP RANGE 0C to +85C PIN-PACKAGE 6 UCSP (3 x 3)
Pin Configuration
TOP VIEW (BUMPS ON BOTTOM OF DIE)
Applications
HSBI for 6.4Gbps Double IEEE 802.3ae XAUI Double STM-16/OC-48
A1 INA2 GND A3 OUT-
MAX3785
C1 IN+ C2 VCC C3 OUT+
UCSP is a trademark of Maxim Integrated Products, Inc.
3 x 3 UCSP
Typical Application Circuit
LINE CARD BACKPLANE SWITCH CARD
MAC
1.8V VCC
SWITCH ASIC WITH SERDES
Rx
Tx 1.8V 6.25Gbps VCC
IN
MAX3785
OUT
Rx
Tx
Rx
OUT
MAX3785
IN 30in (0.75m)
Tx
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
6.25Gbps, 1.8V PC Board Equalizer MAX3785
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC to GND.................................-0.5V to +6.0V Continuous Output Current (OUT+, OUT-) .......-25mA to +25mA Input Voltage (IN+, IN-) ..............................-0.5V to (VCC + 0.5V) Operating Ambient Temperature Range ............... 0C to +85C Storage Ambient Temperature Range...............-55C to +150C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical values measured at V CC = 1.8V and T A= +25C. Specifications guaranteed over specified operating conditions.) (See Operating Conditions table.)
PARAMETER Supply Current Input Swing (IN) Input Common-Mode Voltage Range Input Return Loss Differential Input Resistance Output Swing Output Resistance Output Return Loss Output Transition Time (tr, tf) Measured differentially at data source before encountering loss (Point A in Figure 1) (Note 1) (Note 1) 100MHz to 3.2GHz, power off IN+ and INMeasured differentially at OUT+ and OUT- with 50 1% load at each side OUT+ or OUT100MHz to 3.2GHz, IN+ = high 20% to 80% (Note 2) 2.5Gbps, 3.2Gbps, 5.0Gbps; 0in to 30in FR4 400mVP-P IN 1600mVP-P Residual Deterministic Jitter (Notes 1, 3, 4) 2.5Gbps, 3.2Gbps; 40in FR4 400mVP-P IN 1600mVP-P 6.25Gbps; 0in to 30in FR4 600mVP-P IN 1600mVP-P 6.25Gbps; 0in to 30in FR4 IN = 400mVP-P Output Random Jitter Low-Frequency Cutoff Frequency Latency Maximum Bit Rate Minimum Bit Rate (Note 1) (Note 1) 6.25 (Notes 1, 2) 30 85 450 42 50 14 40 0.10 0.15 0.15 0.20 0.75 50 200 6.4 1.0 2.5 55 0.15 0.20 UI 0.25 0.30 1.0 psRMS kHz ps Gbps Gbps 400 VCC (INMAX/4) 15 100 115 800 58 CONDITIONS MIN TYP 35 MAX 55 1600 VCC (INMIN/4) UNITS mA mVP-P V dB mVP-P dB ps
Note 1: Guaranteed by design and characterization. Note 2: Using input pattern 0000011111 at 6.25Gbps. Note 3: Difference in deterministic jitter between data source and equalizer output, evaluated at 2.5Gbps, 3.2Gbps, 5Gbps, and 6.25Gbps. Pattern used: PRBS (27), ninety-six 0s, 1, 0, 1, 0, PRBS (27), ninety-six 1s, 0, 1, 0, 1. Note 4: Signal is applied differentially at input to a 6-mil wide, loosely coupled stripline. Deterministic jitter at the output of the transmission line is from media-induced loss, not from clock source modulation (see Figure 1).
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6.25Gbps, 1.8V PC Board Equalizer
Operating Conditions
PARAMETER Supply Voltage (VCC) Operating Ambient Temperature 10Hz f < 100Hz Supply Noise Tolerance Bit Rate 100Hz f < 1MHz 1MHz f 1GHz NRZ data 2.50 CONDITIONS MIN 1.71 0 TYP 1.8 25 100 40 10 6.25 Gbps mVP-P MAX 1.89 85 UNITS V C
MAX3785
PC BOARD SIGNAL SOURCE A 3in L 30in B IN <1.0pF SMA CONNECTOR <1.0pF SMA CONNECTOR C OUT
MAX3785
FR4 4.0 < r < 4.4 tan = 0.022
Figure 1. Conditions of Testing
Typical Operating Characteristics
(VCC = +1.8V, TA = +25C, unless otherwise noted. Measurements done at 6.25Gbps, 500mVP-P at the source with a test pattern: PRBS (27), ninety-six 0s, 1, 0, 1, 0, PRBS (27), ninety-six 1s, 0, 1, 0, 1. Deterministic jitter of the MAX3785 and the board was measured using Tektronix's FrameScanTM. Deterministic jitter of the system was subtracted from the measured value. Eye diagrams were acquired by FrameScan, which includes system jitter but eliminates random jitter.)
EYE DIAGRAM OF UNEQUALIZED SIGNAL AFTER 30in OF FR4
MAX3785 toc01
EYE DIAGRAM OF EQUALIZED SIGNAL AFTER 30in OF FR4
MAX3785 toc02
EYE DIAGRAM OF EQUALIZED SIGNAL AFTER 30in OF FR4
MAX3785 toc03
70mV/div
70mV/div
70mV/div
30ps/div TEST PATTERN, 6.25Gbps, WITHOUT RANDOM JITTER, INCLUDING 13ps SYSTEM JITTER
30ps/div TEST PATTERN, 6.25Gbps, WITHOUT RANDOM JITTER, INCLUDING 13ps SYSTEM JITTER
30ps/div 210 - 1 PRBS, 6.25Gbps, WITHOUT RANDOM JITTER, INCLUDING 13ps SYSTEM JITTER
FrameScan is a trademark of Tektronix.
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6.25Gbps, 1.8V PC Board Equalizer MAX3785
Typical Operating Characteristics (continued)
(VCC = +1.8V, TA = +25C, unless otherwise noted. Measurements done at 6.25Gbps, 500mVP-P at the source with a test pattern: PRBS (27), ninety-six 0s, 1, 0, 1, 0, PRBS (27), ninety-six 1s, 0, 1, 0, 1. Deterministic jitter of the MAX3785 and the board was measured using Tektronix's FrameScan. Deterministic jitter of the system was subtracted from the measured value. Eye diagrams were acquired by FrameScan, which includes system jitter but eliminates random jitter.)
EYE DIAGRAM OF UNEQUALIZED SIGNAL AFTER 30in OF FR4
MAX3785 toc04
EYE DIAGRAM OF EQUALIZED SIGNAL AFTER 30in OF FR4
MAX3785 toc05
EYE DIAGRAM OF EQUALIZED SIGNAL AFTER 30in OF FR4
MAX3785 toc06
70mV/div
70mV/div
70mV/div
50ps/div TEST PATTERN, 3.125Gbps, WITHOUT RANDOM JITTER, INCLUDING 13ps SYSTEM JITTER
50ps/div TEST PATTERN, 3.125Gbps, WITHOUT RANDOM JITTER, INCLUDING 13ps SYSTEM JITTER
50ps/div CRPAT, 3.125Gbps, WITHOUT RANDOM JITTER, INCLUDING 13ps SYSTEM JITTER
EQUALIZER OPERATING CURRENT vs. TEMPERATURE
90 80 70 CURRENT (mA) JITTER (ps) 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 TEMPERATURE (C)
MAX3785 toc07
DETERMINISTIC JITTER vs. BOARD LENGTH (FR4) (INPUT LEVEL OF 500mVP-P, TEST PATTERN)
65 60 55 50 45 40 35 30 25 20 15 10 5 10 6Gbps
MAX3785 toc08
DETERMINISTIC JITTER vs. SIGNAL LEVEL (TEST PATTERN, 30in OF FR4 BOARD)
MAX3785 toc09
100
20
15 2.5Gbps JITTER (ps) 10 3.125Gbps
3.125Gbps
5 5Gbps 0 15 20 25 30 35 40 0.4
6.4Gbps
2.5Gbps
5Gbps 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
BOARD LENGTH (in)
DIFFERENTIAL SIGNAL LEVEL (VP-P)
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6.25Gbps, 1.8V PC Board Equalizer MAX3785
Typical Operating Characteristics (continued)
(VCC = +1.8V, TA = +25C, unless otherwise noted. Measurements done at 6.25Gbps, 500mVP-P at the source with a test pattern: PRBS (27), ninety-six 0s, 1, 0, 1, 0, PRBS (27), ninety-six 1s, 0, 1, 0, 1. Deterministic jitter of the MAX3785 and the board was measured using Tektronix's FrameScan. Deterministic jitter of the system was subtracted from the measured value. Eye diagrams were acquired by FrameScan, which includes system jitter but eliminates random jitter.)
DETERMINISTIC JITTER vs. DATA RATE FOR 10in OF FR4 BOARD (INPUT LEVEL OF 500mVP-P)
MAX3785 toc10
DETERMINISTIC JITTER vs. DATA RATE FOR 20in OF FR4 BOARD (INPUT LEVEL OF 500mVP-P)
MAX3785 toc11
DETERMINISTIC JITTER vs. DATA RATE FOR 30in OF FR4 BOARD (INPUT LEVEL OF 500mVP-P)
CRPAT TEST PATTERN
MAX3785 toc12
30 25 210 - 1 20 JITTER (ps) 15 10 K28.5 5 27 - 1 0 2.5 3.5 4.5 5.5 6.5 DATA RATE (Gbps) TEST PATTERN
30 210 - 1 25 CRPAT 20 JITTER (ps) 15 10 5 0 2.5 3.5 4.5 5.5 6.5 DATA RATE (Gbps) TEST PATTERN K28.5 27 - 1
30 25 20 JITTER (ps) 15 10 27 - 1 5 0 2.5 3.5 4.5 5.5 6.5 DATA RATE (Gbps)
CRPAT
210 - 1
K28.5
EQUALIZER INPUT RETURN GAIN (SDD11) (INPUT SIGNAL LEVEL = -40dBm, POWER OFF)
MAX3785 toc13
EQUALIZER INPUT RETURN GAIN (SDD22) (INPUT SIGNAL LEVEL = -40dBm, IN+ HIGH)
MAX3785 toc14
30 20 10 GAIN (dB) 0 -10 -20 -30 -40 100 1000 FREQUENCY (MHz)
30 20 10 GAIN (dB) 0 -10 -20 -30 -40
10,000
100
1000 FREQUENCY (MHz)
10,000
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6.25Gbps, 1.8V PC Board Equalizer MAX3785
Pin Description
PIN A1 A2 A3 C1 C2 C3 NAME INGND OUTIN+ VCC OUT+ Negative Data Input, CML Supply Ground Negative Data Output, CML Postive Data Input, CML Supply Voltage Positive Data Output, CML FUNCTION
Functional Description
The MAX3785 6.25Gbps PC board equalizer consists of an equalizer, limiting amplifier, offset driver, and offset cancellation circuit (see Figure 2). The equalizer block compensates for the attenuation caused by the PC board. The limiting amplifier squares up the signal at the output of the equalizer block. The offset cancellation circuit corrects for internal offset in the limiting amplifier to minimize pulse-width distortion. This introduces a low-frequency cutoff. The data must achieve a 50% mark/space ratio in less than 100s. The specified minimum differential input must be maintained to avoid oscillation.
Package Description
LIMITER IN+ EQUALIZER IN-
OUTPUT BUFFER OUT+ OUT-
MAX3785
OFFSET ADJUST
Input and Output Structures
An equivalent DC input circuit is shown in Figure 3. It has an equivalent DC differential input resistance of 100. The output buffer is implemented using currentmode logic (CML), as shown in Figure 4.
Figure 2. Functional Diagram of the MAX3785
The chip-scale package (UCSP) has a bump pitch of 0.5mm (19.7 mils) and a bump diameter of 0.3mm (12 mils). Lay out the solder pad spacing on 0.5mm (19.7 mils), a pad size of 0.25mm (10 mils) and a solder mask opening of 0.33mm (13 mils). Round or square pads are permissible. For detailed information on UCSP layout and handling, go to Maxim's website, www.maxim-ic.com. The enclosed package description was accurate at the time of publication. For the MAX3785, all of the balls shown in row B of the drawing are unpopulated. Go to Maxim's website for the latest package information.
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6.25Gbps, 1.8V PC Board Equalizer MAX3785
VCC
50
50
37 IN+ 28 37 INESD STRUCTURES
37
37
OFFSET CORRECTION
Figure 3. Equalizer Input DC Equivalent Circuit
VCC
50
50 OUT+ OUT-
ESD STRUCTURES
Figure 4. CML Output Equivalent Circuit
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6.25Gbps, 1.8V PC Board Equalizer MAX3785
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
Note: For the MAX3785, all of the balls shown in row B of the drawing are unpopulated.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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