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Multichannel Network Interface Controller for HDLC with Extensions MUNICH32X PEB 20321 Version 2.1 Delta Sheet 02.98
This Delta Sheet describes the differences between MUNICH32X Version 2.1 (Data Sheet 01.98 DS1) and MUNICH32X V1.2 (Data Sheet 05.97 T2032-1V11-7600). 1 1.1 External Bus Modes De-multiplexed Bus Modes
The Address Latch Enable (LALE) signal is used to mark the address phase in Multiplexed Bus Modes and triggers external latches to capture the current address with its falling edge. After a period of time the address is removed and data transfer cycle starts. Although this signal was generated by MUNICH32X Version 1.x independent of the selected bus mode it is obsolete and thus not supported by MUNICH32X V2.1 in Demultiplexed Bus Mode.
Address Data In LRD Data Out LWR
ITD10349
Figure 52 De-multiplexed Bus Cycle Signal LALE is deleted from figure 52 describing the de-multiplexed bus cycle.
Siemens Semiconductor Group
(c) Siemens AG 1998. All Rights Reserved.
DS 1
Please note that any information contained in this publication may be subject to change. Siemens reserves the right to make changes to or to discontinue any product or service identified in this publication without notice. Please contact our regional offices to receive the latest version of the relevant information to verify, before placing orders, that the information being relied upon is current. Revision History: Previous Version: Major Changes:
PEB 20321
2
TMA Mode
In case of using subchanneling by fill masks the MUNICH32X supports two different modes of operation in Transparent Mode A (TMA). These modes are selected by bit 'CRC' in the channel configuration. CRC = '0': Data is transmitted transparently only in bit positions selected by the transmit fill mask (corresponding fill mask bit equal '1'). Masked bit positions are driven Tristate 'Z'. In receive direction bits are received from bit positions selected by the receive fill mask (corresponding fill mask bit equal '1') only. Receive data is grouped to octets and stored in memory transparently (no gaps). CRC = '1': In transmit direction each data octet is masked with the transmit fill mask. Masked bit positions are overwritten with Tristate 'Z' when transmitted. In receive direction the receive fill mask has to be set to 0xFF. The entire 8 bit time slot is received and stored byte aligned in memory. It is the software responsibility to mask received data octets as needed by the application. 3 Device ID
The Device ID has changed in the PCI Configuration Space and the boundary scan pattern. For detailed information please refer to the Data Sheet V2.1 01.98 DS 1. 4 Pin Description
Pin 10 and Pin 61 are labled as 'N.C.1' and 'N.C.2'. Due to the Pull-Up recommendation in the Data Sheet 01.98 these pins should be treated and labled as 'Reserved' and connected as recommended.
Semiconductor Group
2
02.98

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