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Integrated Circuit Systems, Inc.
ICSSSTU32866
Advance Information
25-Bit Configurable Registered Buffer
Recommended Application: * DDR2 Memory Modules * Provides complete DDR DIMM logic solution with ICS97U877 Product Features: * 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality * Supports SSTL_18 JEDEC specification on data inputs and outputs * Supports LVCMOS switching levels on CSR# and RESET# inputs * Low voltage operation VDD = 1.7V to 1.9V * Available in 96 BGA package
Pin Configuration
1 A B C D E F G H J K L M N P 2 3 4 5 6
Functionality Truth Table
I nputs RST# H H H H H H H H H H H H L DCS# L L L L L L H H H H H H X or Floating CSR# L L L H H H L L L H H H X or Floating L or H X or Floating L or H X or Floating L or H L or H L or H L or H L or H L or H CK CK# Dn, DODT, DCK E L H X L H X L H X L H X X or Floating Qn L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L Outputs QCS# L L Q0 L L Q0 H H Q0 H H Q0 L QODT, QCKE L H Q0 L H Q0 L H Q0 L H Q0 L
R T
96 Ball BGA (Top View)
0850--08/27/03 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICSSSTU32866
Advance Information
Ball Assignments
25 bit 1:1 Register
A DCKE B D2 C D3 D DODT E D5
PPO D15 D16 QERR# D17 V REF GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD V REF V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD V DD QCKE Q2 Q3 QODT Q5 Q6 C1 QCS# ZOH Q8 Q9 Q10 Q11 Q12 Q13 Q14 NC Q15 Q16 NC Q17 Q18 C0 NC ZOL Q19 Q20 Q21 Q22 Q23 Q24 Q25
D18 F D6 G PAR_IN RST#
H CK J CK# K D8 L
D9
DCS# CSR# D19 D20 D21 D22 D23 D24 D25
M D10 N D11 P D12 R D13 T D14 1
2
3
4
5
6
C0 = 0, C1 = 0 14 bit 1:2 Registers
A DCKE B D2 C D3 D DODT E D5
PPO NC NC QERR# NC V REF GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD V REF V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD V DD QCKEA Q2A Q3A QODTA Q5A Q6A C1 QCSA# ZOH Q8A Q9A Q10A Q11A Q12A Q13A Q14A QCKEB Q2B Q3B QODTB Q5B Q6B C0 QCSB# ZOL Q8B Q9B Q10B Q11B Q12B Q13B Q14B
A D1 B D2 C D3 D D4 E D5
PPO NC NC QERR# NC
V REF GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD V REF
V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD V DD
Q1A Q2A Q3A Q4A Q5A Q6A C1 QCSA# ZOH Q8A Q9A Q10A QODTA Q12A Q13A QCKEA
Q1B Q2B Q3B Q4B Q5B Q6B C0 QCSB# ZOL Q8B Q9B Q10B QODTB Q12B Q13B QCKEB
NC F D6 G PAR_IN RST#
NC F D6 G PAR_IN RST#
H CK J K D8 L D9 M D10 N D11 P D12 R D13 T D14 1
CK#
DCS# CSR# NC NC NC NC NC NC NC
H CK J CK# K D8 L
D9
DCS# CSR# NC NC NC NC NC NC NC
M D10 N DODT P D12 R D13 T DCKE 1
2
3
4
5
6
2
3
4
5
6
Register A (C0 = 0, C1 = 1)
Register B (C0 = 1, C1 = 1)
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ICSSSTU32866
Advance Information
General Description
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTU32866 operates from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). A - Pair Configuration (CO1 = 0, CI1 = 1 and CO2 = 0, CI2 = 1) Parity that arrives one cycle after the data input to which it applies is checked on the PAR_IN of the first register. The second register produces to PPO and QERR# signals. The QERR# of the first register is left floating. The valid error information is latched on the QERR# output of the second register. If an error occurs QERR# is latched low for two cycles or until Reset# is low.
B - Single Configuration (CO = 0, C1 = 0)
The device supports low-power standby operation. When the reset input (RST#) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RST# is low all registers are reset, and all outputs are forced low. The LVCMOS RST# and Cn inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RST# must be held in the low state during power up. In the DDR-II RDIMM application, RST# is specified to be completely asynchronous with respect to CK and CK#. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST# until the input receivers are fully enabled, the design of the ICSSSTU32866 must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS# and CSR# inputs are high. If either DCS# or CSR# input is low, the Qn outputs will function normally. The RST input has priority over the DCS# and CSR# control and will force the outputs low. If the DCS#-control functionality is not desired, then the CSR# input can be hardwired to ground, in which case, the setup-time requirement for DCS# would be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC).
Parity and Standby Functionality Truth Table
Inputs
Reset# H H H H H H H H L DCS# L L L L H H H X CSR# X X X X L L H X CK L or H CK# L or H X or Floating Sum of Inputs = H (D1 - D25) Even Odd Even Odd Even Odd X X X or Floating PAR_IN L L H H L H X X X or Floating
Outputs
PPO L H H L L H PPO0 PPO0 L QERR# H L L H H L QERR0# QERR0# H
X or X or X or Floating Floating Floating
1. CO = 0 and CI = 0, Data inputs are D2, D3, D5, D6, D8 - D25. CO = 0 and CI = 1, Data inputs are D2, D3, D5, D6, D8 - D14 CO = 1 and CI = I, Data inputs are D1 - D6, D8 - D10, D12, D13 2. PAR_IN arrives one clock cycle after the data to which it applies when CO = 0. 3. PAR_IN arrives two clock cycles after the data to which it applies when CO = 1. 4. Assume QERR# is high at the CK and CK# crossing. If QERR# is low it stays latched low for two clock cycles on until Reset# is low.
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ICSSSTU32866
Advance Information
Ball Assignment
Terminal Name GND V DD VREF ZOH ZOL CK CK C0, C1 RST# CSR#, DCS# D1 - D25 DODT DCKE Q1 - Q25 QCS# QODT QCKE PPO PAR_IN QERR# Ground Power supply voltage Input reference voltage Reserved for future use Reserved for future use Positive master clock input Negative master clock input Configuration control inputs Asynchronous reset input - resets registers and disables VREF data and clock differential-input receivers Description Electrical Characteristics Ground input 1.8V nominal 0.9V nominal Input Input Differential input Differential input LVCMOS inputs LV C M O S i n p u t
Chip select inputs - disables D1 - D24 outputs switching when both inputs SSTL_18 input are high Data input - clock in on the crossing of the rising edge of CK and the falling edge of CK# The outputs of this register bit will not be suspended by the DCS# and CSR# control The outputs of this register bit will now be suspended by the DCS# and CSR# control Data ouputs that are suspended by the DCS# and CSR# control Data output that will not be suspended by the DCS# and CSR# control Data output that will not be suspended by the DCS# and CSR# control Data output that will not be suspended by the DCS# and CSR# control Par tial parity out indicates off parity of inputs D1 - D25. Parity input arrives one clock cycle after the corresponding data input Output error bit-generated one clock cycle after the corresponding data output SSTL_18 input SSTL_18 input SSTL_18 input 1.8V CMOS 1.8V CMOS 1.8V CMOS 1.8V CMOS 1.8V CMOS SSTL_18 input Open drain output
0850--08/27/03
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ICSSSTU32866
Advance Information
Block Diagram for 1:1 mode (positive logic)
RST#
CK CK# VREF
DCKE
D C1 R QCKEA
DODT
D C1 R QODTA
DCS#
1D C1 R QCSA#
CSR#
D1
0 1 1D C1 R Q1B *
Q1A
To 21 Other Channels
*Note: Disabled in 1:1 configuration
0850--08/27/03
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ICSSSTU32866
Advance Information
Block Diagram for 1:2 mode (positive logic)
RST#
CK CK# VREF
DCKE
1D C1 R
QCKEA
QCKEB*
DODT
1D C1 R
QODTA
QODTB*
DCS#
1D C1 R
QCSA#
QCSB#*
CSR#
D1
0 1 1D C1 R Q1B *
Q1A
To 10 Other Channels
*Note: Disabled in 1:1 configuration
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ICSSSTU32866
Advance Information
Parity Functionality Block Diagram
RST# CK CK# VREF DATA INPUT* DATA OUTPUT*
Parity Logic
PPO
PAR_IN
QERR#
* Register Configurations
DATA INPUT: D2, D3, D5, D6, D8 - D25 D2, D3, D5, D6, D8 - D14 D1 - D6, D8 D10, D12, D13 DATA OUTPUT: D2, D3, D5, D6, D8 - D25 D2, D3, D5, D6, D8 - D14 D1 - D6, D8 D10, D12, D13 CO 0 CI 0
0
1
1
1
0850--08/27/03
7
ICSSSTU32866
Advance Information
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clamp Current . . . . . . . . . . . . . . . . . . . . Output Clamp Current . . . . . . . . . . . . . . . . . . . Continuous Output Current . . . . . . . . . . . . . . . VDDQ or GND Current/Pin . . . . . . . . . . . . . . . Package Thermal Impedance 3
...............
-65C to +150C -0.5 to 2.5V -0.5 to VDD + 2.5V -0.5 to VDDQ + 0.5 50 mA 50mA 50mA 100mA 36C
Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level V0 >VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Recommended Operating Conditions
PARAMETER VDDQ VREF VTT VI VIH (DC) VIH (AC) VIL (DC) VIL (DC) VIH VIL VICR VID IOH IOL TA
1
DESCRIPTION I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage RESET#, Input High Voltage Level C0, C1 Input Low Voltage Level Common mode Input Range CLK, CLK# Differential Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature
MIN TYP 1.7 1.8 0.49 x VDD 0.5 x V DD VREF - 0.04 VREF 0 VREF + 0.125 VREF + 0.250 VREF + 0.250 0.65 x VDDQ 0.675 0.600
MAX 1.9 0.51 x V DD VREF + 0.04 VDDQ
UNITS
V REF - 0.125
V
0.35 x VDDQ 1.125 -8 8 70
mA C
0
Guaranteed by design, not 100% tested in production. Note: Reset# and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless Reset# is low.
0850--08/27/03
8
ICSSSTU32866
Advance Information
Electrical Characteristics - DC
TA = 0 - 70C; V DD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated) SYMBOL V IK V OH PARAMETERS I I = -18mA I OH = -100A I OH = -16mA I OL = 100A I OL = 16mA All Inputs VI = VDD or GND Standby (Static) RESET# = GND VI = VIH(AC) or VIL(AC), Operating (Static) RESET# = VDD RESET# = VDD, Dynamic operating VI = VIH(AC) or VIL(AC), (clock only) CLK and CLK# switching 50% duty cycle. IO = 0 RESET# = VDD, VI = VIH(AC) or VIL (AC), Dynamic Operating CLK and CLK# switching (per each data input) 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle Output High I OH = -20mA Output Low I OL = 20mA [rOH - rOL] each I O = 20mA, TA = 25 C separate bit Data Inputs VI = VREF 350mV CLK and CLK# VICR = 1.25V, VI(PP) = 360mV RESET# VI = VDDQ or GND 1.7V - 1.9V 1.7V 1.7V - 1.9V 1.7V 1.9V 1.9V VDDQ 0.2 1.95 0.2 0.35 5 0.01 TBD CONDITIONS V DDQ MIN TYP MAX -1.2 UNITS
V
V OL II I DD
A A mA
TBD
/clock MHz
I DDD
1.8V TBD A/ clock MHz/data
rOH rOL rO(D) Ci
4 2.5 2 2.5 3.5 3 pF
Notes: 1 - Guaranteed by design, not 100% tested in production.
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7) V DD = 1.8V 0.1V PARAMETER UNIT MIN MAX dV/dt_r 1 4 V/ns dV/dt_f 1 4 V/ns dV/dt_ 1 1 V/ns 1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
0850--08/27/03
9
ICSSSTU32866
Advance Information
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted) VDD = 1.8V 0.1V SYMBOL PARAMETERS MIN MAX Clock frequency 300 f clock 0.75 Data before CLK, CLK# 0.9 DCS# before CK, CK#, 0.7 CSR# high CSR# before CK, CK#, 0.7 tS Setup time DCS# high DCS# before CK, CK#, 0.5 CSR# low DODT, DCKE and Q before 0.5 CK, CK# PAR_IN before CK, CK# 0.5 DCS#, DODT, DCKE and Q Hold time 0.50 after CK, CK# tH PAR_IN after CK, CK# 0.50 Hold time 1 - Guaranteed by design, not 100% tested in production. Notes: 2 - For data signal input slew rate of 1V/ns. 3 - For data signal input slew rate of 0.5V/ns and < 1V/ns. 4 - CLK/CLK# signal input slew rate of 1V/ns. UNITS MHz
ns
ns ns
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted) Measurement Symbol Parameter MIN MAX Conditions fmax tPDM Max input clock frequency 270 1.41 0.5 1.2 1 215 1.8 3 2.4 2.35 3 3 3 Units MHz ns ns ns ns ns ns ns ns
Propagation delay, single CK to CK# QN bit switching Propagation delay CK to CK# to PPO tPD Low to High propagation t LH CK to CK# to QERR# delay High to low propagation CK to CK# to QERR# t HL delay Propagation delay CK to CK# QN t PDMSS simultaneous switching High to low propagation tPHL Reset# to QN delay High to low propagation Reset# to PPO tPHL delay Low to High propagation Reset# to QERR# tPLH delay 2. Guaranteed by design, not 100% tested in production.
0850--08/27/03
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ICSSSTU32866
Advance Information
VDD
DUT td = 350ps TL =50 CK Inputs Test Point RL = 100 Test Point VCMOS RST# Inp ut t in act IDD (see Note 2) LOAD CIRCUIT VDD VDD/2 VDD/2 0V t act 90% 10% VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES tw Inpu t VICR VICR LVCMOS RST# Input VIH VDD /2 t RPHL t su Inpu t VREF th VREF VIH VOH Output VTT VOL VIL VID Output VTT V TT CK VICR CK t PLH t PHL VOH VOL VICR CK# CK TL=350ps, 50 Out CL = 30 pF (see Note 1) RL = 1000 Test Point RL = 1000
VID
VOLTAGE WAVEFORMS - PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS - PULSE DURATION VID CK VICR CK
VIL VOLTAGE WAVEFORMS - SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS - PROPAGATION DELAY TIMES
Figure 6 -- Parameter M easurement I nfor mation (V DD = 1.8 V 0.1 V)
Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: PRR 10 MHz, Zo=50, input slew rate = 1 V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VREF = VDD/2 6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600 mV 9. tPLH and tPHL are the same as tPDM.
0850--08/27/03
11
ICSSSTU32866
Advance Information
VDD DUT RL = 50 Out C L = 10 pF (see Note 1) Test Point
LOAD CIRCUIT - HIGH-TO-LOW SLEW-RATE MEASUREMENT Output 80% 20% dv _f dt _f VOL VOH
VOLTAGE WAVEFORMS - HIGH-TO-LOW SLEW-RATE MEASUREMENT
DUT
Out CL = 10 pF (see Note 1)
Test Point RL = 50
LOAD CIRCUIT - LOW-TO-HIGH SLEW-RATE MEASUREMENT dv _r dt _r 80% 20% Output VOL VOLTAGE WAVEFORMS - LOW-TO-HIGH SLEW-RATE MEASUREMENT VOH
Figure 7 -- Output Slew-Rate M easurement I nfor mation (V DD = 1.8 V 0.1 V)
Notes: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified).
0850--08/27/03
12
ICSSSTU32866
Advance Information
C Seating Plane A1 T b REF
D
Numeric Designations for Horizontal Grid 4321 A B C D
Alpha Designations for Vertical Grid (Letters I, O, Q & S not used)
d TYP
- e - TYP TOP VIEW
E
h TYP 0.12 C
ALL DIMENSIONS IN MILLIMETERS
c REF
- e - TYP
D
E
T Min/Max
e
----- BALL GRID ----HORIZ VERT
Max. TOTAL
d Min/Max
h Min/Max 0.31/0.41 0.25/0.41 0.15/0.21
REF. DIMENSIONS b c 0.80 0.75 0.575 0.75 0.75 0.625
16.00 Bsc 5.50 Bsc 1.30/1.50 0.80 Bsc 6 19 114 0.40/0.50 13.50 Bsc 5.50 Bsc 1.30/1.50 0.80 Bsc 6 16 96 0.40/0.50 7.00 Bsc 4.50 Bsc 0.86/1.00 0.65 Bsc 6 10 60 0.35/0.45 Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.
* Source Ref.: JEDEC Publication 95, 10-0055C
MO-205
Ordering Information
ICSSSTU32866yHT
Example:
ICS XXXX y H - T
Designation for tape and reel packaging Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0850--08/27/03
13

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