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Integrated Circuit Systems, Inc.
ICS9212-03
Direct RambusTM Clock Generator
General Description
The ICS9212-03 is a High-speed clock generator providing 400 MHz differential clock source for direct RambusTM memory system. It includes DDLL (Distributed Delay locked loop) and phase detection mechanism to synchronize the direct RambusTM channel clock to an external system clock. ICS9212-03 provides a solution for a broad range of Direct Rambus memory applications. The device works in conjunction with the ICS9250-09. The ICS9212-03 power management support system turns "off" the RambusTM channel clock to minimize power consumption for mobile and other power -sensitive applications. In "clock off" mode the device remains "on" while the output is disabled, allowing fast transitions between clock-off and clock -on states. In "power down" mode it completely powers down for minimum power dissipation. The ICS9212-03 meets the requirements for input frequency tracking when the input frequency clock is using Spread Spectrum clocking and also the optimum bandwidth is maintained while attenuating the jitter of the reference signal.
Features
* * * * * Compatible with all Direct RambusTM based IC s Up to 400 MHz differential clock source for direct RambusTM memory system Cycle to cycle jitter is less than 50ps 3.3 + 5% supply Synchronization flexibility: Supports Systems that need clock domains of Rambus channel to synchronize with system or processor clock, or systems that do not require synchronization of the Rambus clock to another system clock Excellent power management support REFCLK input is from the ICS9250-09.
* *
Block Diagram
BUSCLK_STOP# PD# FS(0:1) Test MUX GND PLLclk Refclk B Bypass MUX Bypclk
Pin Configuration
VDDREF REFCLK VDD1 GND1 GND3 PCLK/M SYNCLK/N GND2 VDD2 BUSCLKT VDDPD BUSCLKC BUSCLK_STOP# PD# 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 FS0 FS1 VDD-OUT GND-OUT BUSCLKT N/C BUSCLKC GND-OUT VDD-OUT MULTI0 MULTI1 GND3
PLL
A
Phase Aligner
PAclk GND
Multi(0:1) Pclk/M Synclk/N
Phase Detector
2
24-Pin 150 Mil SSOP
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ICS9212-03
ICS9212-03
Pin Descriptions
Pin #
1 2 3 4 5, 13 6,7 8 9 10 11 12 14,15 16 17 18 19 20 21 22 24, 23
Name
VDDREF REFCLK VDD1 GND1 GND3 PCLK/M, SYNCLK/N GND2 VDD2 VDDPD BUSCLK_ STOP# PD# MULTI (0:1) VDD_OUT GND_OUT BUSCLKC N/C BUSCLKT GND_OUT VDD_OUT FS(0:1)
Type
REFV IN PWR PWR PWR IN PWR PWR REFV IN IN IN PWR PWR OUT N/C OUT PWR PWR IN
Description
Reference voltage for refclk, to be connected to CK133 Reference clock, to be connected to CK133 3.3 V power supply used for PLL Ground for PLL Ground for control inputs Phase controller input, used to drive a phase aligner that adjusts the phase of the busclk. Ground for phase aligner 3.3 V power supply used for phase aligner Reference voltage for phase detector inputs connected to the controller Active low output enable/disable 3.3V CMOS active low power down, the device is powered down when the "(PD#) =0" 3.3V CMOS PLL Multiplier select, logic for selecting the multiply ratio for the PLL from the input REFCLK 3.3V supply for clock out puts Ground for clock outputs Out put clock connected to the Rambus channel. This output is the complement of BUSCLK NOT USED Out put clock connected to the Rambus channel. This output is the true component of BUSCLK Ground for clock outputs 3.3V supply for clock out puts 3.3V CMOS Mode control, used in selecting bypass, test, normal, and output test (OE)
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ICS9212-03
PLL Divider Selection and PLL Values (PLLCLK = REFCLK*A/B)
Mult0 0 0 1 1 Mult1 0 1 0 1 A 4 6 16 8 B 1 1 3 1 PLLCLK for REFCLK=50MHz 200 300 266.7 400 PLLCLK for REFCLK=66.67MHz 266.68 400.02 355.57 Reserved
Bypass and Test Mode Selections
Mode Normal Bypass Test FS0 0 1 1 FS1 0 0 1 Bypclk (int.) Gnd PLLclk Refclk BusClk PAclk PLLclk Refclk BusClkB PAclkB PLLclkB RefclkB
Power Management Modes
State NORMAL Clk Off Powerdown PwrDnB 1 1 0 StopB 1 0 X
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ICS9212-03
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics-input/supply/Outputs
Parameters Supply Voltage Refclk Input cycle time Input cycle-to-cycle Jitter Input Duty cycle over 10k cycles Input frequency of modulation Modulation index Phase detector input cycle time at PDclk/M & Synclk/N Initial phase error at phase detector inputs Phase detector input duty cycle over 10k cycles Input rise & fall times ( measured at 20%-80% of input voltage) for PDCLK/M & SYNCLK/N,&REfCLK Input capacitance at PDCLK/M,Synclk/N,&REFCLK Input Capacitance matching at PCLK/M & SYNCLK/N Input capacitance at CMOS pins Input (CMOS) signal low voltage Input (CMOS) signal high voltage REFCLK input low voltage REFCLK input high voltage Input signal low voltage for PD inputs and STOP Input signal high voltage for PD inputs and STOP Input supply referance for REFCLK Input supply referance vfor PD inputs Phase detector phase error for distributed loop measured at PDCLK/M & SYNCLK/N(rising Cycle cycle time Cycle-to-cycle jitter at Busclk/BUSCLKB Total jitter over 2,3, or 4clock cycles Phase aligner, phase step size (BSCLK/BUSCLKB) PLL out put phase error when tracking SSC Out put crossing-point voltage Output voltage swing Output high voltage Out put duty cycle over 10k cycle Output cycle -to-cycle duty cycle error Output rise & fall times ( measured at 20%-80% of output voltage) Difference between rise and fall times on a single device(20%-80%)
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Symbol VDD tCYCLE,IN tJ,IN DCIN Fm,in PM,IN t CYCLE,PD Terr,init DCIN,PD TIR,TIF CIN,PD DCIN,PD CIN,CMOS VIL VIH VIL,R VIH,R VIL,PD VIH,PD VDD,IR VDDI,PD tERR,PD tCYCLE tJ tJ tSTEP tERR,SSC VX VCOS VH DC tDC,ERR t CR,tCF t CR,CF
Min 3.15 10 40% 30 0.25 30 -0.5 25% 0.7 0.7 0.7 1.3 1.3 -100 2.5 1 -100 1.3 0.4 40% 300 -
Max 3.45 40 250 60% 33 0.5 100 0.5 75% 1 7 0.5 10 0.3 0.3 0.3 3.3 3.3 100 3.75 50 100 100 1.8 0.6 2 60% 50 500 100
Unit V ns ps t CYCLE KHz % ns tCYCLE,PD tCYCLE,PD ns pF pF pF Vdd Vdd Vddi,R Vddi,R Vddi,PD Vddi,PD V V ps ns ps ps ps ps V V V t CYCLE ps psd ps
4
ICS9212-03
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Capacitor Values: C3 : 100pF ceramic All unmarked capacitors are 0.01F ceramic Connections to VDD:
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ICS9212-03
SYMBOL A A1 A2 b c D E E1 e L N ZD VARIATIONS N 24 10-0032 D mm. MIN 8.55 MAX 8.75
150 mil SSOP (QSOP) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 1.35 1.75 .053 .069 0.10 0.25 .004 .010 -1.50 -.059 0.20 0.30 .008 .012 0.18 0.25 .007 .010 SEE VARIATIONS SEE VARIATIONS 5.80 6.20 .228 .244 3.80 4.00 .150 .157 0.635 BASIC 0.025 BASIC 0.40 1.27 .016 .050 SEE VARIATIONS SEE VARIATIONS 0 8 0 8 SEE VARIATIONS SEE VARIATIONS
ZD (Ref) 0.84
D (inch) MIN .337 MAX .344
ZD (Ref) .033
Reference Doc.: JEDEC Publication 95, MO-137
Ordering Information
ICS9212yF-03LF-T
Example:
ICS XXXX y F - PP LF - T
Designation for tape and reel packaging RoHS Compliant (Optional) Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers) Prefix ICS, AV = Standard Device
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ICS9212-03
Revision History
Rev. F G Issue Date Description 5/20/2005 Added LF Ordering Information. 5/24/2005 Corrected LF Ordering Information. Page # 6 6
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