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Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/ LVTTL CLOCK GENERATOR W/POLARITY CONTROL
FEATURES
* 20 LVCMOS/LVTTL outputs, 7 typical output impedance * 1 LVCMOS/LVTTL clock input * Maximum output frequency: 250MHz * Selectable inverting and non-inverting outputs * Bank enable logic allows unused banks to be disabled in reduced fanout applications * Output skew: 300ps (maximum) * Part-to-part skew: 700ps (maximum) * Bank skew: 250ps (maximum) * Multiple frequency skew: 350ps (maximum) * 3.3V or mixed 3.3V input, 2.5V output operating supply * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
ICS8701-01
GENERAL DESCRIPTION
The ICS8701-01 is a low skew, /1, /2 LVCMOS/ LVTTL Clock Generator and a member of the HiPerClockSTM HiPerClockSTMfamily of High Performance Clock Solutions from ICS. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines.
ICS
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The master reset/output enable input, nMR/OE, resets the internal dividers and controls the active and high impedance states of all outputs. The output polarity inputs, INV0:1, control the polarity (inverting or non-inverting) of the outputs of each bank. Outputs QA0-QA4 are inverting for every combination of the INV0:1 input. The timing relationship between the inverting and non-inverting outputs at different frequencies is shown in the Timing Diagrams. The ICS8701-01 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics make the ICS8701-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
/1
1 0
PIN ASSIGNMENT
GND QB2 GND QB3 VDDOB QB4 QC0 VDDOC QC1 GND QC2 GND
CLK DIV_SELA
/2
QA0:QA4 QC3 VDDOC QC4 QD0 VDDOD QD1 GND QD2 GND QD3 VDDOD QD4
1 0
QB0:QB4
DIV_SELB
1 0
QC0:QC4
DIV_SELC
1 0
QD0:QD4
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS8701-01
QB1 VDDOB QB0 QA4 VDDOA QA3 GND QA2 GND QA1 VDDOA QA0
DIV_SELD nMR/OE INV0 INV1 Output Polarity Control
48-Pin LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
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REV. E DECEMBER 15, 2003
DIV_SELA DIV_SELB CLK GND VDD INV0 GND INV1 VDD nMR/OE DIV_SELC DIV_SELD
8701AY-01
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/ LVTTL CLOCK GENERATOR W/POLARITY CONTROL
Type Output Power Output Power Power Input Input Input Power Input Input Input Input Output Power Output Power Description Bank C outputs. LVCMOS interface levels. 7 typical output impedance. Output Bank C supply pins. Bank D outputs. LVCMOS interface levels. 7 typical output impedance. Output Bank D supply pins. Power supply ground. Pullup Controls frequency division for Bank D outputs. LVCMOS interface levels. Pullup Controls frequency division for Bank C outputs. LVCMOS interface levels. Master Reset and output enable. When HIGH, output drivers are Pullup enabled. When LOW, output drivers are in HiZ and dividers are reset. LVCMOS interface levels. Core supply pins. Pullup Determines polarity of outputs by banks. LVCMOS interface levels. Pullup LVCMOS clock input. Pullup Controls frequency division for Bank B outputs. LVCMOS interface levels. Pullup Controls frequency division for Bank A outputs. LVCMOS interface levels. Bank A outputs. LVCMOS interface levels. 7 typical output impedance. Output Bank A supply pins. Bank B outputs. LVCMOS interface levels. 7 typical output impedance. Output Bank B supply pins.
ICS8701-01
TABLE 1. PIN DESCRIPTIONS
Number 1, 3, 43, 45, 47 2, 44 4, 6, 8, 10, 12 5, 11 7, 9, 18, 21, 28, 30, 37, 39, 46, 48 13 14 15 16, 20 17, 19 22 23 24 25, 27, 29, 31, 33 26, 32 34, 36, 38, 40, 42 35, 41 Name QC3, QC4, QC0, QC1, QC2 VDDOC QD0, QD1, QD2, QD3, QD4 VDDOD GND DIV_SELD DIV_SELC nMR/OE VDD INV1, INV0 CLK DIV_SELB DIV_SELA QA0, QA1, QA2, QA3, QA4 VDDOA QB0, QB1, QB2, QB3, QB4 VDDOB
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter CIN RPULLUP C PD ROUT Input Capacitance Input Pullup Resistor Power Dissipation Capacitance (per output) Output Impedance VDD, *VDDOx = 3.465 5 7 Test Conditions Minimum Typical 4 51 15 12 Maximum Units pF K pF
*NOTE: VDDOx denotes VDDOA, VDDOB, VDDOC, and VDDOD.
TABLE 3. FUNCTION TABLE
nMR/OE 0 1 1 1 1 1 1 1 1
8701AY-01
Inputs DIV_SELx INV1 X X 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1
INV0 X 0 1 0 1 0 1 0 1
Bank A Hi Z Inver ting Inver ting Inver ting Inver ting Inver ting Inver ting Inver ting Inver ting
Bank B Hi Z Non-inver ting Inver ting Inver ting Inver ting Non-inver ting Inver ting Inver ting Inver ting
Outputs Bank C Hi Z Non-inver ting Non-inver ting Inver ting Inver ting Non-inver ting Non-inver ting Inver ting Inver ting
Bank D Hi Z Non-inver ting Non-inver ting Non-inver ting Inver ting Non-inver ting Non-inver ting Non-inver ting Inver ting
Qx Frequency zero fIN/2 fIN/2 fIN/2 fIN/2 fIN fIN fIN fIN
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REV. E DECEMBER 15, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/ LVTTL CLOCK GENERATOR W/POLARITY CONTROL
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ICS8701-01
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDOX = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDOx Parameter Core Supply Voltage Output Supply Voltage; NOTE 1 Test Conditions Minimum 3.135 3.135 2.375 Typical 3.3 3.3 2.5 Maximum 3.465 3.465 2.625 95 Units V V V mA
IDD Power Supply Current; NOTE 2 NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, and VDDOD. NOTE 2: IDD contributes 50mA; IDDOx contributes 45mA.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDOX = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol Parameter VIH Input High Voltage DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, INV0, INV1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, INV0, INV1, nMR/OE CLK VDD = VIN = 3.465V, VDD = VIN = 2.625V VDD = 3.465V, VIN = 0V, VDD = 2.625V, VIN = 0V *VDDOx = 3.465V *VDDOx = 2.625V -150 2.6 1.8 0.5 Test Conditions Minimum 2 2 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 5 Units V V V V A A V V V
VIL
Input Low Voltage
IIH IIL VOH
Input High Current Input Low Current Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50 to VDDOx/2. See Parameter Measurement Information section, "3.3V Output Load Test Circuit". *NOTE: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD.
8701AY-01
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3
REV. E DECEMBER 15, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/ LVTTL CLOCK GENERATOR W/POLARITY CONTROL
Test Conditions f 200MHz Measured on the Falling Edge Measured on the Falling Edge Minimum 2.0 Typical Maximum 250 3.5 250 300 350 700 20% to 80% 20% to 80% f 200MHz f = 200MHz 150 150 tPeriod/2 - 0.5 2 tPeriod/2 2.5 700 700 tPeriod/2 + 0.5 3 6 Units MHz ns ps ps ps ps ps ps ns ns ns ns
ICS8701-01
TABLE 5A. AC CHARACTERISTICS, VDD = VDDOX = 3.3V5%, TA = 0C TO 70C
Symbol Parameter Output Frequency fMAX tPD Propagation Delay; NOTE 1 Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t to Par t Skew; NOTE 5, 7 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Pulse Width Output Enable Time; NOTE 6
t sk(b) t sk(o) t sk(w) t sk(pp) tR tF
tPW tEN
tDIS Output Disable Time; NOTE 6 6 All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDOx/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOx/2. NOTE 4: Defined as skew across banks of outputs switching in the same direction operating at different frequencies with the same supply voltages and equal load conditions. Measured at VDDOx/2. NOTE 5: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOx/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDOX = 3.3V5%, TA = 0C TO 70C
Symbol Parameter Test Conditions Minimum Typical Maximum t sk(inv) Inver ting Skew; NOTE 1, 2 f = 66.7MHz 400 NOTE 1: Defined as skew across banks of outputs switching in opposite directions operating at the same frequency with the same supply voltages and equal load conditions. Measured at VDDOx/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. Units ps
8701AY-01
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4
REV. E DECEMBER 15, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/ LVTTL CLOCK GENERATOR W/POLARITY CONTROL
Test Conditions f 200MHz Measured on the Falling Edge Measured on the Falling Edge Minimum 2.0 Typical Maximum 250 3.5 300 300 350 700 20% to 80% 20% to 80% f 200MHz f = 200MHz 150 150 tPeriod/2 - 0.5 2 tPeriod/2 2.5 720 720 tPeriod/2 + 0.5 3 6 Units MHz ns ps ps ps ps ps ps ns ns ns ns
ICS8701-01
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDOX = 2.5V5%, TA = 0C TO 70C
Symbol Parameter Output Frequency fMAX tPD Propagation Delay; NOTE 1 Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t to Par t Skew; NOTE 5, 7 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Pulse Width Output Enable Time; NOTE 6
t sk(b) t sk(o) t sk(w) t sk(pp) tR tF
tPW t EN
Output Disable Time; NOTE 6 6 tDIS All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDOx/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOx/2. NOTE 4: Defined as skew across banks of outputs switching in the same direction operating at different frequencies with the same supply voltages and equal load conditions. Measured at VDDOx/2. NOTE 5: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOx/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
8701AY-01
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5
REV. E DECEMBER 15, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/ LVTTL CLOCK GENERATOR W/POLARITY CONTROL
ICS8701-01
PARAMETER MEASUREMENT INFORMATION
1.65V 5% 2.05V 5% 1.25V 5%
VDD, VDDOx
SCOPE
Qx
VDD VDDOx
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
VDDO 2
-1.65V 5% -1.25V 5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
PART 1 Qx
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
V
Qx
DDOx
V
DDOx
2
PART 2 Qy
2
V
Qy
DDOx
V
DDOx
2
2
tsk(pp)
tsk(o)
PART-TO-PART SKEW
V QAx, QBx, QCx, QDx
DDOX
OUTPUT SKEW
2 Pulse Width t
PERIOD
80% 20%
tR
80% 20% tF
Clock Outputs
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
CLK QAx,QBx, QCx, QDx
VDD 2 VDDOx 2 tPD
V CLK V Qx Qy
DD
2
DDOx
2 V
DDOx
2
tsk(in)
PROPAGATION DELAY
8701AY-01
INVERTING SKEW
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REV. E DECEMBER 15, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/ LVTTL CLOCK GENERATOR W/POLARITY CONTROL RELIABILITY INFORMATION
ICS8701-01
TABLE 7. JAVS. AIR FLOW TABLE
FOR
48 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8701-01 is: 1819
8701AY-01
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7
REV. E DECEMBER 15, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/ LVTTL CLOCK GENERATOR W/POLARITY CONTROL
48 LEAD LQFP
ICS8701-01
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
8701AY-01
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8
REV. E DECEMBER 15, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/ LVTTL CLOCK GENERATOR W/POLARITY CONTROL
ICS8701-01
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8701AY-01 ICS8701AY-01T Marking ICS8701AY-01 ICS8701AY-01 Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0C to 70C 0C to 70C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8701AY-01
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9
REV. E DECEMBER 15, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/ LVTTL CLOCK GENERATOR W/POLARITY CONTROL
REVISION HISTORY SHEET
ICS8701-01
Rev B
Table T4A & T4C
Page 4&6
B
T5A & T5B T2 T5A & T5B T5B T1 T2 T4A
5&7 2 4&5 4 2 2 3 3 4&5 4&5 6
B C C
Description of Change DC Characteristics tables revised. IDD row, value changed from 70mA Max. to 95mA Max. AC Characteristics tables revised: tPD symbol (Propagation Delay row), changed to tpHL. Added test conditions to Bank and Output Skews. Revised notes. Pin Characteristics table, added 15pF Max. to CPD row. Revised notes in AC tables. Added extra AC characteristics table to include Inver ting Skew parameters. Pin Description Table, revised nMR/OE description. Pin Characteristics Table - changed CIN max. 4pF to 4pF typical. Added 5 min. and 12 max. to ROUT. Combined 3.3V and Mixed 3.3V/2.5V Power Supply Tables. LVCMOS Table - changed VIH max. from 3.765V to VDD + 0.3V. Combined 3.3V and Mixed 3.3V/2.5V LVCMOS Tables. AC Characteristics Tables - deleted tpHL row. Changed tpLH to tPD. Updated format throughout data sheet. AC Characteristics Tables - changed tPD min. from 2.5ns to 2.0ns. Parameter Measurement Section - Propagation Delay Diagram, Qx should be inver ted and measurement should be from rising edge of clk to falling edge of Qx. Output Skew and Par t-to-Par t Skew Diagram should be measured on falling edge. Added Inver ting Skew Diagram.
Date 8/1/01
8/7/01
8/29/01 2/8/02 8/21/02
D
T4B T5A & T5B T5A & T5B
11/17/03
E
12/15/03
8701AY-01
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REV. E DECEMBER 15, 2003

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