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Integrated Circuit Systems, Inc.
ICS8532AY-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FEATURES
* 17 differential 3.3V LVPECL outputs * Selectable differential CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum output frequency: 500MHz * Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input * Output skew: 50ps (maximum) * Part-to-part skew: 250ps (maximum) * Propagation delay: 2.5ns (maximum) * 3.3V operating supply * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8532AY-01 is a low skew, 1-to-17, Differential-to-3.3V LVPECL Fanout Buffer and a HiPerClockSTM member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8532AY-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
ICS
Guaranteed output and part-to-part skew characteristics make the ICS8532AY-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_EN D Q CLK nCLK PCLK nPCLK CLK_SEL
PIN ASSIGNMENT
VCCO nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 Q0 Q1 Q2 Q3 Q4 Q5
LE
0 1
Q0:Q16 nQ0:nQ16
VCCO nc nc VCC CLK nCLK CLK_SEL PCLK nPCLK VEE CLK_EN VEE VCCO
1 2 3 4 5 6 7 8 9
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
VCCO Q6 nQ6 Q7 nQ7 Q8 nQ8 VCCO Q9 nQ9 Q10 nQ10 VCCO
ICS8532AY-01
33 32 31 30 29 28
10 11 12
13 27 14 15 16 17 18 19 20 21 22 23 24 25 26
nQ16 Q16 nQ15 Q15 nQ14 Q14 VCCO nQ13 Q13 nQ12 Q12 nQ11 Q11
52-Lead LQFP 10mm x 10mm x 1.4mm body package Y package Top View
8532AY-01
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REV. C FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS8532AY-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Type Description Output supply pins. No connect. Core supply pin. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects PCLK, nPCLK inputs. Pulldown When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential LVPECL clock input. Pullup Inver ting differential LVPECL clock input. Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follows clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Pullup
TABLE 1. PIN DESCRIPTIONS
Number 1, 13, 20, 27, 32, 39, 46 2, 3 4 5 6 7 8 9 10, 12 11 14, 15 16, 17 18, 19 Name VCCO nc VCC CLK nCLK CLK_SEL PCLK nPCLK V EE CLK_EN nQ16, Q16 nQ15, Q15 nQ14, Q14 Power Unused Power Input Input Input Input Input Power Input Output Output Output
Pullup
Differential clock outputs. LVPECL interface levels. 21, 22 nQ13, Q13 Output 23, 24 nQ12, Q12 Output Differential clock outputs. LVPECL interface levels. nQ11, Q11 Output Differential clock outputs. LVPECL interface levels. 25, 26 28, 29 nQ10, Q10 Output Differential clock outputs. LVPECL interface levels. 30, 31 nQ9, Q9 Output Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. 33, 34 nQ8, Q8 Output 35, 36 nQ7, Q7 Output Differential clock outputs. LVPECL interface levels. 37, 38 nQ6, Q6 Output Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. 40, 41 nQ5, Q5 Output 42, 43 nQ4, Q4 Output Differential clock outputs. LVPECL interface levels. 44, 45 nQ3, Q3 Output Differential clock outputs. LVPECL interface levels. 47, 48 nQ2, Q2 Output Differential clock outputs. LVPECL interface levels. 49, 50 nQ1, Q1 Output Differential clock outputs. LVPECL interface levels. 51, 52 nQ0, Q0 Output Differential clock outputs. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. NOTE: Unused output pairs must be terminated.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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REV. C FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS8532AY-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Inputs Outputs Selected Source CLK, nCLK PCLK, nPCLK CLK, nCLK Q0:Q16 Disabled; LOW Disabled; LOW Enabled nQ0:nQ16 Disabled; HIGH Disabled; HIGH Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
CLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B.
Disabled
nCLK, nPCLK CLK, PCLK
Enabled
CLK_EN
nQ0:nQ16 Q0:Q16
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK or PCLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK or nPCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q16 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ16 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section "Wiring the Differential Input to Accept Single Ended Levels".
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REV. C FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS8532AY-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
4.6V -0.5V to VCC + 0.5 V -0.5V to VCCO + 0.5V 42.3C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCO IEE Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 122 Maximum 3.465 3.465 150 Units V V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Current Input Low Current Input High Current Input Low Current CLK_EN, CLK_SEL CLK_EN, CLK_SEL CLK_SEL CLK_EN CLK_SEL CLK_EN Test Conditions Minimum 2 -0.3 VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -150 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL V PP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -150 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VEE + 0.5 VCMR NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK and nCLK is VCC + 0.3V.
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REV. C FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS8532AY-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Test Conditions PCLK nPCLK PCLK nPCLK VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.3 VEE + 1.5 VCCO - 1.4 VCCO - 2.0 1 VCC VCCO - 1.0 VCCO - 1.7 0.85 Minimum Typical Maximum 150 5 Units A A A A V V V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP VCMR VOH VOL Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage; NOTE 3 Output Low Voltage; NOTE 3
Peak-to-Peak Voltage Swing 0.6 VSWING NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time Output Duty Cycle 20% to 80% @ 50MHz 20% to 80% @ 50MHz 0 266MHz 300 300 48 50 500MHz 1.3 Test Conditions Minimum Typical Maximum 500 2.5 50 250 700 700 52 53 Units MHz ns ps ps ps ps % %
t sk(o) t sk(pp)
tR tF odc
266 500MHz 47 50 All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. C FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS8532AY-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V V CC
V CC, VCCO
Qx
SCOPE
LVPECL
VEE
nQx
nCLK, nPCLK
V
CLK, PCLK
PP
Cross Points
V
CMR
-1.3V 0.165V
VEE
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx nQ nQy Qy
PART 1 nQx Qx PART 2 nQy Qy
tsk(o)
tsk(pp)
OUTPUT SKEW
PART-TO-PART SKEW
nCLK, nPCLK CLK, PCLK nQ0:nQ16 Q0:Q16
tPD
80% Clock Outputs
80% VOD
20%
20% tR tF
PROPAGATION DELAY
nQ0:nQ16 Q0:Q16
OUTPUT RISE/FALL TIME
Pulse Width t
PERIOD
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. C FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS8532AY-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K CLK_IN + V_REF
-
C1 0.1uF R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125 125
FOUT
FIN
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 3A. LVPECL OUTPUT TERMINATION
8532AY-01
FIGURE 3B. LVPECL OUTPUT TERMINATION
REV. C FEBRUARY 22, 2005
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Integrated Circuit Systems, Inc.
ICS8532AY-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8532AY-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8532AY-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.8mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 17 * 30.2mW = 513.4mW
Total Power_MAX (3.465V, with all outputs switching) = 519.8mW + 513.4mW = 1033.2mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 36.4C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 1.033W * 36.4C/W = 107.6C. This is well below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
52-PIN LQFP FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0C/W 42.3C/W
200
47.1C/W 36.4C/W
500
42.0C/W 34.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. C FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
ICS8532AY-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4.
VCCO
Q1
VOUT RL 50 VCCO - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. C FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS8532AY-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
52 LEAD LQFP
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0C/W 42.3C/W
200
47.1C/W 36.4C/W
500
42.0C/W 34.0C/W
NOTE: Most all modern PCB designs use multi-layered boards, so the data in the second row will pertain to most designs.
TRANSISTOR COUNT
The transistor count for ICS8532AY-01 is: 1398
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REV. C FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS8532AY-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
52 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 E E1 e L ccc 0.45 0 --0.05 1.35 0.22 0.09 BCC MINIMUM NOMINAL 52 --1.40 0.32 -12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC ---0.75 7 0.08 1.60 0.15 1.45 0.38 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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REV. C FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS8532AY-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Marking ICS8532AY-01 ICS8532AY-01 Package 52 Lead LQFP 52 Lead LQFP Shipping Packaging tray tape & reel Temperature 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8532AY-01 ICS8532AY-01T
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8532AY-01
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REV. C FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS8532AY-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
REVISION HISTORY SHEET
Rev B B B B B
Table
Page 3 3 1 2 9 2 5 11
Description of Change Revised Figure 1, CLK_EN Timing Diagram. Revised Figure 1, CLK_EN Timing Diagram. Revised Pin Assignment. Revised Pin Description table. Added "Termination for LVPECL Outputs" section. Changed P/N (throughout the data sheet) from ICS8532-01 to ICS8532AY-01 Pin Description & Power Supply tablse - VCC description changed to "Core supply pin" from "Positive supply pin". Output Load Test Circuit diagram - corrected VEE equation to read, VEE = -1.3V 0.165V from VEE = -1.3V 0.135V. Revised Package Outline diagram and the Package Dimensions table. Block Diagram reversed CLK/nCLK & PCLK/nPCLK labels. Pin Characteristics Table -CIN changed 4pF max to 4pF typical. Block Diagram - switched PCLK/nPCLK with CLK/nCLK. Pin Descriptions table - pin 7 corrected description to read "When HIGH, selects PCLK, nPCLK... When LOW, selects CLK, nCLK...
Date 10/18/01 11/2/01 5/24/02 5/28/02 6/26/02
1
T1, T4A B
10/03/02
B C C T2 T1
11/20/02 12/20/04 2/22/05
1 2 1 2
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REV. C FEBRUARY 22, 2005

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