View ICS8530-01_986840.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FEATURES
* 16 differential 3.3V LVPECL outputs * CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency: 500MHz * Translates any single-ended input signal to 3.3V LVPECL levels with a resistor bias on nCLK input * Output skew: 75ps (maximum) * Part-to-part skew: 250ps (maximum) * Additive phase jitter, RMS: 0.03ps (typical) * 3.3V output operating supply * 0C to 70C ambient operating temperature * Lead-Free package RoHS compliant * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8530-01 is a low skew, 1-to-16 Differential-to-3.3V LVPECL Fanout Buffer and a memHiPerClockSTM ber of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels. The high gain differential amplifier accepts peak-topeak input voltages as small as 150mV as long as the common mode voltage is within the specified minimum and maximum range.
ICS
Guaranteed output and part-to-part skew characteristics make the ICS8530-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK nCLK
PIN ASSIGNMENT
nCLK VCCO Q15 nQ15 Q14 nQ14 VEE Q13 nQ13 Q12 nQ12 VCCO
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7
Q15 nQ15 Q14 nQ14 Q13 nQ13 Q12 nQ12 Q11 nQ11 Q10 nQ10 Q9 nQ9 Q8 nQ8
VCCO Q11 nQ11 Q10 nQ10 VEE Q9 nQ9 Q8 nQ8 VCCO VCC
ICS8530-01
CLK VCCO nQ0 Q0 nQ1 Q1 VEE nQ2 Q2 nQ3 Q3 Vcco
48-Pin LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
8530DY-01
www.icst.com/products/hiperclocks.html 1
VCCO nQ4 Q4 nQ5 Q5 VEE nQ6 Q6 nQ7 Q7 VCCO VCC
REV. D FEBRUARY 28, 2005
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Type Power Output Output Power Output Output Power Output Output Output Output Output Output Description Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Core supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 11, 14, 24, 25, 35, 38, 48 2, 3 4, 5 6, 19, 30, 43 7, 8 9, 10 12, 13 15, 16 17, 18 20, 21 22, 23 26, 27 28, 29 36 37 39, 40 41, 42 44, 45 46, 47 NOTE: Pullup and Name VCCO Q11, nQ11 Q10, nQ10 V EE Q9, nQ9 Q8, nQ8 VCC Q7, nQ7 Q6, nQ6 Q5, nQ5 Q4, nQ4 Q3, nQ3 Q2, nQ2
CLK Input Pulldown Non-inver ting differential clock input. nCLK Input Pullup Inver ting differential clock input. Q15, nQ15 Output Differential output pair. LVPECL interface levels. Q14, nQ14 Output Differential output pair. LVPECL interface levels. Q13, nQ13 Output Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Q12, nQ12 Output Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
TABLE 3. FUNCTION TABLE
Inputs CLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q15 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ15 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8530DY-01
www.icst.com/products/hiperclocks.html 2
REV. D FEBRUARY 28, 2005
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCO I EE Parameter Input/core Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 140 Units V V mA
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 1.0 VCCO - 1.7 0.85 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO-2V.
8530DY-01
www.icst.com/products/hiperclocks.html 3
REV. D FEBRUARY 28, 2005
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Test Conditions 500MHz Minimum 1 88 106.25MHz, Integration Range: 12KHz to 20MHz 20% to 80% @ 50MHz 20% to 80% @ 50MHz 0.03 300 300 700 700 53 Typical Maximum 500 2 75 250 Units MHz ns ps ps ps ps ps %
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise Time Output Fall Time
tsk(o) tsk(pp) tjit
tR tF
odc Output Duty Cycle 47 50 All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8530DY-01
www.icst.com/products/hiperclocks.html 4
REV. D FEBRUARY 28, 2005
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50 -60
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
@ 106.25MHz (12KHz to 20MHz) = 0.03ps typical
SSB PHASE NOISE dBc/HZ
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
8530DY-01
www.icst.com/products/hiperclocks.html 5
REV. D FEBRUARY 28, 2005
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V VCC
VCC, VCCO
Qx
SCOPE
nCLK V
PP
LVPECL
nQx
Cross Points
V
CMR
CLK
VEE VEE -1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
PART 1 nQx Qx PART 2 nQy Qy
tsk(o)
tsk(pp)
OUTPUT SKEW
nCLK
PART-TO-PART SKEW
80% CLK nQ0:nQ15 Q0:Q15
tPD
80% VSW I N G
Clock Outputs
20% tR tF
20%
PROPAGATION DELAY
nQ0:nQ15 Q0:Q15
Pulse Width t
PERIOD
OUTPUT RISE/FALL TIME
odc =
t PW t PERIOD
OUTPUT DUTY CYLE/PULSE WIDTH/PERIOD
8530DY-01
www.icst.com/products/hiperclocks.html 6
REV. D FEBRUARY 28, 2005
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125 125
FOUT
FIN
Zo = 50
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
FIGURE 2A. LVPECL OUTPUT TERMINATION
8530DY-01
FIGURE 2B. LVPECL OUTPUT TERMINATION
REV. D FEBRUARY 28, 2005
www.icst.com/products/hiperclocks.html 7
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
Zo = 50 Ohm
LVDS_Driv er
CLK
R1 100
nCLK
Receiv er
Zo = 50 Ohm
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
8530DY-01
BY
www.icst.com/products/hiperclocks.html 8
REV. D FEBRUARY 28, 2005
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8530-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8530-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.1mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 16 * 30.2mW = 483.2mW
Total Power_MAX (3.465V, with all outputs switching) = 485.1mW + 483.2mW = 968.3mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 47.9C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.968W * 47.9C/W = 116.4C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
48-PIN LQFP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8530DY-01
www.icst.com/products/hiperclocks.html 9
REV. D FEBRUARY 28, 2005
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8530DY-01
www.icst.com/products/hiperclocks.html 10
REV. D FEBRUARY 28, 2005
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
48 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8530-01 is: 930
8530DY-01
www.icst.com/products/hiperclocks.html 11
REV. D FEBRUARY 28, 2005
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
48 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
8530DY-01
www.icst.com/products/hiperclocks.html 12
REV. D FEBRUARY 28, 2005
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Marking ICS8530DY-01 ICS8530DY-01 ICS8530D01LF ICS8530D01LF Package 48 Lead LQFP 48 Lead LQFP 48 Lead "Lead-Free" LQFP 48 Lead "Lead-Free" LQFP Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8530DY-01 ICS8530DY-01T ICS8530DY-01LF ICS8530DY-01LFT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8530DY-01
www.icst.com/products/hiperclocks.html 13
REV. D FEBRUARY 28, 2005
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
REVISION HISTORY SHEET
Rev B
Table
Page 5-6 7 2 5
B T2 T4A C
Description of Change Updated figures. Added Termination for LVPECL Outputs section. Pin Description table - VCC description changed to "Core supply pin" from "Positive supply pin". Output Load Test Circuit diagram - corrected VEE equation to read, VEE = -1.3V 0.165V from VEE = -1.3V 0.135V. Pin Characteristics table - changed CIN 4pF max. to 4pF typical. Updated AMR Output rating. Power Supply table - changed IEE max. from 120mA to 140mA. Updated Single Ended Signal Driving Differential Input diagram. Added Differential Clock Input Interface section. Power Considerations, changed IEE to 140mA to reflect the Power Supply table and recalculated the equations. Update format throughout the data sheet. Added "Lead-Free" marking to Ordering Information Table. Features section - added Additive Phase Jitter bullet. AC Characteristics table - added tjit row. Added Additive Phase Jitter section.
Date 05/28/02
10/02/02
2 3 3 6 7 8
4/7/04
C D
T9 T5
12 1 4 5
6/29/04 2/28/05
8530DY-01
www.icst.com/products/hiperclocks.html 14
REV. D FEBRUARY 28, 2005

▲Up To Search▲

Price & Availability of ICS8530-01

	To Download ICS8530-01 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .