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ICS650-14
Networking System Clock
Description
The ICS650-14 is a low-cost, low-jitter, high-performance clock synthesizer customized for networking systems applications. Using analog/digital Phase-Locked Loop (PLL) techniques, the device accepts a 25 MHz clock or fundamental mode crystal input to produce multiple output clocks of one fixed 25 MHz, a four (plus one) frequency selectable bank, and two frequency selectable clocks. All output clocks are frequency locked together. All of the ICS650-14 outputs have zero ppm synthesis error.
Features
* * * * * * * * * * *
Packaged in 20-pin (150 mil) SSOP (QSOP) 25 MHz fundamental crystal clock or clock input One fixed output clock of 25 MHz One bank of four frequency selectable output clocks Three frequency selectable clocks outputs Zero ppm synthesis error in all clocks Ideal for networking systems Full CMOS output swing Advanced, low-power sub-micron CMOS process Operating voltage of 3.3 V or 5 V Industrial temperature range available
Block Diagram
VDD 2
S E L A 0 :1 S E L B 0 :1 S ELC
2 2 C lo ck S yn th e s is a n d C o n tro l C ircu itry
4
C L K A 1 :4 C LKA5 C LKB CLKC 25 M H z
X 1 /IC L K 25 M H z C rystal or C lock X2
C rystal B u ffe r/ C rystal O scillator 2
O p tional crystal capacitors are show n and m a y be re quired fo r tu ning of in itia l accura cy (d e term ined o n c e p e r b o a rd )
GND
O E (a ll o u tp u ts)
MDS 650-14 E
1
Revision 092104
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS650-14 Networking System Clock
Pin Assignment
SELB0 X2 X1/ICLK VDD SELB1 GND CLKB CLKC CLKA5 25M 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SELC SELA0 CLKA2 CLKA3 VDD SELA1 GND CLKA4 CLKA1 OE
Table 1
SELA1 0 0 0 M M M 1 1 1 SELA0 0 M 1 0 M 1 0 M 1 CLKA1:4 33.33 50 66.67 100 33.33 50 33.33 25 66.67 CLKA5 66.66 75 133.33 33.33 83.33 125 100 75 100
20-pin (150 mil) SSOP
Table 3 Table 2
SELC SELB1 0 0 0 1 1 1 SELB0 0 M 1 0 M 1 CLKB 30 27 48 83.33 19.44 80 0 M 1 CLKC CLKB/4 62.5 125
0 = connect directly to ground 1 = connect directly to VDD M = leave unconnected (floating)
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12
Pin Name
SELB0 X2 X1/ICLK VDD SELB1 GND CLKB CLKC CLKA5 25M OE CLKA1
Pin Type
TI XO XI P I(Pu) P O O O Ou I(Pu) O
Pin Description
Select pin for CLKB. See table 2. Crystal connection. Connect to a 25 MHz crystal or leave unconnected for clock input. Crystal connection. Connect to a 25 MHz fundamental crystal or clock input. Connect to 3.3 V or 5 V. Must be same as other VDDs. Select pin for CLK B. See table 2. Connect to ground. Selectable clock output. See table 2. Selectable clock output. See table 3. Selectable clock output. See table 1. 25 MHz clock output. Output enable. Tri-states all outputs when low. Internal pull-up. Selectable clock output. See table 1.
MDS 650-14 E
2
Revision 092104
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS650-14 Networking System Clock
Pin Number
13 14 15 16 17 18 19 20
Pin Name
CLKA4 GND SELA1 VDD CLKA3 CLKA2 SELA0 SELC
Pin Type
O P TI P O O TI TI Connect to ground.
Pin Description
Selectable clock output. See table 1. Select pin for CLKA1:4 and CLKA5 outputs. See table 1. Connect to 3.3 Vor 5 V. Must be same as other VDDs. Selectable clock output. See table 1. Selectable clock output. See table 1. Select pin for CLKA1:4 and CLKA5 outputs. See table 1. Select pin for CLKC output. See table 3.
Key: XI, XO = crystal connections; I = input; I(Pu) = input with pull-up; O = output; P = power supply connection; TI = tri-level input
External Components
The ICS650-14 requires a minimum number of external components for proper operation.
Crystal Information
The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation: Crystal caps (pF) = (CL - 6) x 2 In the equation, CL is the crystal load capacitance. For a crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2] capacitors should be used.
Decoupling Capacitor
Decoupling capacitors of 0.01F must be connected between each VDD and GND (pins 4 and 6, pins 16 and 14), as close to the device as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50 trace (a commonly used trace impedance) place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
MDS 650-14 E
3
Revision 092104
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS650-14 Networking System Clock
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-14. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD (referecned to GND) Inputs and Outputs (referecned to GND) Ambient Operating Temperature Ambient Operating Temperature (industrial "I" version) Soldering Temperature (max. of 20 seconds) Storage Temperature 7V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -40 to 85C -65 to +150C 260C
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature 0 to +70C
Parameter
Operating Voltage Input High Voltage (X1 pin only) Input Low Voltage (X1 pin only) Input High Voltage (SEL pins only) Input Low Voltage (SEL pins only) Input High Voltage (OE pin only) Input Low Voltage (OE pin only) Output High Voltage Output High Voltage (CMOS level) Output Low Voltage Operating Supply Current Short Circuit Current
Symbol
VDD VIH VIL VIH VIL VIH VIL VOH VOH VOL IDD
Conditions
Clock input Clock input
Min.
3.0 VDD/2+1
Typ.
Max.
5.5 VDD/2-1
Units
V V V V V V V V V
VDD-0.5 0.5 2.0 0.8 IOH = -12 mA IOH = -8 mA IOL = 12 mA No load, VDD = 3.3 V Each output 32 50 2.4 VDD-0.4 0.4
V mA mA
MDS 650-14 E
4
Revision 092104
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS650-14 Networking System Clock
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature 0 to +70 C
Parameter
Input Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Frequency Error Absolute Jitter, short term
Symbol
tOR tOF
Conditions
0.8 to 2.0 V 2.0 to 0.8 V At VDD/2 All clocks CLKB = 27M CLKC = 62.5M Other Clocks
Min.
Typ.
25
Max. Units
MHz 1.5 1.5 ns ns % ppm ps ps ps
45
50 250 300 350
55 0
Marking Diagram
20 11
650R-14 ###### YYWW$$
1
Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled.
10
MDS 650-14 E
5
Revision 092104
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS650-14 Networking System Clock
Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
20
Millimeters Symbol Min Max
Inches Min Max
E1 INDEX AREA
E
12 D
A A1 A2 b c D E E1 e L
1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 8.55 8.75 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0 8
0.053 0.069 0.004 0.010 -0.059 0.008 0.012 0.007 0.010 0.337 0.344 0.228 0.244 0.150 0.157 0.025 Basic 0.016 0.050 0 8
A 2 A 1
A
c
-Ce
b SEATING PLANE L
.10 (.004)
C
Ordering Information
Part / Order Number
ICS650R-14 ICS650R-14T ICS650R-14I ICS650R-14IT
Marking
650R-14 650R-14 650R-14I 650R-14I
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP
Temperature
0 to +70 C 0 to +70 C -40 to 85 C -40 to 85 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 650-14 E
6
Revision 092104
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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