 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| AT17C65/128/256 Features * * * * * * * * * E2 Programmable 65,536 x 1, 131,072 x 1, and 262,144 x 1 bit Serial Memories Designed To Store Configuration Programs For Programmable Gate Arrays Simple Interface to SRAM FPGAs Requires Only One User I/O Pin Compatible With AT6000 FPGAs, ATT3000 FPGA, EPF8000 FPGAs, ORCA FPGAs, XC2000, XC3000, XC4000, XC5000 FPGAs Cascadable To Support Additional Configurations or Future Higher-density Arrays (17C128 and 17C256 only) Low-power CMOS EEPROM Process Programmable Reset Polarity Available In the Space-efficient Plastic DIP or Surface-mount PLCC and SOIC Packages In-system Programmable Via 2-Wire Bus Emulation of 24CXX Serial E2PROMs Description The AT17C65/128/256 (AT17CXXX family) FPGA Configuration E2PROMS (Configurator) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. Both the AT17C65 and the AT17C128 are packaged in the 8-pin DIP and the popular 20-pin Plastic Leaded Chip Carrier, and SOIC. The AT17C256 is available in 14-pin SOIC or 20-pin PLCC or SOIC packages. The AT17CXXX family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17CXXX organization supplies enough memory to configure one or multiple smaller FPGAs. Using a special feature of the AT17CXXX, the user can select the polarity of the reset function by programming a special E2PROM bit. The AT17C65/128/256 can be programmed with the standard programmers from other manufacturers. FPGA Configuration E2PROM 65K, 128K, and 256K Pin Configurations 20-Pin PLCC 20-Pin SOIC * Please refer to Section 5, FPGA Configuration Memories, page 5-3 for complete AT17C65/128/256 data sheet. AT17C65/128/256 8-Pin DIP 0391D 2-117 Controlling The AT17C65/128/256 Serial E2PROMs Most connections between the FPGA device and the Serial E2PROM are simple and self-explanatory: * The DATA output of the AT17C65/128/256 drives DIN of the FPGA devices. * The master FPGA CCLK output drives the CLK input of the AT17C65/128/256. * The CEO output of any AT17C128/256 drives the CE input of the next AT17C128/256 in a cascade chain of PROMs. * SER_EN must be connected to VCC. There are, however, two different ways to use the inputs CE and OE, as shown in the AC Characteristics Waveform. If a system reset is applied to the FPGA, it will abort the original configuration and then reset itself for a new configuration, as intended. Of course, the AT17C65/128/256 does not see the external reset signal and will not reset its internal address counters and, consequently, will remain out of sync with the FPGA for the remainder of the configuration cycle. Condition 2 The FPGA D/P output drives only the CE input of the AT17C65/128/256, while its OE input is driven by the inversion of the FPGA RESET input. This connection works under all normal circumstances, even when the user aborts a configuration before D/P has gone High. A high level on the RESET/OE input to the AT17CXXX during FPGA reset clears the PROM internal address pointer, so that the reconfiguration starts at the beginning. The AT17C65/128/256 does not require an inverter since the RESET polarity is programmable. Condition 1 The simplest connection is to have the FPGA D/P output drive both CE and RESET/OE in parallel. Due to its simplicity, however, this method will fail if the FPGA receives an external reset condition during the configuration cycle. Block Diagram 2-118 AT17C65/128/256 |
Price & Availability of F65-E
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |