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| Eclipse II Family Data Sheet * * * * * * Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Flexible Programmable Logic * As low as 14 A standby current * 0.18 m, six layer metal CMOS process * 1.8 V VCC, 1.8/2.5/3.3 V drive capable I/O * Up to 4,002 dedicated flip-flops * Up to 55.3 K embedded SRAM bits * Up to 310 I/O * Up to 335 user available pins * Up to 320 K system gates * IEEE 1149.1 boundary scan testing compliant Advanced Clock Network * Multiple dedicated low skew clock networks * High drive input-only networks * Quadrant-based segmentable clock networks * User programmable Phase Locked Loops (PLL) Embedded Computational Units (ECUs) Hardwired DSP building blocks with integrated Multiply, Add, and Accumulate functions. Security Features The QuickLogic products come with secure ViaLink technology that protects intellectual property from design theft and reverse engineering. No external configuration memory needed; instant-on at power-up. Figure 1: Eclipse II Block Diagram PLL Embedded RAM Blocks Embeded Computational Units PLL Embedded Dual Port SRAM * Up to twenty-four 2,304 bit dual port high performance SRAM blocks * RAM/ROM/FIFO wizard for automatic configuration * Configurable and cascadable aspect ratio Programmable I/O * High performance I/O cell * Programmable slew rate control * Programmable I/O standards: ! Fabric LVTTL, LVCMOS, LVCMOS18, PCI, GTL+, SSTL2, and SSTL3 Independent I/O banks capable of supporting multiple standards in one device I/O register configurations: Input, Output, Output Enable (OE) PLL Embedded RAM Blocks PLL ! ! (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 1 Eclipse II Family Data Sheet Rev. H Table 1: Eclipse II Product Family Members QL8025 Max Gates Logic Array Logic Cells Max Flip-Flops Max I/O RAM Modules RAM Bits PLLs ECUs VQFP TQFP Packages TFBGA (0.8 mm) PQFP LFBGA (0.8 mm) BGA (1.0 mm) 47,052 16 x 8 128 532 92 4 9,216 100 144 196 QL8050 63,840 16 x 16 256 884 124 4 9,216 100 144 196 QL8150 188,946 32 x 20 640 1,709 163 16 36,864 144 196 208 280 QL8250 248,160 40 x 24 960 2,670 250 20 46,100 4 10 208 280 484 QL8325 320,640 48 x 32 1,536 4,002 310 24 55,300 4 12 208 280 484 Table 2: Max I/O per Device/Package Combination Device QL8025 QL8050 QL8150 QL8250 QL8325 100 VQFP 62 62 144 TQFP 92 100 100 196 TFBGA 92 124 124 208 PQFP 143 115 115 280 LFBGA 163 163 163 484 PBGA 250 310 QuickWorks Design Software The QuickWorks package provides the most complete ESP and FPGA software solution from design entry to logic synthesis, to place and route, to power calculation, and simulation. The package provides a solution for designers who use third-party tools from Cadence, Mentor, OrCAD, Synopsys, Viewlogic, and other thirdparty tools for design entry, synthesis, or simulation. Process Data Eclipse II is fabricated on a 0.18 , six layer metal CMOS process. The core voltage is 1.8 V and the I/Os are up to 3.3 V drive/tolerant. The Eclipse II product line is available in commercial, industrial, and military temperature grades. 2 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Programmable Logic Architectural Overview The Eclipse II logic cell structure is presented in Figure 2. This architectural feature addresses today's registerintensive designs. Table 3: Performance Standards Function Multiplexer Parity Tree Counter Description 16:1 24 36 16 bit 32 bit 128 x 32 FIFO Clock-to-Out System clock 128 x 64 256 x 16 Slowest Speed Grade 2.8 ns 3.4 ns 4.6 ns 275 MHz 250 MHz 197 MHz 188 MHz 208 MHz 4 ns 200 MHz Fastest Speed Grade 2.4 ns 2.9 ns 3.9 ns 328 MHz 300 MHz 235 MHz 266 MHz 248 MHz 3.3 ns 300 MHz The Eclipse II logic cell structure presented in Figure 2 is a dual register, multiplexer-based logic cell. It is designed for wide fan-in and multiple, simultaneous output functions. Both registers share CLK, SET, and RESET inputs. The second register has a two-to-one multiplexer controlling its input. The register can be loaded from the NZ output or directly from a dedicated input. NOTE: The input PP is not an "input" in the classical sense. It is a static input to the logic cell and selects which path (NZ or PS) is used as an input to the Q2Z register. All other inputs are dynamic and can be connected to multiple routing channels. The complete logic cell consists of two six-input AND gates, four two-input AND gates, seven two-to-one multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell has a fan-in of 30 (including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six outputs (four combinatorial and two registered). The high logic capacity and fan-in of the logic cell accommodates many user functions with a single level of logic delay while other architectures require two or more levels of delay. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 3 Eclipse II Family Data Sheet Rev. H Figure 2: Eclipse II Logic Cell QS A1 A2 A3 A4 A5 A6 OS OP B1 B2 C1 C2 MP MS D1 D2 E1 E2 NP NS F1 F2 F3 F4 F5 F6 PS PP QC QR AZ OZ QZ NZ Q2Z FZ RAM Modules The Eclipse II Product Family includes up to 24 dual-port 2,304-bit RAM modules for implementing RAM, ROM, and FIFO functions. Each module is user-configurable into two different block organizations and can be cascaded horizontally to increase their effective width, or vertically to increase their effective depth as shown in Figure 4. Figure 3: 2,304-bit RAM Module MODE[1:0] WA[7:0] WD[17:0] WE WCLK ASYNCRD RA[7:0] RD[17:0] RE RCLK The number of RAM modules varies from 4 to 24 blocks for a total of 9.2 K to 55.3 K bits of RAM. Using the two "mode" pins, designers can configure each module into 128 x 18 and 256 x 9. The blocks are also easily cascadable to increase their effective width and/or depth (see Figure 4). 4 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Figure 4: Cascaded RAM Modules WDATA WADDR RAM Module (2,304 bits) RDATA RADDR WDATA RAM Module (2,304 bits) RDATA The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE ports support synchronous operation. Each port has 18 data lines and 8 address lines, allowing word lengths of up to 18 bits and address spaces of up to 256 words. Depending on the mode selected, however, some higher order data or address lines may not be used. The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for asynchronous READ operation (ASYNCRD input high). Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. A similar technique can be used to create depths greater than 256 words. In this case address signals higher than the MSB are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals. The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with data from an external PROM (typically for ROM functions). Embedded Computational Unit (ECU) Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively-- these functions require high logic cell usage while garnering only moderate performance results. The Eclipse II architecture allows for functionality above and beyond that achievable using programmable logic devices. By embedding a dynamically reconfigurable computational unit, the Eclipse II device can address various arithmetic functions efficiently. This approach offers greater performance and utilization than traditional programmable logic implementations. The embedded block is implemented at the transistor level as shown in Figure 5. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 5 Eclipse II Family Data Sheet Rev. H Figure 5: ECU Block Diagram RESET D S1 S2 S3 CIN SIGN1 SIGN2 00 01 3-1 mux 10 Q[16:0] 3-4 decoder C B A A[7:0] A[15:8] 8-bit Multiplier 2-1 mux 16-bit Adder D Q 17-bit Register A[0:15] CLK B[0:15] 2-1 mux The Eclipse II ECU blocks (Table 4) are placed next to the SRAM circuitry for efficient memory/instruction fetch and addressing for DSP algorithmic implementations. Table 4: Eclipse II ECU Blocks Device QL8325 QL8250 QL8150 QL8050 QL8025 ECUs 12 10 0 0 0 Up to twelve 8-bit MAC functions can be implemented per cycle for a total of 1 billion MACs/s when clocked at 100 MHz. Additional multiply-accumulate functions can be implemented in the programmable logic. The modes for the ECU block are dynamically re-programmable through the programmable logic. 6 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Table 5: ECU Mode Select Criteria Instruction Operation S1 0 0 0 0 1 1 1 1 S2 0 0 1 1 0 0 1 1 S3 0 1 0 1 0 1 0 1 Multiply Multiply-Add Accumulate Add Multiply (registered)c Multiply- Add (registered) Multiply - Accumulate Add (registered) b ECU Performancea, tPD 6.6 ns max 8.8 ns max tSU -8 WCC tCO 3.9 ns min 3.1 ns max 9.6 ns min 9.6 ns min 9.6 ns min 3.9 ns min 1.2 ns max 1.2 ns max 1.2 ns max 1.2 ns max 1.2 ns max a. tPD, tSU and tCO do not include routing paths in/out of the ECU block. b. Internal feedback path in ECU restricts max clk frequency to 238 MHz. c. B [15:0] set to zero. NOTE: Timing numbers in Table 5 represent -8 Worst Case Commercial conditions. Phase Locked Loop (PLL) Information Instead of requiring extra components, designers simply need to instantiate one of the pre-configured models (described in this section). The QuickLogic built-in PLLs support a wider range of frequencies than many other PLLs. These PLLs also have the ability to support different ranges of frequency multiplications or divisions, driving the device at a faster or slower rate than the incoming clock frequency. When PLLs are cascaded, the clock signal must be routed off-chip through the PLLPAD_OUT pin prior to routing into another PLL; internal routing cannot be used for cascading PLLs. Figure 6 illustrates a QuickLogic PLL. Figure 6: PLL Block Diagram 1st Quadrant 2nd Quadrant 3rd Quadrant FIN Frequency Divide _ .1 . . _2 . . _4 . + Filter vco PLL Bypass 4th Quadrant Clock Tree Frequency Multiply . _ .1 . _2 . . _4 . FOUT (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 7 Eclipse II Family Data Sheet Rev. H Fin represents a very stable high-frequency input clock and produces an accurate signal reference. This signal can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass through the PLL itself. Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external Fin signal and the local VCO form a control loop. The VCO is multiplied or divided down to the reference frequency, so that a phase detector (the crossed circle in Figure 6) can compare the two signals. If the phases of the external and local signals are not within the tolerance required, the phase detector sends a signal through the charge pump and loop filter (Figure 6). The charge pump generates an error voltage to bring the VCO back into alignment, and the loop filter removes any high frequency noise before the error voltage enters the VCO. This new VCO signal enters the clock tree to drive the chip's circuitry. Fout represents the clock signal emerging from the output pad (the output signal PLLPAD_OUT is explained in Table 7). The PLL always drives the PLLPAD_OUT signal, regardless of whether the PLL is configured for on-chip use. The PLLPAD_OUT will not oscillate if PLL_RESET is asserted, or if the PLL is powered down. The QL8325 and QL8250 devices contain four PLLs, the remaining Eclipse II devices do not contain PLLs. There is one PLL located in each quadrant of the FPGA. QuickLogic PLLs compensate for the additional delay created by the clock tree itself, as previously noted, by subtracting the clock tree delay through the feedback path. PLL Modes of Operation QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output frequency-- Table 6 indicates the features of each mode. NOTE: "HF" stands for "high frequency" and "LF" stands for "low frequency." Table 6: PLL Mode Frequencies PLL Model PLL_HF PLL_LF PLL_MULT2HF PLL_MULT2LF PLL_DIV2HF PLL_DIV2LF PLL_MULT4 PLL_DIV4 Output Frequency Same as input Same as input 2x 2x 1/2x 1/2x 4x 1/4x Input Frequency Range 66 MHz-220 MHz 25 MHz-66 MHz 33 MHz-110 MHz 12.5 MHz-33 MHz 220 MHz-440 MHz 50 MHz-220 MHz 12.5 MHz-50 MHz 100 MHz-440 MHz Output Frequency Range 66 MHz-220 MHz 25 MHz-66 MHz 66 MHz-220 MHz 25 MHz-66 MHz 110 MHz-220 MHz 25 MHz-110 MHz 50 MHz-200 MHz 25 MHz-110 MHz The input frequency can range from 12.5 MHz to 440 MHz, while output frequency ranges from 25 MHz to 220 MHz. When adding PLLs to the top-level design, be sure that the PLL mode matches the desired input and output frequencies. 8 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H PLL Signals Table 7 summarizes the key signals in QuickLogic PLLs. Table 7: QuickLogic PLL Signals Signal Name PLLCLK_IN PLL_RESET ONn_OFFCHIP CLKNET_OUT PLLCLK_OUT PLLPAD_OUT Input clock signal. Active High Reset If PLL_RESET is asserted, then CLKNET_OUT and PLLPAD_OUT are reset to 0. This signal must be asserted and then released in order for the LOCK_DETECT to work. This is a reserved signal. It can be connected to VCC or GND. Out to internal gates This signal bypasses the PLL logic before driving the clock tree. Note that this signal cannot be used in the same quadrant where the PLL signal is used (PLLCLK_OUT). Out from PLL to internal gates This signal can drive the clock tree after going through the PLL. Out to off-chip This outgoing signal is used off-chip. The PLLPAD_OUT is always active, driving the PLL-derived clock signal out through the pad. The PLLPAD_OUT will not oscillate if PLL_RESET is asserted, or if the PLL is powered down. Description Active High Lock detection signal LOCK_DETECT NOTE: For simulation purposes, this signal gets asserted after 10 clock cycles. However, it can take a maximum of 200 clock cycles to sync with the input clock upon release of the PLL_RESET signal. NOTE: Because PLLCLK_IN and PLL_RESET signals have PLL_INPAD, and PLLPAD_OUT has OUTPAD, you do not need to add additional pads to your design. I/O Cell Structure Eclipse II features a variety of distinct I/O pins to maximize performance, functionality, and flexibility with bidirectional I/O pins and input-only pins. All input and I/O pins are 1.8 V, 2.5 V, and 3.3 V tolerant and comply with the specific I/O standard selected. For single ended I/O standards, VCCIO specifies the input tolerance and the output drive. For voltage referenced I/O standards (e.g SSTL), the voltage supplied to the INREF pins in each bank specifies the input switch point. For example, the VCCIO pins must be tied to a 3.3 V supply to provide 3.3 V compliance. Eclipse II can also support the LVDS and LVPECL I/O standards with the use of external resistors (see Table 8). Table 8: I/O Standards and Applications I/O Standard LVTTL LVCMOS25 LVCMOS18 PCI GTL+ SSTL3 SSTL2 Reference Voltage n/a n/a n/a n/a 1 1.5 1.25 Output Voltage 3.3 V 2.5 V 1.8 V 3.3 V n/a 3.3 V 2.5 V Application General Purpose General Purpose General Purpose PCI Bus Applications Backplane SDRAM SDRAM As designs become more complex and requirements more stringent, several application-specific I/O standards have emerged for specific applications. I/O standards for processors, memories, and a variety of bus applications have become commonplace and a requirement for many systems. In addition, I/O timing has (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 9 Eclipse II Family Data Sheet Rev. H become a greater issue with specific requirements for setup, hold, clock to out, and switching times. Eclipse II has addressed these new system requirements and now includes a completely new I/O cell which consists of programmable I/Os as well as a new cell structure consisting of three registers--Input, Output, and OE. Eclipse II offers banks of programmable I/Os that address many of the bus standards that are popular today. As shown in Figure 7 each bi-directional I/O pin is associated with an I/O cell which features an input register, an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one output multiplexers. Figure 7: Eclipse II I/O Cell + - INPUT REGISTER QE D R OUTPUT REGISTER D R Q PAD OUTPUT ENABLE REGISTER D E Q R The bi-directional I/O pin options can be programmed for input, output, or bi-directional operation. As shown in Figure 7, each bi-directional I/O pin is associated with an I/O cell which features an input register, an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one multiplexers. The select lines of the two-to-one multiplexers are static and must be connected to either VCC or GND. For input functions, I/O pins can provide combinatorial, registered data, or both options simultaneously to the logic array. For combinatorial input operation, data is routed from I/O pins through the input buffer to the array logic. For registered input operation, I/O pins drive the D input of input cell registers, allowing data to be captured with fast, predictable set-up times without consuming internal logic cell resources. The comparator and multiplexer in the input path allows for native support of I/O standards with reference points offset from traditional ground. For output functions, I/O pins can receive combinatorial or registered data from the logic array. For combinatorial output operation, data is routed from the logic array through a multiplexer to the I/O pin. For registered output operation, the array logic drives the D input of the output cell register which in turn drives the I/O pin through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be 10 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H driven to the I/O pin. The addition of an output register will also decrease the Tco. Since the output register does not need to drive the routing the length of the output path is also reduced, and static timing analysis becomes very predictable. The three-state output buffer controls the flow of data from the array logic to the I/O pin and allows the I/O pin to act as an input and/or output. The buffer's output enable can be individually controlled by the logic cell array or any pin (through the regular routing resources), or it can be bank-controlled through one of the global networks. The signal can also be either combinatorial or registered. This is identical to that of the flow for the output cell. For combinatorial control operation, data is routed from the logic array through a multiplexer to the three-state control. The IOCTRL pins can directly drive the OE and CLK signals for all I/O cells within the same bank. For registered control operation, the array logic drives the D input of the OE cell register which in turn drives the three-state control through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be driven to the three-state control. When I/O pins are unused, the OE controls can be permanently disabled, allowing the output cell register to be used for registered feedback into the logic array. I/O cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular routing resources, from one of the global networks, or from two IOCTRL input pins per bank of I/O's. The CLK and RESET signals share common lines, while the clock enables for each register can be independently controlled. I/O interface support is programmable on a per bank basis. The two larger Eclipse II devices contain eight I/O banks. Figure 8 illustrates the I/O bank configurations for QL8325 and QL8250. The three smaller Eclipse II devices contain two I/O banks per device. Figure 9 illustrates the I/O bank configurations for QL8150, QL8050, and QL8025. Each I/O bank is independent of other I/O banks and each I/O bank has its own VCCIO and INREF supply inputs. A mixture of different I/O standards can be used on the device; however, there is a limitation as to which I/O standards can be supported within a given bank. Only standards that share a common VCCIO and INREF can be shared within the same bank (e.g., PCI and LVTTL). In the case of the QL8150, QL8050 and QL8025, only one voltage-referenced standard can be used. The two I/O banks, A and B, share the INREF pin. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 11 Eclipse II Family Data Sheet Rev. H Figure 8: Multiple I/O Banks on QL8325 and QL8250 VCCIO(F) INREF(F) VCCIO(E) INREF(E) VCCIO(G) PLL Embedded RAM Blocks Embeded Computational Units PLL VCCIO(D) INREF(G) INREF(D) Fabric VCCIO(H) VCCIO(C) INREF(H) PLL Embedded RAM Blocks PLL INREF (C) VCCIO(A) INREF(A) VCCIO(B) INREF(B) Figure 9: Multiple I/O Banks on QL8150, QL8050, and QL8025 VDED Embedded RAM Blocks VCCIO(A) Fabric VCCIO(B) Embedded RAM Blocks INREF 12 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Programmable Slew Rate Each I/O has programmable slew rate capability--the slew rate can be either fast or slow. The slower rate can be used to reduce the switching times of each I/O. Programmable Weak Pull-Down A programmable Weak Pull-Down resistor is available on each I/O. The I/O Weak Pull-Down eliminates the need for external pull down resistors for used I/Os as shown in Figure 10. The spec for pull-down current is maximum of 150 A under worst case condition. Figure 10: Programmable I/O Weak Pull-Down I/O Output Logic PAD (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 13 Eclipse II Family Data Sheet Rev. H Clock Networks Global Clocks There are eight global clock networks in each QL8325 and QL8250 device, and five global clock networks in each QL8150, QL8050 and QL8025 device. Global clocks can drive logic cells and I/O registers, ECUs, and RAM blocks in the device. All global clocks have access to a Quad Net (local clock network) connection with a programmable connection to the logic cell's register clock input. Figure 11: Global Clock Architecture Quad Net Global Clock Net CLK Pin Quad-Net Network There are five Quad-Net local clock networks in each quadrant for a total of 20 in a device. Each Quad-Net is local to a quadrant. Before driving the column clock buffers, the quad-net is driven by the output of a mux which selects between the CLK pin input and an internally generated clock source (see Figure 12). Figure 12: Global Clock Structure Quad-Net Clock Network Internally generated clock, or clock from general routing network Global Clock (CLK) Input FF Global Clock Buffer 14 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Dedicated Clock There is one dedicated clock in the two larger devices of the Eclipse II Family (QL8325 and QL8250). This clock connects to the clock input of the Logic Cell and I/O registers, and RAM blocks through a hardwired connection and is multiplexed with the programmable clock input. The dedicated clock provides a fast global network with low skew. Users have the ability to select either the dedicated clock or the programmable clock (Figure 13). Figure 13: Dedicated Clock Circuitry within Logic Cell Logic Cell Programmable Clock or General Routing Dedicated Clock CLK NOTE: For more information on the clocking capabilities of Eclipse II FPGAs, see QuickLogic Application Note 68 at http://www.quicklogic.com/images/appnote68.pdf. I/O Control and Local Hi-Drives Each bank of I/Os has two input-only pins that can be programmed to drive the RST, CLK, and EN inputs of I/Os in that bank. These input-only pins also serve as high drive inputs to a quadrant. These buffers can be driven by the internal logic both as an I/O control or high drive. For I/O constrained designs, these pins can be used for general purpose inputs. To provide more general purpose I/Os in the 208 PQFP package, the I/O controls pins are not bonded out. The performance of these resources is presented in Table 9. Table 9: I/O Control Network/Local High-Drive Destination TT, 25 C, 2.5 V I/O (far) I/O (near) Skew From Pad 1.00 ns 0.63 ns 0.37 ns From Array 1.14 ns 0.78 ns 0.36 ns (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 15 Eclipse II Family Data Sheet Rev. H Table 10 shows the total number of I/O control pins per device/package combination. These pins are not bonded out in the smaller devices and packages. This increases the number of bi-directional user I/Os available. Table 10: I/O Control Pins per Device/Package Combination Device QL8025 QL8050 QL8150 QL8250 QL8325 100 VQFP Not available Not available Not available 144 TQFP Not available Not available 196 TFBGA Not available Not available 208 PQFP Not available Not available 280 LFBGA Not available Not available Not available 16 16 484 BGA Not available Not available Not available 16 16 Programmable Logic Routing Eclipse II devices are engineered with six types of routing resources as follows: short (sometimes called segmented) wires, dual wires, quad wires, express wires, distributed networks, and default wires. Short wires span the length of one logic cell, always in the vertical direction. Dual wires run horizontally and span the length of two logic cells. Short and dual wires are predominantly used for local connections. Default wires supply VCC and GND (Logic `1' and Logic `0') to each column of logic cells. Quad wires have passive link interconnect elements every fourth logic cell. As a result, these wires are typically used to implement intermediate length or medium fan-out nets. Express lines run the length of the device, uninterrupted. Each of these lines has a higher capacitance than a quad, dual, or short wire, but less capacitance than shorter wires connected to run the length of the device. The resistance will also be lower because the express wires don't require the use of pass links. Express wires provide higher performance for long routes or high fan-out nets. Distributed networks are described in Clock Networks on page 14. These wires span the programmable logic and are driven by quad-net buffers. Global Power-On Reset (POR) The Eclipse II family of devices features a global power-on reset. This reset is hardwired to all registers and resets them to Logic `0' upon power-up of the device. In QuickLogic devices, the asynchronous Reset input to flip-flops has priority over the Set input; therefore, the Global POR will reset all flip-flops during power-up. If you want to set the flip-flops to Logic `1', you must assert the "Set" signal after the Global POR signal has been deasserted. Figure 14: Power-On Reset VCC Power-on Reset Q XXXXXXX 0 16 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Low Power Mode Quiescent power consumption of all Eclipse II devices can be reduced significantly by de-activating the charge pumps inside the architecture. By applying 3.3 V to the VPUMP pin, the internal charge pump is deactivated--this effectively reduces the static and dynamic power consumption of the device. The Eclipse II device is fully functional and operational in the Low Power mode. Users who have a 3.3 V supply available in their system should take advantage of this low power feature by tying the VPUMP pin to 3.3 V. Otherwise, if a 3.3 V supply is not available, this pin should be tied to ground. Joint Test Access Group (JTAG) Information Figure 15: JTAG Block Diagram TCK TMS TRSTB Tap Controller State Machine (16 States) Instruction Decode & Control Logic Instruction Register RDI Mux Boundary-Scan Register (Data Register) Mux TDO Bypass Register Internal Register I/O Registers User Defined Data Register Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, one problem being the accessibility of test points. JTAG formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR), which allow users to run three required tests along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 17 Eclipse II Family Data Sheet Rev. H The 1149.1 standard requires the following three tests: * Extest Instruction. The Extest Instruction performs a printed circuit board (PCB) interconnect test. This test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (through the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction. The Sample/Preload Instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed through a data scan operation, allowing users to sample the functional data entering and leaving the device. * Bypass Instruction. The Bypass Instruction allows data to skip a device boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device. JTAG BSDL Support * BSDL-Boundary Scan Description Language * Machine-readable data for test equipment to generate testing vectors and software * BSDL files available for all device/package combinations from QuickLogic * Extensive industry support available and ATVG (Automatic Test Vector Generation) Security Links There are several security links to disable reading logic from the array, and to disable JTAG access to the device. Programming these optional links completely disables access to the device from the outside world and provides an extra level of design security not possible in SRAM-based FPGAs. The option to program these links is selectable through QuickWorks in the Tools/Options/Device Programming window in SpDE. Power-Up Loading Link The flexibility link enables Power-Up Loading of the Embedded RAM blocks. If the link is programmed, the Power-Up Loading state machine is activated during power-up of the device. The state machine communicates with an external EPROM via the JTAG pins to download memory contents into the on-chip RAM. If the link is not programmed, Power-Up Loading is not enabled and the JTAG pins function as they normally would. The option to program this link is selectable through QuickWorks in the Tools/Options/Device Programming window in SpDE. For more information on Power-Up Loading, see QuickLogic Application Note 55 at http://www.quicklogic.com/images/appnote55.pdf. See the Power-Up Loading power-up sequencing requirement for proper functionality in Figure 16. 18 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Figure 16: Required Power-Up Sequence When Using Power-Up Loading VCCIO VDED VDED2 VPUMP VCC Voltage VCC < 2 ms Time To use the power-up loading function in Eclipse II, designers must ensure that VCC begins to ramp within a maximum of 2 ms of VCCIO, VDED, VDED2, and VPUMP. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 19 Eclipse II Family Data Sheet Rev. H Electrical Specifications DC Characteristics The DC Specifications are provided in Table 11 through Table 14. Table 11: Absolute Maximum Ratings Parameter VCC Voltage VCCIO Voltage INREF Voltage Input Voltage Value -0.5 V to 2.0 V -0.5 V to 4.0 V 0.5 V to VCCIO -0.5 V to VCCIO + 0.5 V Parameter Latch-up Immunity DC Input Current Leaded Package Storage Temperature Laminate Package (BGA) Storage Temperature Value 100 mA 20 mA -65 C to + 150 C -55 C to + 125 C Table 12: Recommended Operating Range Symbol VCC VCCIO TJ K Parameter Supply Voltage I/O Input Tolerance Voltage Junction Temperature -6 Speed Grade Delay Factor -7 Speed Grade -8 Speed Grade Military Min 1.71 1.71 -55 0.49 0.48 0.45 Max 1.89 3.60 125 1.57 1.40 1.32 Industrial Min 1.71 1.71 -40 0.50 0.50 0.47 Max 1.89 3.60 100 1.51 1.34 1.26 Commercial Min 1.71 1.71 0 0.54 0.53 0.50 Max 1.89 3.60 85 1.47 1.31 1.23 V V C n/a n/a n/a Unit 20 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Table 13: DC Characteristics Symbol Il IOZ CI CCLOCK IOS IREF IPD IPUMP IPLL IVCCIO Parameter I or I/O Input Leakage Current 3-State Output Leakage Current I/O Input Capacitance Clock Input Capacitance Output Short Circuit Currenta Quiescent Current on INREF Current on programmable pull-down Quiescent Current on VPUMP Quiescent Current on each VCCPLL Conditions VI = VCCIO or GND VI = VCCIO or GND VO = GND VO = VCC VCC = 1.8 V VPUMP= 3.3 V 2.5 V 3.3 V VCCIO = 3.6 V VCCIO = 2.5 V VCCIO = 1.8 V Min -1 -15 40 -10 Max 1 1 8 8 -180 210 10 50 10 3 20 10 10 Units A A pF pF mA mA A A A mA Quiescent Current on VCCIO - A a. The data provided in Figure 14 represents the JEDEC and PCI specifications. Duration should not exceed 30 seconds. Table 14: DC Input and Output Levelsa Symbol LVTTL LVCMOS2 LVCMOS18 GTL+ PCI SSTL2 SSTL3 INREF VMIN VMAX VMIN n/a n/a n/a 0.88 n/a 1.15 1.3 n/a n/a n/a 1.12 n/a 1.35 1.7 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 VIL VMAX 0.8 0.7 0.63 INREF - 0.2 0.3 x VCCIO INREF - 0.2 VMIN 2.2 1.7 1.2 INREF + 0.2 0.6 x VCCIO INREF + 0.2 VIH VMAX VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VOL VMAX 0.4 0.7 0.7 0.6 0.74 1.10 VOH VMIN 2.4 1.7 1.7 n/a 1.76 1.90 IOL mA 2.0 2.0 2.0 40 7.6 8 IOH mA -2.0 -2.0 -2.0 n/a -0.5 -7.6 -8 VCCIO + 0.5 0.1 x VCCIO 0.9 x VCCIO 1.5 VCCIO + 0.3 -0.3 INREF - 0.18 INREF + 0.18 VCCIO + 0.3 a. The data provided in Table 14 represents the JEDEC and PCI specification. QuickLogic devices either meet or exceed these requirements. For data specific to QuickLogic I/Os, see preceding Table 19 through Table 27, Figure 7 through Figure 10, and Figure 39 through Figure 42. NOTE: All CLK, IOCTRL, and PLLIN pins are clamped to the VDED rail. Therefore, these pins can be driven up to VDED. All JTAG inputs are clamped to the VDED2 rail. These JTAG input pins can only be driven up to VDED2. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 21 Eclipse II Family Data Sheet Rev. H Figure 17 through Figure 20 show the VIL and VIH characteristics for I/O and clock pins. Figure 17: VIL Maximum for I/O VILmax for IO 2.5 1.71 V 2 Voltage (V) 1.5 1 0.5 0 -55C -40C 0C 25C 70C 90C 110C 125C Junction Temperature 1.8 V 1.89 V 2.5 V 3.3 V 3.6 V Figure 18: VIH Minimum for I/O VIHmin for IO 2.5 2 Voltage 1.5 1 0.5 0 -55C -40C 0C 25C 70C 90C 110C 125C 1.71 V 1.8 V 1.89 V 2.5 V 3.3 V 3.6 V Junction Temperature 22 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Figure 19: VIL Maximum for CLOCK Pins VILmax for CLOCK pins 2 1.71V Voltage (V) 1.5 1 0.5 0 -55C -40C 0C 25C 70C 90C 110C 125C 1.8 V 1.89 V 2.5 V 3.3 V 3.6 V Junction Temperature Figure 20: VIH Minimum for CLOCK Pins VIHmin for CLOCK pins 2.5 2 Voltage (V) 1.5 1 0.5 0 -55C -40C 0C 25C 70C 90C 110C 125C Junction Temperature 1.71 V 1.8 V 1.89 V 2.5 V 3.3 V 3.6 V (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 23 Eclipse II Family Data Sheet Rev. H Figure 21 through Figure 25 show the output drive characteristics for the I/Os across various voltages and temperatures. Figure 21: Drive Current at VCCIO = 1.71 V Drive Current @ Vccio = 1.71 V 35 Drive Current (mA) 30 25 20 15 10 5 0 IOH: -55C IOL: -55C IOH: 25C IOL: 25C IOH: 125C IOL: 125C 0. 2 0. 4 0. 6 0. 8 1. 2 1. 4 1. 6 0 1 Output Voltage (V) Figure 22: Drive Current at VCCIO = 1.8 V Drive Current @ Vccio = 1.8 V 40 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 1. 71 Drive Current (mA) IOH: -55C IOL: -55C IOH: 25C IOL: 25C IOH: 125C IOL: 125C Output Voltage (V) 24 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Figure 23: Drive Current at VCCIO = 2.5 V Drive Current @ Vccio = 2.5V 80 70 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 Output Voltage (V) Drive Current (mA) IOH: -55C IOL: -55C IOH: 25C IOL: 25C IOH: 125C IOL: 125C Figure 24: Drive Current at VCCIO = 3.3 V Drive Current @ Vccio = 3.3V 120 Drive Current (mA) 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.3 Output Voltage (V) IOH: -55C IOL: -55C IOH: 25C IOL: 25C IOH: 125C IOL: 125C (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 25 Eclipse II Family Data Sheet Rev. H Figure 25: Drive Current at VCCIO = 3.6 V Drive Current @ Vccio = 3.6V 140 Drive Current (mA) 120 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.3 3.6 Output Voltage (V) IOH: -55C IOL: -55C IOH: 25C IOL: 25C IOH: 125C IOL: 125C 26 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Figure 26 through Figure 30 show the quiescent current for the Eclipse II family of devices for each of the voltage supplies, across voltage and temperature. Quiescent current on VCC is a function of device utilization. The numbers in the following graphs were taken from 100% utilized devices, filled with 32-bit counters. For conditions other than those described, measured quiescent current levels may be higher than the values in Figure 26 through Figure 30. Use the Power Calculator Tool for more accurate estimates. Figure 26: Quiescent Current on VCC for QL8025 Quiescent Current on VCC for QL8025 140.0 120.0 100.0 80.0 uA 60.0 40.0 20.0 0.0 -55C -40C 0C 25C 70C 90C 125C Am bient Tem perature VCC=1.71V VCC=1.8V VCC=1.89V Table 15: Quiescent Current on VCC for QL8025 (Over All Temperatures - Over 1.71 V to 3.6 V) Parameter IVDED ICCIO Current 2.5 A 1.0 A (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 27 Eclipse II Family Data Sheet Rev. H Figure 27: Quiescent Current on VCC for QL8050 Queiscent Current on VCC for QL8050 200.0 180.0 160.0 140.0 120.0 uA 100.0 80.0 60.0 40.0 20.0 0.0 -55C -40C 0C 25C 70C 90C 125C Am bient Tem perature VCC=1.71V VCC=1.8V VCC=1.89V Table 16: Quiescent Current on VCC for QL8050 (Over All Temperatures - Over 1.71 V to 3.6 V) Parameter IVDED ICCIO Current 2.6 A 2.0 A 28 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Figure 28: Quiescent Current on VCC for QL8150 Quiescent Current on VCC for QL8150 1200.0 1000.0 800.0 VCC=1.71V uA 600.0 400.0 200.0 0.0 -55C -40C 0C 25C 70C 90C 125C Am bient Tem perature VCC=1.8V VCC=1.89V Table 17: Quiescent Current on VCC for QL8150 (Over All Temperatures - Over 1.71 V to 3.6 V) Parameter IVDED ICCIO Current 18.4 A 7.7 A (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 29 Eclipse II Family Data Sheet Rev. H Figure 29: Quiescent Current on VCC for QL8250 Quiescent Current on VCC for QL8250 1000.0 900.0 800.0 700.0 600.0 uA 500.0 400.0 300.0 200.0 100.0 0.0 -55C -40C 0C 25C 70C 90C 125C Ambient Temperature VCC=1.71V VCC=1.8V VCC=1.89V Table 18: Quiescent Current on VCC for QL8250 (Over All Temperatures - Over 1.71 V to 3.6 V) Parameter IVDED ICCIO Current 16.9 A 5.5 A 30 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Figure 30: Quiescent Current on VCC for QL8325 Quiescent Current on VCC for QL8325 1600.0 1400.0 1200.0 1000.0 VCC=1.71V uA 800.0 600.0 400.0 200.0 0.0 -55C -40C 0C 25C 70C 90C 125C Ambient Temperature VCC=1.8V VCC=1.89V Table 19: Quiescent Current on VCC for QL8325 (Over All Temperatures - Over 1.71 V to 3.6 V) Parameter IVDED ICCIO Current 16.9 A 5.1 A (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 31 Eclipse II Family Data Sheet Rev. H AC Characteristics The AC Specifications (at VCC = 1.8 V, TJ = 25 C, Worst Case Corner, Speed Grade = -8 (K = 1.03)) are provided from Table 20 through Table 29. Logic Cell diagrams and waveforms are provided from Figure 31 through Figure 42. Figure 31: Eclipse II Logic Cell Table 20: Logic Cell Delays Symbol tPD tSU tHL tCO tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay of the longest path: time taken by the combinatorial circuit to output Setup time: time the synchronous input of the flip-flop must be stable before the active clock edge Hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Clock-to-out delay: the amount of time taken by the flip-flop to output after the active clock edge. Clock High Time: required minimum time the clock stays high Clock Low Time: required minimum time that the clock stays low Set Delay: time between when the flip-flop is "set" (high) and when the output is consequently "set" (high) Reset Delay: time between when the flip-flop is "reset" (low) and when the output is consequently "reset" (low) Set Width: time that the SET signal must remain high/low Reset Width: time that the RESET signal must remain high/low Value Min 0.28 ns 0.10 ns 0 ns 0.22 ns 0.46 ns 0.46 ns 0.69 ns 1.09 ns 0.3 ns 0.3 ns Max 0.98 ns 0.25 ns 0 ns 0.52 ns 0.46 ns 0.46 ns 0.69 ns 1.09 ns 0.3 ns 0.3 ns 32 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Figure 32: Logic Cell Flip-Flop SET D CLK RESET Figure 33: Logic Cell Flip-Flop Timings--First Waveform Q CLK tCWHI (min) SET tCWLO (min) RESET Q tRESET tRW tSET tSW Figure 34: Logic Cell Flip-Flop Timings--Second Waveform CLK D tSU tHL Q tCO (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 33 Eclipse II Family Data Sheet Rev. H Table 21: Eclipse II Tree Clock Delay Clock Segment tPGCK tBGCK tDPD tGSKEW tDSKEW Parameter Global clock pin delay to quad net Global clock tree delay (quad net to flip-flop) Dedicated clock pad Global delay clock skew Dedicated clock skew Value Min Max 1.92 ns 0.28 ns 1.7 ns 0.1 ns 0.05 ns NOTE: When using a PLL, tPGCK and tBGCK are effectively zero due to delay adjustment by Phase Locked Loop feedback path. Figure 35: Global Clock Structure Timing Elements Quad-Net Clock Network Internally generated clock, or clock from general routing network Global Clock (CLK) Input FF Global Clock Buffer Figure 36: Dual-Port SRAM Cell [7:0] [17:0] WA WD WE WCLK RE RCLK RA RD ASYNCRD RAM Module [7:0] [17:0] 34 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Table 22: RAM Cell Synchronous Write Timing Symbol RAM Cell Synchronous Write Timing tSWA tHWA tSWD tHWD tSWE tHWE tWCRD WA setup time to WCLK: time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK WD setup time to WCLK: time the WRITE DATA must be stable before the active edge of the WRITE CLOCK WD hold time to WCLK: time the WRITE DATA must be stable after the active edge of the WRITE CLOCK WE setup time to WCLK: time the WRITE ENABLE must be stable before the active edge of the WRITE CLOCK WE hold time to WCLK: time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the time when the data is available at RD 0.47 ns 0 ns 0.48 ns 0 ns 0 ns 0 ns 3.79 ns Parameter Value Min Max Figure 37: RAM Cell Synchronous Write Timing WCLK WA tSWA WD tSWD WE tSWE RD old data tWCRD tHWE new data tHWD tHWA (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 35 Eclipse II Family Data Sheet Rev. H Table 23: RAM Cell Synchronous and Asynchronous Read Timing Symbol RAM Cell Synchronous Read Timing tSRA tHRA tSRE tHRE tRCRD RA setup time to RCLK: time the READ ADDRESS must be stable before the active edge of the READ CLOCK RA hold time to RCLK: time the READ ADDRESS must be stable after the active edge of the READ CLOCK RE setup time to WCLK: time the READ ENABLE must be stable before the active edge of the READ CLOCK RE hold time to WCLK: time the READ ENABLE must be stable after the active edge of the READ CLOCK RCLK to RD: time between the active READ CLOCK edge and the time when the data is available at RD RA to RD: time between when the READ ADDRESS is input and when the DATA is output 0.43 ns 0 ns 0.21 ns 0 ns 2.25 ns Parameter Value Min Max RAM Cell Asynchronous Read Timing rPDRD 1.99 ns 36 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Figure 38: RAM Cell Synchronous and Asynchronous Read Timing RCLK RA tSRA tHRA RE tSRE tHRE new data RD old data tRCRD rPDRD Figure 39: Eclipse II I/O Cell Output Path PAD OUTPUT REGISTER (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 37 Eclipse II Family Data Sheet Rev. H Figure 40: Eclipse II I/O Cell Output Enable Timing tOUTHL H L H Z L H Z L tOUTLH H L H tPZH Z L H Z L tPZL tPHZ tPLZ Table 24: Eclipse II I/O Cell Output Timing Symbol Output Register Cell Only tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ tCOP Output Delay low to high (90% of H) Output Delay high to low (10% of L) Output Delay tri-state to high (90% of H) Output Delay tri-state to low (10% of L) Output Delay high to tri-state Output Delay low to tri-state Clock-to-out delay (does not include clock tree delays) Parameter 4.0 3.5 4.96 4.87 5.8 5.58 5.49 Value (ns) Slow Slew Max Fast Slew Max 2.95 2.49 2.93 2.84 3.62 3.4 3.3 Table 25: Output Slew Rates @ VCCIO = 3.3 V, T = 25 C Fast Slew Rising Edge Falling Edge 2.8 V/ns 2.86 V/ns Slow Slew 1.0 V/ns 1.0 V/ns Table 26: Output Slew Rates @ VCCIO = 2.5 V, T = 25 C Fast Slew Rising Edge Falling Edge 1.7 V/ns 1.9 V/ns Slow Slew 0.6 V/ns 0.6 V/ns Table 27: Output Slew Rates @ VCCIO = 1.8 V, T = 25 C Fast Slew Rising Edge Falling Edge TBD TBD Slow Slew TBD TBD 38 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Figure 41: Eclipse II I/O Cell Input Path tISU + tSID QE R D PAD Figure 42: Eclipse II Input Register Cell Timing R CLK D tIS U tIH L Q tIC O tIR S T E tIE S U tIE H i C ll i i (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 39 Eclipse II Family Data Sheet Rev. H Table 28: I/O Input Register Cell Timing Symbol tISU tIHL tICO tIRST tIESU tIEH Parameter Input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge Input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Input register clock-to-out: time taken by the flip-flop to output after the active clock edge Input register reset delay: time between when the flip-flop is "reset"(low) and when the output is consequently "reset" (low) Input register clock enable setup time: time "enable" must be stable before the active clock edge Input register clock enable hold time: time "enable" must be stable after the active clock edge Value Min 2.15 ns 0 ns 0.4 ns 0 ns Max 0.3 ns 0.82 ns - Table 29: I/O Input Buffer Delays Parameter Symbol To get the total input delay add this delay to tISU tSID (LVTTL) tSID (LVCMOS2) LVTTL input delay: Low Voltage TTL for 3.3 V applications LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower applications Min Max 0.82 ns 0.82 ns 0.94 ns 0.94 ns 0.94 ns 0.82 ns Value tSID (LVCMOS18) LVCMOS18 input delay: Low Voltage CMOS for 1.8 V applications tSID (GTL+) tSID (SSTL3) tSID (SSTL2) tSID (PCI) GTL+ input delay: Gunning Transceiver Logic SSTL3 input delay: Stub Series Terminated Logic for 3.3 V SSTL2 input delay: Stub Series Terminated Logic for 2.5 V PCI input delay: Peripheral Component Interconnect for 3.3 V 40 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Package Thermal Characteristics Thermal Resistance Equations: JC = (TJ - TC)/P JA = (TJ - TA)/P PMAX = (TJMAX - TAMAX)/JA Parameter Description: JC: Junction-to-case thermal resistance JA: Junction-to-ambient thermal resistance TJ: Junction temperature TA: Ambient temperature P: Power dissipated by the device while operating PMAX: The maximum power dissipation for the device TJMAX: Maximum junction temperature TAMAX: Maximum ambient temperature NOTE: Maximum junction temperature (TJMAX) is 125C. To calculate the maximum power dissipation for a device package look up JA from Table 30, pick an appropriate TAMAX and use: PMAX = (125C - TAMAX)/ JA Table 30: Package Thermal Characteristics Device Package Description Package Code Package Type PS PBGA LFBGA PQFP PBGA LFBGA PQFP LFBGA PQFP TFBGA TQFP TFBGA TQFP VQFP TFBGA TQFP VQFP PT PQ PS Pin Count 484 280 208 484 280 208 280 208 196 144 196 144 100 196 144 100 0 LFM 26.6 34 32 26.6 34 32 34 43.6 40 37 54 41 43 54 41 43 JA ( C/W) 200 LFM 24.1 31.6 28 24.1 31.6 28 31.6 41 38 36 51.8 39 41.3 51.8 39 41.3 400 LFM 21.8 29.9 26.5 21.8 29.9 26.5 29.9 39 35.2 34 48 37 38.8 48 37 38.8 QL8325 QL6325E QL8250 QL6250E PT PQ PT PQ PT PF PT QL8150 QL8050 PF PV PT QL8025 PF PV (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 41 Eclipse II Family Data Sheet Rev. H Power vs. Operating Frequency The basic power equation which best models power consumption is given below: PTOTAL = 0.350 + f[0.0031 LC + 0.0948 CKBF + 0.01 CLBF + 0.0263 0.543 RAM + 0.20 PLL + 0.0035 INP + 0.0257 OUTP] (mW) Where: CKLD + LC is the total number of logic cells in the design CKBF = # of clock buffers CLBF = # of column clock buffers CKLD = # of loads connected to the column clock buffers RAM = # of RAM blocks PLL = # of PLLs INP is the number of input pins OUTP is the number of output pins NOTE: To learn more about power consumption, see QuickLogic Application Note 60 at http://www.quicklogic.com/images/appnote60.pdf. Power-up Sequencing Figure 43: Power-Up Sequencing VCCIO VDED VDED2 VPUMP VCC |VCCIO , VDED , VDED2 , VPUMP - VCC|MAX Voltage VCC 400 us Time When powering up a device, the VCC/VCCIO/VDED/VDED2 rails must take 400 s or longer to reach the maximum value (refer to Figure 43). NOTE: Ramping VCC, VCCIO, VPUMP, VDED, or VDED2 faster than 400 s can cause the device to behave improperly. For users with a limited power budget, ensure VCCIO, VDED, VDED2, and VPUMP are within 500 mV of VCC when ramping up the power supplies. 42 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Pin Descriptions Table 31: Pin Descriptions Pin Direction Function JTAG Pin Descriptions TDI/RSI I Test Data In for JTAG/RAM init. Serial Data In Active low Reset for JTAG/RAM init. reset out Test Mode Select for JTAG Test Clock for JTAG Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VDED2 if unused Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused Hold HIGH during normal operation. Connect to VDED2 if not used for JTAG Hold HIGH or LOW during normal operation. Connect to VDED2 or GND if not used for JTAG Description TRSTB/RRO TMS TCK I/0 I I TDO/RCO O Connect to serial PROM clock for RAM initialization. Must be Test data out for JTAG/RAM init. left unconnected if not used for JTAG or RAM initialization. clock out The output voltage drive is specified by VDED. Dedicated Pin Descriptions Low skew global clock. This pin provides access to a dedicated, distributed network capable of driving the CLOCK, SET, RESET, F1, and A2 inputs to the Logic Cell, READ, and WRITE CLOCKS, Read and Write Enables of the Embedded RAM Blocks, CLOCK of the ECUs, and Output Enables of the I/Os. The voltage tolerance of this pin is specified by VDED. The I/O pin is a bi-directional pin, configurable to either an input-only, output-only, or bi-directional pin. The A inside the parenthesis means that the I/O is located in Bank A. If an I/O is not used, SpDE (QuickWorks Tool) provides the option of tying that pin to GND, VCC, or TriState. Connect to 1.8 V supply. This pin provides the flexibility to interface the device with either a 3.3 V, 2.5 V, or 1.8 V device. The A inside the parenthesis means that VCCIO is located in BANK A. Every I/O pin in Bank A will be tolerant of VCCIO input signals and will drive VCCIO level output signals. This pin must be connected to either 3.3 V, 2.5 V, or 1.8 V. VCCIO powers the the PLLOUT pins. Connect to ground. Clock input for PLL. The voltage tolerance of this pin is specified by VDED. Very low skew global clock. This pin provides access to a dedicated, distributed clock network capable of driving the CLOCK inputs of all sequential elements of the device (e.g., RAM, Flip Flops). The voltage tolerance of this pin is specified by VDED. Connect to GND. CLK I Global clock network pin I/O(A) I/O Input/Output pin VCC I Power supply pin VCCIO(A) I Input voltage tolerance pin GND PLLIN I I Ground pin PLL clock input DEDCLK I Dedicated clock pin GNDPLL I Ground pin for PLL (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 43 Eclipse II Family Data Sheet Rev. H Table 31: Pin Descriptions (Continued) Pin Direction Function Description The INREF is the reference voltage pin for GTL+, SSTL2, and STTL3 standards. Follow the recommendations provided in Table 14 for the appropriate standard. The A inside the parenthesis means that INREF is located in BANK A. This pin should be tied to GND if voltage referenced standards are not used. Dedicated PLL output pin. Must be left unconnected if PLL is powered up and not held in reset, since PLLOUT will be driving the PLL-derived clock. May be left unconnected if PLL is held in reset or not powered up. PLLOUT pin is driven by VCCIO. For a list of each PLLOUT pin and the VCCIO pin that powers it see Table 32. This pin provides fast RESET, SET, CLOCK, and ENABLE access to the I/O cell flip-flops, providing fast clock-to-out and fast I/O response times. This pin can also double as a highdrive pin to the internal logic cells. The A inside the parenthesis means that IOCTRL is located in Bank A. There is an internal pulldown resistor to GND on this pin. This pin should be tied to GND if it is not used. For backwards compatibility with Eclipse and EclipsePlus, it can be tied to VDED or GND. If tied to VDED, it will draw no more than 20 A per IOCTRL pin due to current through the pulldown resistor. The voltage tolerance of this pin is specified by VDED. Note that the 208 PQFP package has no I/O control pins. This pin disables the internal charge pump for lower static power consumption. To disable the charge pump, connect VPUMP to 3.3 V. If the Disable Charge Pump feature is not used, connect VPUMP to GND. For backwards compatibility with Eclipse and EclipsePlus devices, connect VPUMP to GND. This pin specifies the input voltage tolerance for CLK, DEDCLK, PLLIN, and IOCTRL dedicated input pins, as well as the output voltage drive TDO JTAG pins. If the PLLs are used, VDED must be the same as VCCPLL. The legal range for VDED is between 1.71 V and 3.6 V. For backwards compatibility with Eclipse and EclipsePlus devices, connect VDED to 2.5 V. INREF(A) I Differential reference voltage PLLOUT O PLL output pin IOCTRL(A) I Highdrive input VPUMP I Charge Pump Disable VDED I Voltage tolerance for clocks, TDO JTAG output, and IOCTRL 44 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Table 31: Pin Descriptions (Continued) Pin Direction Function Description These pins specify the input voltage tolerance for the JTAG input pins. The legal range for VDED2 is between 1.71 V and 3.6 V. These do not specify output voltage of the JTAG output, TDO. Refer to the VDED pin section for specifying the JTAG output voltage. Connect to 2.5 V or 3.3 V supply. For backwards compatibility with Eclipse and EclipsePlus devices, connect to 2.5 V. To minimize static power consumption when designs do not utilize the PLLs, you may connect VCCPLL to GND. If VCCPLL is grounded, the PLL is disabled. If PLL_RESET is asserted, then CLKNET_OUT and PLLPAD_OUT are reset to 0. This signal must be asserted and then released in order for the LOCK_DETECT to work. If a PLL module is not used, then the associated PLLRST VDED2 I Voltage tolerance for JTAG pins (TDI, TMS, TCK, and TRSTB) VCCPLL I Power Supply pin for PLL PLL_RESET I PLL reset pin Table 32: PLLOUT Pin Supply Voltage PLLOUT PLLOUT(0) PLLOUT(1) PLLOUT(2) PLLOUT(3) VCCIO VCCIO(E) VCCIO(B) VCCIO(A) VCCIO(F) (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 45 Eclipse II Family Data Sheet Rev. H Figure 44: QL8325 and QL8250 I/O Banks with Relevant Pins VCCIO (B) INREF(B) VCCIO (A) INREF(A) IOCTRL(B) IOCTRL(A) IO(A) IO BANK A VCCIO (H) INREF(H) IOCTRL(H) IO(H) IO BANK B VCCIO (C) INREF(C) IOCTRL(C) IO(C) IO BANK H IO(B) IO BANK C IO BANK G VCCIO (G) INREF(G) IOCTRL(G) IO(G) VCCIO (D) INREF(D) IOCTRL(D) IO(D) IO BANK D IO BANK F IO BANK E INREF(E) IO(E) INREF(F) IO(F) VCCIO (E) IOCTRL(E) Figure 45: QL8150, QL8050, and QL8025 I/O Banks with Relevant Pins VCCIO (F) IOCTRL(F) IO BANK B VCCIO (A) IO(A) VCCIO (B IO(B) IO BANK A INREF 46 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Recommended Unused Pin Terminations for Eclipse II Devices All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally using the Configuration Editor. This option is given in the bottom-right corner of the placement window. To use the Placement Editor, choose Constraint > Fix Placement in the Option pull-down menu of SpDE. The rest of the pins should be terminated at the board level in the manner presented in Table 33. Table 33: Recommended Unused Pin Terminations Signal Name Recommended Termination In earlier versions, the recommendation for unused PLLOUT pins was that they be connected to VCC or GND. This was acceptable for Rev. D (and earlier) silicon, including all 0.25 m devices. For Rev. G (and later) silicon this is not correct. Unused PLLOUT pins should be left unconnected. Used PLLOUT pins will normally be connected to inputs, but can also be left unconnected. For the truth table of PLLOUT connections, refer to Table 34. There is an internal pulldown resistor to GND on this pin. This pin should be tied to GND if it is not used. For backwards compatibility with Eclipse, it can be tied to VDED or GND. If tied to VDED, it will draw no more than 20 A per IOCTRL pin due to current through the pulldown resistor. Any unused clock pins should be connected to VDED or GND. If a PLL module is not used, then the associated PLLRST PLLOUT IOCTRL a. x represents a number. b. y represents an alphabetical character. Table 34: Recommended PLLOUT Terminations Truth Table PLL_RESET 0 1 Recommended PLLOUT Termination Must be left unconnected. May be left unconnected, or connected to GND. Must not be connected to VCC. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 47 Eclipse II Family Data Sheet Rev. H QL8025 - 100 VQFP Pinout Diagram Pin 1 Pin 76 Eclipse II QL8025-7PV100C Pin 26 Pin 51 QL8025 - 100 VQFP Pinout Table Table 35: QL8025 - 100 VQFP Pinout Table Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Function GND GND I/O(A) I/O(A) I/O(A) VCC I/O(A) I/O(A) VCCIO(A) I/O(A) TDI CLK(0) CLK(1) VCC I/O(A) VDED I/O(A) GND I/O(A) I/O(A) Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Function I/O(A) I/O(A) I/O(A) I/O(A) TDO I/O(A) GND I/O(A) VCCIO(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCC TRSTB VDED2 I/O(A) I/O(A) GND Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Function VCC I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) VPUMP I/O(A) GND I/O(B) I/O(B) I/O(B) VCC I/O(B) INREF I/O(B) I/O(B) VCCIO(B) Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function I/O(B) I/O(B) CLK(2) CLK(3) VCC CLK(4) TMS I/O(B) GND I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) GND I/O(B) VCCIO(B) I/O(B) I/O(B) Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Function I/O(B) I/O(B) I/O(B) VCC I/O(B) I/O(B) VCC TCK VDED2 I/O(B) GND I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCCIO(B) I/O(B) I/O(B) 48 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H QL8025 - 144 TQFP Pinout Diagram Pin 1 Pin 109 Eclipse II QL8025-7PF144C Pin 37 Pin 73 Figure 46: Top View of 144 Pin TQFP (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 49 Eclipse II Family Data Sheet Rev. H QL8025 - 144 TQFP Pinout Table Table 36: QL8025 - 144 TQFP Pinout Table Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Function GND GND IO(A) IO(A) IO(A) IO(A) VCC IO(A) IO(A) IO(A) NC IO(A) VCCIO(A) IO(A) TDI CLK(0) CLK(1) VCC IO(A) VDED IO(A) IO(A) GND VCCIO(A) IO(A) IO(A) NC IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) TDO GND IO(A) Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Function IO(A) GND IO(A) VCCIO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) IO(A) NC VCC TRSTB VDED2 IO(A) IO(A) IO(A) GND IO(A) VCC IO(A) IO(A) IO(A) IO(A) NC IO(A) IO(A) IO(A) VCCIO(A) IO(A) VPUMP IO(A) Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Function IO(A) IO(B) GND IO(B) IO(B) IO(B) VCC IO(B) IO(B) INREF IO(B) IO(B) IO(B) VCCIO(B) IO(B) NC IO(B) CLK(2) CLK(3) VCC CLK(4) TMS IO(B) GND VCCIO(B) IO(B) IO(B) IO(B) IO(B) NC IO(B) IO(B) IO(B) IO(B) GND IO(B) Pin 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Function GND IO(B) VCCIO(B) IO(B) IO(B) IO(B) IO(B) IO(B) NC IO(B) IO(B) VCC IO(B) VCCIO(B) IO(B) IO(B) VCC TCK VDED2 IO(B) IO(B) GND IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) NC IO(B) IO(B) IO(B) VCCIO(B) IO(B) IO(B) IO(B) 50 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H QL8025 - 196 TFBGA Pinout Diagram Top Eclipse II QL8025-7PT196C Bottom 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Pin A1 Corner (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 51 Eclipse II Family Data Sheet Rev. H QL8025 - 196 TFBGA Pinout Table Table 37: QL8025 - 196 TFBGA Pinout Table Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 Function IO(B) IO(B) NC IO(B) IO(B) NC CLK(4) CLK(2) NC IO(B) INREF IO(B) IO(B) IO(B) NC IO(B) IO(B) NC IO(B) TMS VCC IO(B) NC IO(B) IO(B) IO(B) IO(A) IO(A) IO(B) IO(B) IO(B) VCC IO(B) VCC IO(B) CLK(3) IO(B) VCC IO(B) IO(A) Ball C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 Function NC NC IO(B) NC NC IO(B) IO(B) VCCIO(B) VCCIO(B) VDED VCCIO(B) IO(B) NC VPUMP IO(A) IO(A) IO(B) IO(B) IO(B) IO(B) VCCIO(B) GND GND GND GND IO(A) VCCIO(A) IO(A) NC VCC IO(B) VCC NC IO(B) VCCIO(B) GND GND GND GND IO(A) Ball F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J6 J7 J8 Function IO(A) NC IO(A) IO(A) IO(B) TCK NC VCC GND GND GND GND GND GND IO(A) VCC IO(A) IO(A) NC IO(B) VDED2 VCCIO(B) GND GND GND GND GND GND VCCIO(A) TRSTB VDED2 VCC IO(B) IO(B) IO(B) VCC IO(B) GND GND GND Ball J9 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 Function GND GND IO(A) IO(A) NC NC NC NC IO(B) IO(B) VCCIO(B) VCCIO(A) GND GND VCCIO(A) VCCIO(A) NC IO(A) IO(A) IO(A) IO(B) IO(B) IO(B) IO(B) NC NC VCCIO(A) VDED VDED VCCIO(A) VCC IO(A) IO(A) IO(A) NC IO(B) IO(A) GND VCC TDI Ball M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Function VCC IO(A) IO(A) IO(A) IO(A) IO(A) NC IO(A) NC IO(B) IO(A) IO(A) IO(A) NC IO(A) IO(A) IO(A) NC NC TDO IO(A) NC IO(A) IO(A) IO(A) NC IO(A) CLK(0) CLK(1) IO(A) IO(A) IO(A) NC IO(A) IO(A) IO(A) 52 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H QL8050 - 100 VQFP Pinout Diagram Pin 1 Pin 76 Eclipse II QL8050-7PV100C Pin 26 Pin 51 QL8050 - 100 VQFP Pinout Table Table 38: QL8050 - 100 VQFP Pinout Table Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Function GND GND I/O(A) I/O(A) I/O(A) VCC I/O(A) I/O(A) VCCIO(A) I/O(A) TDI CLK(0) CLK(1) VCC I/O(A) VDED I/O(A) GND I/O(A) I/O(A) Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Function I/O(A) I/O(A) I/O(A) I/O(A) TDO I/O(A) GND I/O(A) VCCIO(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCC TRSTB VDED2 I/O(A) I/O(A) GND Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Function VCC I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) VPUMP I/O(A) GND I/O(B) I/O(B) I/O(B) VCC I/O(B) INREF I/O(B) I/O(B) VCCIO(B) Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function I/O(B) I/O(B) CLK(2) CLK(3) VCC CLK(4) TMS I/O(B) GND I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) GND I/O(B) VCCIO(B) I/O(B) I/O(B) Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Function I/O(B) I/O(B) I/O(B) VCC I/O(B) I/O(B) VCC TCK VDED2 I/O(B) GND I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCCIO(B) I/O(B) I/O(B) (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 53 Eclipse II Family Data Sheet Rev. H QL8050 - 144 TQFP Pinout Diagram Pin 1 Pin 109 Eclipse II QL8050-7PF144C Pin 37 Pin 73 Figure 47: Top View of 144 Pin TQFP 54 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H QL8050 - 144 TQFP Pinout Table Table 39: QL8050 - 144 TQFP Pinout Table Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Function GND GND IO(A) IO(A) IO(A) IO(A) VCC IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) IO(A) TDI CLK(0) CLK(1) VCC IO(A) VDED IO(A) IO(A) GND VCCIO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) TDO GND IO(A) Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Function IO(A) GND IO(A) VCCIO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) IO(A) IO(A) VCC TRSTB VDED2 IO(A) IO(A) IO(A) GND IO(A) VCC IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) IO(A) VPUMP IO(A) Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Function IO(A) IO(B) GND IO(B) IO(B) IO(B) VCC IO(B) IO(B) INREF IO(B) IO(B) IO(B) VCCIO(B) IO(B) IO(B) IO(B) CLK(2) CLK(3) VCC CLK(4) TMS IO(B) GND VCCIO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) GND IO(B) Pin 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Function GND IO(B) VCCIO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) VCC IO(B) VCCIO(B) IO(B) IO(B) VCC TCK VDED2 IO(B) IO(B) GND IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) VCCIO(B) IO(B) IO(B) IO(B) (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 55 Eclipse II Family Data Sheet Rev. H QL8050 - 196 TFBGA Pinout Diagram Top Eclipse II QL8050-7PT196C Bottom 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Pin A1 Corner 56 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H QL8050 - 196 TFBGA Pinout Table Table 40: QL8050 - 196 TFBGA Pinout Table Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 Function IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) CLK(4) CLK(2) IO(B) IO(B) INREF IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) TMS VCC IO(B) IO(B) IO(B) IO(B) IO(B) IO(A) IO(A) IO(B) IO(B) IO(B) VCC IO(B) VCC IO(B) CLK(3) IO(B) VCC IO(B) IO(A) Ball C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 Function IO(A) IO(A) IO(B) IO(B) IO(B) IO(B) IO(B) VCCIO(B) VCCIO(B) VDED VCCIO(B) IO(B) IO(B) VPUMP IO(A) IO(A) IO(B) IO(B) IO(B) IO(B) VCCIO(B) GND GND GND GND IO(A) VCCIO(A) IO(A) IO(A) VCC IO(B) VCC IO(B) IO(B) VCCIO(B) GND GND GND GND IO(A) Ball F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J6 J7 J8 Function IO(A) IO(A) IO(A) IO(A) IO(B) TCK IO(B) VCC GND GND GND GND GND GND IO(A) VCC IO(A) IO(A) IO(B) IO(B) VDED2 VCCIO(B) GND GND GND GND GND GND VCCIO(A) TRSTB VDED2 VCC IO(B) IO(B) IO(B) VCC IO(B) GND GND GND Ball J9 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 Function GND GND IO(A) IO(A) IO(A) IO(A) IO(B) IO(B) IO(B) IO(B) VCCIO(B) VCCIO(A) GND GND VCCIO(A) VCCIO(A) IO(A) IO(A) IO(A) IO(A) IO(B) IO(B) IO(B) IO(B) IO(A) IO(A) VCCIO(A) VDED VDED VCCIO(A) VCC IO(A) IO(A) IO(A) IO(B) IO(B) IO(A) GND VCC TDI Ball M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Function VCC IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(B) IO(B) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) TDO IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) CLK(0) CLK(1) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 57 Eclipse II Family Data Sheet Rev. H QL8150 - 144 TQFP Pinout Diagram Pin 1 Pin 109 Eclipse II QL8150-7PF144C Pin 37 Pin 73 Figure 48: Top View of 144 Pin TQFP 58 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H QL8150 - 144 TQFP Pinout Table Table 41: QL8150 - 144 TQFP Pinout Table Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Function GND GND IO(A) IO(A) IO(A) IO(A) VCC IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) IO(A) TDI CLK(0) CLK(1) VCC IO(A) VDED IO(A) IO(A) GND VCCIO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) TDO GND IO(A) Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Function IO(A) GND IO(A) VCCIO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) IO(A) IO(A) VCC TRSTB VDED2 IO(A) IO(A) IO(A) GND IO(A) VCC IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) IO(A) VPUMP IO(A) Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Function IO(A) IO(B) GND IO(B) IO(B) IO(B) VCC IO(B) IO(B) INREF IO(B) IO(B) IO(B) VCCIO(B) IO(B) IO(B) IO(B) CLK(2) CLK(3) VCC CLK(4) TMS IO(B) GND VCCIO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) GND IO(B) Pin 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Function GND IO(B) VCCIO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) VCC IO(B) VCCIO(B) IO(B) IO(B) VCC TCK VDED2 IO(B) IO(B) GND IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) VCCIO(B) IO(B) IO(B) IO(B) (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 59 Eclipse II Family Data Sheet Rev. H QL8150 - 196 TFBGA Pinout Diagram Top Eclipse II QL8150-7PT196C Bottom 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Pin A1 Corner 60 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H QL8150 - 196 TFBGA Pinout Table Table 42: QL8150 - 196 TFBGA Pinout Table Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 Function IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) CLK(4) CLK(2) IO(B) IO(B) INREF IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) TMS VCC IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) VCC IO(B) VCC IO(B) CLK(3) IO(B) VCC IO(B) IO(A) Ball C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 Function IO(A) IO(A) IO(B) IO(B) IO(B) IO(B) IO(B) VCCIO(B) VCCIO(B) VDED VCCIO(B) IO(B) IO(A) VPUMP IO(A) IO(A) IO(B) IO(B) IO(B) IO(B) VCCIO(B) GND GND GND GND IO(B) VCCIO(A) IO(A) IO(A) VCC IO(B) VCC IO(B) IO(B) VCCIO(B) GND GND GND GND IO(A) Ball F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J6 J7 J8 Function IO(A) IO(A) IO(A) IO(A) IO(B) TCK IO(B) VCC GND GND GND GND GND GND IO(A) VCC IO(A) IO(A) IO(B) IO(B) VDED2 VCCIO(B) GND GND GND GND GND GND VCCIO(A) TRSTB VDED2 VCC IO(B) IO(B) IO(B) VCC IO(B) GND GND GND Ball J9 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 Function GND GND IO(A) IO(A) IO(A) IO(A) IO(B) IO(B) IO(B) IO(A) VCCIO(B) VCCIO(A) GND GND VCCIO(A) VCCIO(A) IO(A) IO(A) IO(A) IO(A) IO(B) IO(B) IO(B) IO(B) IO(A) IO(A) VCCIO(A) VDED VDED VCCIO(A) VCC IO(A) IO(A) IO(A) IO(B) IO(B) IO(B) GND VCC TDI Ball M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Function VCC IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) TDO IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) CLK(0) CLK(1) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 61 Eclipse II Family Data Sheet Rev. H QL8150 - 208 PQFP Pinout Diagram Eclipse II QL8150-7PQ208C 62 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H QL8150 - 208 PQFP Pinout Table Table 43: QL8150 - 208 PQFP Pinout Table Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Function I/O(A) I/O(A) GND GND I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) I/O(A) I/O(A) VCC I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) GND I/O(A) TDI CLK(0) CLK(1) VCC I/O(A) I/O(A) VDED I/O(A) I/O(A) I/O(A) GND VCCIO(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) Pin 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Function I/O(A) VCCIO(A) I/O(A) VCC I/O(A) I/O(A) GND TDO I/O(A) GND I/O(A) I/O(A) I/O(A) VDED I/O(A) GND I/O(A) VCCIO(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) I/O(A) GND VCC I/O(A) TRSTB VDED2 I/O(A) I/O(A) I/O(A) GND VCCIO(A) Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Function I/O(A) VCC I/O(A) I/O(A) VCC I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) I/O(A) VPUMP I/O(A) I/O(A) GND I/O(B) I/O(B) I/O(B) GND I/O(B) I/O(B) VCCIO(B) I/O(B) VCC I/O(B) I/O(B) I/O(B) I/O(B) INREF I/O(B) I/O(B) I/O(B) VCCIO(B) GND I/O(B) I/O(B) I/O(B) Pin 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Function I/O(B) CLK(2) VDED CLK(3) VCC CLK(4) TMS I/O(B) I/O(B) I/O(B) GND VCCIO(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCC I/O(B) I/O(B) I/O(B) VCCIO(B) I/O(B) I/O(B) GND I/O(B) I/O(B) GND I/O(B) I/O(B) I/O(B) GND I/O(B) VCCIO(B) I/O(B) I/O(B) VCC I/O(B) I/O(B) I/O(B) Pin 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCC I/O(B) VCCIO(B) GND I/O(B) I/O(B) I/O(B) VCC TCK VDED2 I/O(B) I/O(B) I/O(B) GND VCCIO(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCC I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCCIO(B) GND I/O(B) I/O(B) I/O(B) I/O(B) (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 63 Eclipse II Family Data Sheet Rev. H QL8150 - 280 LFBGA Pinout Diagram Top Eclipse II QL8150-7PT280C Bottom Pin A1 Corner 64 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H QL8150 - 280 LFBGA Pinout Table Table 44: QL8150 - 280 LFBGA Pinout Table Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 Function NC GND I/O(B) I/O(B) I/O(B) NC I/O(B) I/O(B) I/O(B) CLK(3) I/O(B) I/O(B) I/O(B) NC I/O(B) I/O(B) I/O(B) NC NC NC NC I/O(B) I/O(B) I/O(B) NC I/O(B) I/O(B) TMS CLK(2) I/O(B) I/O(B) NC I/O(B) I/O(B) I/O(B) NC GND NC I/O(B) NC I/O(B) I/O(B) VCCIO(B) NC I/O(B) I/O(B) VCCIO(B) Ball C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 Function I/O(B) VCCIO(B) I/O(B) I/O(B) I/O(B) VCCIO(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) CLK(4) I/O(B) I/O(B) I/O(B) INREF I/O(B) I/O(B) I/O(A) I/O(A) I/O(A) I/O(A) I/O(B) I/O(B) VCCIO(B) I/O(B) GND VCC VCC VDED VCC GND GND VCC VCC GND VPUMP I/O(A) VCCIO(A) NC Ball E19 F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G15 G16 G17 G18 G19 H1 H2 H3 H4 H5 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J15 J16 J17 J18 J19 K1 K2 K3 K4 K5 K15 Function NC NC NC I/O(B) I/O(B) GND VCC NC I/O(A) I/O(A) I/O(A) I/O(B) I/O(B) NC I/O(B) VCC VCC I/O(A) I/O(A) I/O(A) I/O(A) I/O(B) I/O(B) I/O(B) I/O(B) VCC VCC VDED2 I/O(A) I/O(A) I/O(A) I/O(B) I/O(B) VCCIO(B) I/O(B) GND VCC I/O(A) VCCIO(A) I/O(A) I/O(A) VDED2 TCK I/O(B) I/O(B) GND GND Ball K16 K17 K18 K19 L1 L2 L3 L4 L5 L15 L16 L17 L18 L19 M1 M2 M3 M4 M5 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N15 N16 N17 N18 N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R3 Function I/O(A) I/O(A) I/O(A) TRSTB I/O(B) I/O(B) VCCIO(B) I/O(B) VCC GND I/O(A) VCCIO(A) I/O(A) I/O(A) I/O(B) I/O(B) I/O(B) I/O(B) VCC VDED NC I/O(A) I/O(A) I/O(A) NC I/O(B) I/O(B) I/O(B) VCC VCC I/O(A) I/O(A) NC NC I/O(B) I/O(B) NC NC VCC GND I/O(A) I/O(A) I/O(A) I/O(A) I/O(B) I/O(B) VCCIO(B) Ball R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 Function I/O(B) GND GND VCC VCC GND GND VCC VCC VCC VDED GND I/O(A) VCCIO(A) I/O(A) I/O(A) I/O(B) I/O(B) I/O(A) I/O(A) I/O(A) NC I/O(A) I/O(A) I/O(A) I/O(A) NC I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) NC I/O(A) I/O(A) I/O(A) I/O(A) NC I/O(A) VCCIO(A) NC I/O(A) I/O(A) VCCIO(A) CLK(0) VCCIO(A) I/O(A) Ball U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Function I/O(A) NC VCCIO(A) I/O(A) TDO NC I/O(A) NC GND GND I/O(A) I/O(A) NC I/O(A) I/O(A) I/O(A) CLK(1) NC I/O(A) I/O(A) NC I/O(A) I/O(A) I/O(A) GND NC NC NC I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) TDI I/O(A) I/O(A) I/O(A) I/O(A) NC I/O(A) I/O(A) I/O(A) I/O(A) NC (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 65 Eclipse II Family Data Sheet Rev. H QL8250 - 208 PQFP Pinout Diagram Eclipse II QL8250-7PQ208C 66 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H QL8250 - 208 PQFP Pinout Table Table 45: QL8250 - 208 PQFP Pinout Table Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Function PLLRST(3) VCCPLL(3) GND GND I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) I/O(A) I/O(A) VCC INREF(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) GND I/O(A) TDI CLK(0) CLK(1) VCC CLK(2),PLLIN(2) CLK(3),PLLIN(1) VDED CLK(4),DEDCLK, PLLIN(0) I/O(B) I/O(B) GND VCCIO(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) INREF(B) I/O(B) I/O(B) Pin 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Function I/O(B) VCCIO(B) I/O(B) VCC I/O(B) I/O(B) GND TDO PLLOUT(1) GNDPLL(2) GND VCCPLL(2) PLLRST(2) VDED I/O(C) GND I/O(C) VCCIO(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) INREF(C) I/O(C) I/O(C) I/O(C) VCCIO(C) I/O(C) I/O(C) GND VCC I/O(C) TRSTB VDED2 I/O(D) I/O(D) I/O(D) GND VCCIO(D) Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Function I/O(D) VCC I/O(D) I/O(D) VCC I/O(D) I/O(D) I/O(D) INREF(D) I/O(D) I/O(D) I/O(D) I/O(D) VCCIO(D) I/O(D) I/O(D) VPUMP PLLOUT(0) GND GNDPLL(1) PLLRST(1) VCCPLL(1) I/O(E) GND I/O(E) I/O(E) VCCIO(E) I/O(E) VCC I/O(E) I/O(E) I/O(E) I/O(E) INREF(E) I/O(E) I/O(E) I/O(E) VCCIO(E) GND I/O(E) I/O(E) I/O(E) Pin 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Function CLK(5),PLLIN(3) CLK(6) VDED CLK(7) VCC CLK(8) TMS I/O(F) I/O(F) I/O(F) GND VCCIO(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) INREF(F) VCC I/O(F) I/O(F) I/O(F) VCCIO(F) I/O(F) I/O(F) GND I/O(F) PLLOUT(3) GNDPLL(0) GND VCCPLL(0) PLLRST(0) GND I/O(G) VCCIO(G) I/O(G) I/O(G) VCC I/O(G) I/O(G) I/O(G) Pin 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function I/O(G) INREF(G) I/O(G) I/O(G) I/O(G) I/O(G) VCC I/O(G) VCCIO(G) GND I/O(G) I/O(G) I/O(G) VCC TCK VDED2 I/O(H) I/O(H) I/O(H) GND VCCIO(H) I/O(H) I/O(H) I/O(H) I/O(H) INREF(H) VCC I/O(H) I/O(H) I/O(H) I/O(H) I/O(H) I/O(H) I/O(H) VCCIO(H) GND I/O(H) PLLOUT(2) GND GNDPLL(3) (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 67 Eclipse II Family Data Sheet Rev. H QL8250 - 280 LFBGA Pinout Diagram Top Eclipse II QL8250-7PT280C Bottom Pin A1 Corner 68 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H QL8250 - 280 LFBGA Pinout Table Table 46: QL8250 - 280 LFBGA Pinout Table Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 Function PLLOUT(3) GNDPLL(0) I/O(F) I/O(F) I/O(F) IOCTRL(F) I/O(F) I/O(F) I/O(F) CLK(7) I/O(E) I/O(E) I/O(E) IOCTRL(E) I/O(E) I/O(E) I/O(E) PLLRST(1) GND PLLRST(0) GND I/O(F) I/O(F) I/O(F) INREF(F) I/O(F) I/O(F) TMS CLK(6) I/O(E) I/O(E) IOCTRL(E) I/O(E) I/O(E) I/O(E) VCCPLL(1) GNDPLL(1) PLLOUT(0) I/O(F) VCCPLL(0) I/O(F) I/O(F) VCCIO(F) IOCTRL(F) I/O(F) I/O(F) VCCIO(F) Ball C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 Function CLK(5) /PLLIN(3) VCCIO(E) I/O(E) I/O(E) I/O(E) VCCIO(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(G) I/O(G) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) CLK(8) I/O(E) I/O(E) I/O(E) INREF(E) I/O(E) I/O(E) I/O(D) I/O(D) I/O(D) I/O(D) I/O(G) I/O(G) VCCIO(G) I/O(F) GND VCC VCC VDED VCC GND GND VCC VCC GND VPUMP I/O(D) VCCIO(D) INREF(D) Ball E19 F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G15 G16 G17 G18 G19 H1 H2 H3 H4 H5 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J15 J16 J17 J18 J19 K1 K2 K3 K4 K5 K15 Function IOCTRL(D) INREF(G) IOCTRL(G) I/O(G) I/O(G) GND VCC IOCTRL(D) I/O(D) I/O(D) I/O(D) I/O(G) I/O(G) IOCTRL(G) I/O(G) VCC VCC I/O(D) I/O(D) I/O(D) I/O(D) I/O(G) I/O(G) I/O(G) I/O(G) VCC VCC VDED2 I/O(D) I/O(D) I/O(D) I/O(G) I/O(G) VCCIO(G) I/O(G) GND VCC I/O(C) VCCIO(D) I/O(D) I/O(D) VDED2 TCK I/O(G) I/O(G) GND GND Ball K16 K17 K18 K19 L1 L2 L3 L4 L5 L15 L16 L17 L18 L19 M1 M2 M3 M4 M5 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N15 N16 N17 N18 N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R3 Function I/O(C) I/O(D) I/O(C) TRSTB I/O(H) I/O(H) VCCIO(H) I/O(H) VCC GND I/O(C) VCCIO(C) I/O(C) I/O(C) I/O(H) I/O(H) I/O(H) I/O(H) VCC VDED INREF(C) I/O(C) I/O(C) I/O(C) IOCTRL(H) I/O(H) I/O(H) I/O(H) VCC VCC I/O(C) I/O(C) IOCTRL(C) IOCTRL(C) I/O(H) I/O(H) IOCTRL(H) INREF(H) VCC GND I/O(C) I/O(C) I/O(C) I/O(C) I/O(H) I/O(H) VCCIO(H) Ball R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 Function I/O(H) GND GND VCC VCC GND GND VCC VCC VCC VDED GND I/O(C) VCCIO(C) I/O(C) I/O(C) I/O(H) I/O(H) I/O(A) I/O(A) I/O(A) IOCTRL(A) I/O(A) I/O(A) I/O(A) I/O(A) CLK(3) /PLLIN(1) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCCPLL(2) I/O(B) I/O(B) I/O(A) I/O(A) VCCPLL(3) I/O(A) VCCIO(A) INREF(A) I/O(A) I/O(A) VCCIO(A) CLK(0) VCCIO(B) I/O(B) Ball U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Function I/O(B) IOCTRL(B) VCCIO(B) I/O(B) TDO PLLRST(2) I/O(B) PLLOUT(2) GNDPLL(3) GND I/O(A) I/O(A) IOCTRL(A) I/O(A) I/O(A) I/O(A) CLK(1) CLK(4) DEDCLK/ PLLIN(0) I/O(B) I/O(B) INREF(B) I/O(B) I/O(B) I/O(B) GNDPLL(2) GND GND PLLRST(3) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) TDI CLK(2)/ PLLIN(2) I/O(B) I/O(B) I/O(B) IOCTRL(B) I/O(B) I/O(B) I/O(B) I/O(B) PLLOUT(1) (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 69 Eclipse II Family Data Sheet Rev. H QL8250 - 484 PBGA Pinout Diagram Top Eclipse II QL8250-7PS484C Bottom Pin A1 Corner A B C D E F G H J K L M N P R T U V W Y AA AB 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 70 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H QL8250 - 484 PBGA Pinout Table Table 47: QL8250 - 484 PBGA Pinout Table Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 Function NC PLLRST(3) I/O(A) I/O(A) I/O(A) NC I/O(H) IOCTRL(H) I/O(H) NC NC TCK I/O(G) I/O(G) I/O(G) NC I/O(G) I/O(G) I/O(F) GND PLLOUT(3) I/O(F) Ball C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 Function NC I/O(A) VCCPLL(3) PLLOUT(2) I/O(A) NC I/O(H) NC IOCTRL(H) NC I/O(H) NC I/O(G) NC I/O(G) I/O(G) NC I/O(G) I/O(F) GNDPLL(0) I/O(F) I/O(F) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(H) NC I/O(H) NC I/O(H) I/O(H) I/O(G) I/O(G) I/O(G) IOCTRL(G) I/O(G) I/O(G) I/O(F) VCCPLL(0) I/O(F) I/O(F) I/O(F) Ball E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 Function IOCTRL(A) I/O(A) I/O(A) I/O(A) NC I/O(H) NC I/O(H) I/O(H) I/O(H) VDED2 I/O(G) I/O(G) NC IOCTRL(G) I/O(G) INREF(G) NC I/O(F) I/O(F) NC I/O(F) I/O(A) INREF(A) NC I/O(A) I/O(A) VCCIO(A) VCCIO(H) I/O(H) VCCIO(H) I/O(H) VCCIO(H) VCCIO(G) I/O(G) VCCIO(G) NC VCCIO(G) NC I/O(F) I/O(F) IOCTRL(F) I/O(F) IOCTRL(F) Ball G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 Function NC NC I/O(A) I/O(A) I/O(A) I/O(A) GND I/O(H) I/O(H) NC I/O(G) GND NC NC I/O(G) VPUMP VCCIO(F) I/O(F) I/O(F) I/O(F) INREF(F) I/O(F) I/O(A) I/O(A) I/O(A) I/O(A) IOCTRL(A) VCCIO(A) I/O(H) GND VCC VCC VDED GND VCC VCC GND I/O(F) I/O(F) NC I/O(F) I/O(F) I/O(F) NC Ball J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 Function I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCC GND VCC VCC GND VCC GND VCC I/O(F) VCCIO(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) TDI I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) NC VCC VCC GND GND GND GND VCC VCC NC I/O(F) I/O(F) NC I/O(F) I/O(F) NC Ball L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 Function CLK(4), DEDCLK, PLLIN(0) CLK(0) CLK(2),PLLIN(2) I/O(A) I/O(A) I/O(A) GND GND GND GND GND GND GND VCC VCC CLK(6) VCCIO(F) I/O(F) CLK(8) I/O(F) NC I/O(F) I/O(B) I/O(B) I/O(B) CLK(3),PLLIN(1) NC VCCIO(B) CLK(1) VCC VCC GND GND GND GND GND GND GND I/O(E) I/O(E) I/O(E) CLK(7) CLK(5),PLLIN(3) TMS I/O(A) GND GNDPLL(3) GND I/O(A) I/O(H) I/O(H) INREF(H) I/O(H) I/O(H) I/O(H) NC NC NC NC I/O(G) I/O(G) I/O(G) PLLRST(0) I/O(F) I/O(F) I/O(F) (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 71 Eclipse II Family Data Sheet Rev. H Table 47: QL8250 - 484 PBGA Pinout Table (Continued) Ball N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 Function NC I/O(B) I/O(B) NC I/O(B) NC NC VCC VCC GND GND GND GND VCC VCC I/O(E) VCCIO(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) NC I/O(B) I/O(B) I/O(B) I/O(B) VCCIO(B) I/O(B) VCC GND VCC GND VCC VCC GND VDED Ball P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 Function I/O(E) NC I/O(E) NC I/O(E) I/O(E) I/O(E) I/O(B) INREF(B) I/O(B) I/O(B) I/O(B) NC I/O(B) GND VCC VCC GND VDED VCC VCC GND I/O(D) VCCIO(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCCIO(B) GND I/O(C) Ball T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 Function NC TRSTB GND NC I/O(D) NC I/O(D) GND I/O(E) I/O(E) NC NC IOCTRL(E) I/O(E) IOCTRL(B) I/O(B) IOCTRL(B) I/O(B) I/O(B) I/O(C) VCCIO(C) NC VCCIO(C) I/O(C) VCCIO(C) VCCIO(D) I/O(D) VCCIO(D) NC VCCIO(D) VCCIO(E) I/O(E) I/O(E) IOCTRL(E) NC INREF(E) I/O(B) Ball V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 Function I/O(B) I/O(B) I/O(B) I/O(B) NC I/O(C) I/O(C) NC I/O(C) NC VDED2 NC I/O(D) I/O(D) INREF(D) I/O(D) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(C) NC NC NC NC I/O(C) NC I/O(D) NC I/O(D) NC Ball W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 Function NC I/O(E) NC I/O(E) NC I/O(E) I/O(B) I/O(B) VCCPLL(2) I/O(C) I/O(C) I/O(C) I/O(C) IOCTRL(C) I/O(C) I/O(C) I/O(D) NC NC I/O(D) IOCTRL(D) I/O(D) I/O(D) I/O(E) PLLOUT(0) PLLRST(1) I/O(E) I/O(E) TDO PLLOUT(1) GND I/O(B) I/O(C) I/O(C) NC INREF(C) NC Ball AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 Function I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) NC NC I/O(D) I/O(E) GNDPLL(1) I/O(E) I/O(E) I/O(B) GNDPLL(2) PLLRST(2) I/O(B) I/O(B) I/O(C) I/O(C) IOCTRL(C) I/O(C) I/O(C) NC I/O(D) I/O(D) NC I/O(D) IOCTRL(D) I/O(D) I/O(D) I/O(E) GND VCCPLL(1) I/O(E) 72 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H QL8325 - 208 PQFP Pinout Diagram Eclipse II QL8325-7PQ208C (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 73 Eclipse II Family Data Sheet Rev. H QL8325 - 208 PQFP Pinout Table Table 48: QL8325 - 208 PQFP Pinout Table Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Function PLLRST(3) VCCPLL(3) GND GND I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) I/O(A) I/O(A) VCC INREF(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) GND I/O(A) TDI CLK(0) CLK(1) VCC CLK(2),PLLIN(2) CLK(3),PLLIN(1) VDED CLK(4),DEDCLK, PLLIN(0) I/O(B) I/O(B) GND VCCIO(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) INREF(B) I/O(B) I/O(B) Pin 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Function I/O(B) VCCIO(B) I/O(B) VCC I/O(B) I/O(B) GND TDO PLLOUT(1) GNDPLL(2) GND VCCPLL(2) PLLRST(2) VDED I/O(C) GND I/O(C) VCCIO(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) INREF(C) I/O(C) I/O(C) I/O(C) VCCIO(C) I/O(C) I/O(C) GND VCC I/O(C) TRSTB VDED2 I/O(D) I/O(D) I/O(D) GND VCCIO(D) Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Function I/O(D) VCC I/O(D) I/O(D) VCC I/O(D) I/O(D) I/O(D) INREF(D) I/O(D) I/O(D) I/O(D) I/O(D) VCCIO(D) I/O(D) I/O(D) VPUMP PLLOUT(0) GND GNDPLL(1) PLLRST(1) VCCPLL(1) I/O(E) GND I/O(E) I/O(E) VCCIO(E) I/O(E) VCC I/O(E) I/O(E) I/O(E) I/O(E) INREF(E) I/O(E) I/O(E) I/O(E) VCCIO(E) GND I/O(E) I/O(E) I/O(E) Pin 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Function CLK(5),PLLIN(3) CLK(6) VDED CLK(7) VCC CLK(8) TMS I/O(F) I/O(F) I/O(F) GND VCCIO(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) INREF(F) VCC I/O(F) I/O(F) I/O(F) VCCIO(F) I/O(F) I/O(F) GND I/O(F) PLLOUT(3) GNDPLL(0) GND VCCPLL(0) PLLRST(0) GND I/O(G) VCCIO(G) I/O(G) I/O(G) VCC I/O(G) I/O(G) I/O(G) Pin 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function I/O(G) INREF(G) I/O(G) I/O(G) I/O(G) I/O(G) VCC I/O(G) VCCIO(G) GND I/O(G) I/O(G) I/O(G) VCC TCK VDED2 I/O(H) I/O(H) I/O(H) GND VCCIO(H) I/O(H) I/O(H) I/O(H) I/O(H) INREF(H) VCC I/O(H) I/O(H) I/O(H) I/O(H) I/O(H) I/O(H) I/O(H) VCCIO(H) GND I/O(H) PLLOUT(2) GND GNDPLL(3) 74 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H QL8325 - 280 LFBGA Pinout Diagram Top Eclipse II QL8325-7PT280C Bottom Pin A1 Corner (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 75 Eclipse II Family Data Sheet Rev. H QL8325 - 280 LFBGA Pinout Table Table 49: QL8325 - 280 LFBGA Pinout Table Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 Function PLLOUT(3) GNDPLL(0) I/O(F) I/O(F) I/O(F) IOCTRL(F) I/O(F) I/O(F) I/O(F) CLK(7) I/O(E) I/O(E) I/O(E) IOCTRL(E) I/O(E) I/O(E) I/O(E) PLLRST(1) GND PLLRST(0) GND I/O(F) I/O(F) I/O(F) INREF(F) I/O(F) I/O(F) TMS CLK(6) I/O(E) I/O(E) IOCTRL(E) I/O(E) I/O(E) I/O(E) VCCPLL(1) GNDPLL(1) PLLOUT(0) I/O(F) VCCPLL(0) I/O(F) I/O(F) VCCIO(F) IOCTRL(F) I/O(F) I/O(F) VCCIO(F) Ball C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 Function CLK(5)/ PLLIN(3) VCCIO(E) I/O(E) I/O(E) I/O(E) VCCIO(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(G) I/O(G) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) CLK(8) I/O(E) I/O(E) I/O(E) INREF(E) I/O(E) I/O(E) I/O(D) I/O(D) I/O(D) I/O(D) I/O(G) I/O(G) VCCIO(G) I/O(F) GND VCC VCC VDED VCC GND GND VCC VCC GND VPUMP I/O(D) VCCIO(D) INREF(D) Ball E19 F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G15 G16 G17 G18 G19 H1 H2 H3 H4 H5 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J15 J16 J17 J18 J19 K1 K2 K3 K4 K5 K15 Function IOCTRL(D) INREF(G) IOCTRL(G) I/O(G) I/O(G) GND VCC IOCTRL(D) I/O(D) I/O(D) I/O(D) I/O(G) I/O(G) IOCTRL(G) I/O(G) VCC VCC I/O(D) I/O(D) I/O(D) I/O(D) I/O(G) I/O(G) I/O(G) I/O(G) VCC VCC VDED2 I/O(D) I/O(D) I/O(D) I/O(G) I/O(G) VCCIO(G) I/O(G) GND VCC I/O(C) VCCIO(D) I/O(D) I/O(D) VDED2 TCK I/O(G) I/O(G) GND GND Ball K16 K17 K18 K19 L1 L2 L3 L4 L5 L15 L16 L17 L18 L19 M1 M2 M3 M4 M5 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N15 N16 N17 N18 N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R3 Function I/O(C) I/O(D) I/O(C) TRSTB I/O(H) I/O(H) VCCIO(H) I/O(H) VCC GND I/O(C) VCCIO(C) I/O(C) I/O(C) I/O(H) I/O(H) I/O(H) I/O(H) VCC VDED INREF(C) I/O(C) I/O(C) I/O(C) IOCTRL(H) I/O(H) I/O(H) I/O(H) VCC VCC I/O(C) I/O(C) IOCTRL(C) IOCTRL(C) I/O(H) I/O(H) IOCTRL(H) INREF(H) VCC GND I/O(C) I/O(C) I/O(C) I/O(C) I/O(H) I/O(H) VCCIO(H) Ball R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 Function I/O(H) GND GND VCC VCC GND GND VCC VCC VCC VDED GND I/O(C) VCCIO(C) I/O(C) I/O(C) I/O(H) I/O(H) I/O(A) I/O(A) I/O(A) IOCTRL(A) I/O(A) I/O(A) I/O(A) I/O(A) CLK(3) /PLLIN(1) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCCPLL(2) I/O(B) I/O(B) I/O(A) I/O(A) VCCPLL(3) I/O(A) VCCIO(A) INREF(A) I/O(A) I/O(A) VCCIO(A) CLK(0) VCCIO(B) I/O(B) Ball U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Function I/O(B) IOCTRL(B) VCCIO(B) I/O(B) TDO PLLRST(2) I/O(B) PLLOUT(2) GNDPLL(3) GND I/O(A) I/O(A) IOCTRL(A) I/O(A) I/O(A) I/O(A) CLK(1) CLK(4) DEDCLK/ PLLIN(0) I/O(B) I/O(B) INREF(B) I/O(B) I/O(B) I/O(B) GNDPLL(2) GND GND PLLRST(3) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) TDI CLK(2)/ PLLIN(2) I/O(B) I/O(B) I/O(B) IOCTRL(B) I/O(B) I/O(B) I/O(B) I/O(B) PLLOUT(1) 76 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H QL8325 - 484 PBGA Pinout Diagram Top Eclipse II QL8325-7PS484C Bottom Pin A1 Corner A B C D E F G H J K L M N P R T U V W Y AA AB 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 77 Eclipse II Family Data Sheet Rev. H QL8325 - 484 PBGA Pinout Table Table 50: QL8325 - 484 PBGA Pinout Table Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 Function I/O(A) PLLRST(3) I/O(A) I/O(A) I/O(A) I/O(H) I/O(H) IOCTRL(H) I/O(H) N/C N/C TCK I/O(G) I/O(G) I/O(G) I/O(G) I/O(G) I/O(G) I/O(F) GND PLLOUT(3) I/O(F) I/O(A) GND GNDPLL(3) GND I/O(A) I/O(H) I/O(H) INREF(H) I/O(H) I/O(H) I/O(H) N/C N/C N/C I/O(G) I/O(G) I/O(G) I/O(G) PLLRST(0) I/O(F) I/O(F) I/O(F) Ball C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 Function I/O(A) I/O(A) VCCPLL(3) PLLOUT(2) I/O(A) I/O(H) I/O(H) I/O(H) IOCTRL(H) I/O(H) I/O(H) I/O(H) I/O(G) I/O(G) I/O(G) I/O(G) I/O(G) I/O(G) I/O(F) GNDPLL(0) I/O(F) I/O(F) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(H) I/O(H) I/O(H) I/O(H) I/O(H) I/O(H) I/O(G) I/O(G) I/O(G) IOCTRL(G) I/O(G) I/O(G) I/O(F) VCCPLL(0) I/O(F) I/O(F) I/O(F) Ball E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 Function IOCTRL(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(H) N/C I/O(H) I/O(H) I/O(H) VDED2 I/O(G) I/O(G) I/O(G) IOCTRL(G) I/O(G) INREF(G) I/O(G) I/O(F) I/O(F) I/O(F) I/O(F) I/O(A) INREF(A) I/O(A) I/O(A) I/O(A) VCCIO(A) VCCIO(H) I/O(H) VCCIO(H) I/O(H) VCCIO(H) VCCIO(G) I/O(G) VCCIO(G) N/C VCCIO(G) N/C I/O(F) I/O(F) IOCTRL(F) I/O(F) IOCTRL(F) Ball G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 Function I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) GND I/O(H) I/O(H) I/O(H) I/O(G) GND I/O(G) I/O(G) I/O(G) VPUMP VCCIO(F) I/O(F) I/O(F) I/O(F) INREF(F) I/O(F) I/O(A) I/O(A) I/O(A) I/O(A) IOCTRL(A) VCCIO(A) I/O(H) GND VCC VCC VDED GND VCC VCC GND I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) Ball J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 Function I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCC GND VCC VCC GND VCC GND VCC I/O(F) VCCIO(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) TDI I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) VCC VCC GND GND GND GND VCC VCC I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) Ball L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 Function CLK(4) DEDCLK/ PLLIN(0) CLK(0) CLK(2)/ PLLIN(2) I/O(A) I/O(A) I/O(A) GND GND GND GND GND GND GND VCC VCC CLK(6) VCCIO(F) I/O(F) CLK(8) I/O(F) I/O(F) I/O(F) I/O(B) I/O(B) I/O(B) CLK(3)/ PLLIN(1) I/O(B) VCCIO(B) CLK(1) VCC VCC GND GND GND GND GND GND GND I/O(E) I/O(E) I/O(E) CLK(7) CLK(5)/ PLLIN(3) TMS 78 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Table 50: QL8325 - 484 PBGA Pinout Table (Continued) Ball N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 Function I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCC VCC GND GND GND GND VCC VCC I/O(E) VCCIO(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCCIO(B) I/O(B) VCC GND VCC GND VCC VCC GND VDED Ball P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 Function I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) INREF(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) GND VCC VCC GND VDED VCC VCC GND I/O(D) VCCIO(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCCIO(B) GND I/O(C) Ball T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 Function N/C TRSTB GND N/C I/O(D) N/C I/O(D) GND I/O(E) I/O(E) I/O(E) I/O(E) IOCTRL(E) I/O(E) IOCTRL(B) I/O(B) IOCTRL(B) I/O(B) I/O(B) I/O(C) VCCIO(C) N/C VCCIO(C) I/O(C) VCCIO(C) VCCIO(D) I/O(D) VCCIO(D) N/C VCCIO(D) VCCIO(E) I/O(E) I/O(E) IOCTRL(E) I/O(E) INREF(E) I/O(B) Ball V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 Function I/O(B) I/O(B) I/O(B) I/O(B) I/O(C) I/O(C) I/O(C) N/C I/O(C) I/O(C) VDED2 N/C I/O(D) I/O(D) INREF(D) I/O(D) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(C) N/C I/O(C) I/O(C) I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) N/C Ball W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 Function I/O(D) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) I/O(B) VCCPLL(2) I/O(C) I/O(C) I/O(C) I/O(C) IOCTRL(C) I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) IOCTRL(D) I/O(D) I/O(D) I/O(E) PLLOUT(0) PLLRST(1) I/O(E) I/O(E) TDO PLLOUT(1) GND I/O(B) I/O(C) I/O(C) I/O(C) INREF(C) I/O(C) Ball AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 Function I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) I/O(D) I/O(D) I/O(D) I/O(E) GNDPLL(1) I/O(E) I/O(E) I/O(B) GNDPLL(2) PLLRST(2) I/O(B) I/O(B) I/O(C) I/O(C) IOCTRL(C) I/O(C) I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) IOCTRL(D) I/O(D) I/O(D) I/O(E) GND VCCPLL(1) I/O(E) (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 79 Eclipse II Family Data Sheet Rev. H Package Mechanical Drawings 100 VQFP Packaging Drawing 80 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H 144 TQFP Packaging Drawing (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 81 Eclipse II Family Data Sheet Rev. H 196 TFBGA Packaging Drawing 82 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H 208 PQFP Packaging Drawing (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 83 Eclipse II Family Data Sheet Rev. H 280 LFBGA Packaging Drawing 84 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H 484 PBGA Packaging Drawing (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 85 Eclipse II Family Data Sheet Rev. H Packaging Information The Eclipse II product family packaging information is presented in Table 51. Table 51: Packaging Options Device Device Information Pin 208 PQFP Package Definitionsa 280 LFBGA 484 BGA QL8325 Pitch 0.50 mm 0.80 mm 1.0 mm Pin 208 PQFP 280 LFBGA 484 BGA QL8250 Pitch 0.50 mm 0.80 mm 1.0 mm Pin 144 TQFP 196 TFBGA 208 PQFP 280 LFBGA QL8150 Pitch 0.50 mm 0.80 mm 0.50 mm 0.80 mm Pin 100 VQFP 144 TQFP 196 TFBGA QL8050 Pitch 0.50 mm 0.50 mm 0.80 mm Pin 100 VQFP 144 TQFP 196 TFBGA QL8025 Pitch 0.50 mm 0.50 mm 0.80 mm a. PQFP BGA VQFP TFBGA LFBGA TQFP = = = = = = Plastic Quad Flat Pack Ball Grid Array Very Thin Quad Flat Pack Thin Fine Pitch Ball Grid Array Low Profile Fine Pitch Ball Grid Array Thin Quad Flat Pack Ordering Information QL QuickLogic Device Part Number: 8025, 8050, 8150,8250, 8325 Operating Range: C = Commercial I = Industrial M = Military 8025 -6 PV100 C Speed Grade: 6 - Fast 7 - Faster Package Lead Count: 8 - Fastest PV100 (PVN100)* = 100-pin VQFP PF144 (PFN144)* = 144-pin TQFP PQ208 (PQN208)* = 208-pin PQFP PT196 (PTN196)* = 196-ball TFBGA (0.8 mm) PT280 (PTN280)* = 280-ball LFBGA (0.8 mm) PS484 = 484-ball PBGA (1.0 mm) * Lead-free packaging is available, contact QuickLogic regarding availability (see Contact Information). 86 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation Eclipse II Family Data Sheet Rev. H Contact Information Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932 57 9011 (Europe - except Germany/Benelux) +(49) 89 930 86 170 (Germany/Benelux) +(86) 21 6867 0273 (Asia - except Japan) +(81) 45 470 5525 (Japan) E-mail: Sales: info@quicklogic.com www.quicklogic.com/sales Support: www.quicklogic.com/support Internet: www.quicklogic.com Revision History Revision A Preliminary Rev. A Rev. B Rev. C Rev. D Rev. E Rev. F Rev. G Date August 2002 December 2002 January 2003 May 2003 December 2003 January 2004 May 2004 January 2005 Comments Brian Faith, Judd Heape, and Andreea Rotaru Brian Faith and Andreea Rotaru Brian Faith and Andreea Rotaru Brian Faith and Kathleen Murchek Brian Faith, Mehul Kochar, and Kathleen Murchek Brian Faith and Kathleen Murchek Brian Faith, Mehul Kochar, and Kathleen Murchek Brian Faith, Mehul Kochar, and Kathleen Murchek Brian Faith, Mehul Kochar, and Kathleen Murchek Added QL8150 - 280 device. Updated PLL information. Added lead-free packaging information. Rev. H March 2005 Copyright and Trademark Information Copyright (c) 2002-2005 QuickLogic Corporation. All Rights Reserved. The information contained in this document is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic and the QuickLogic logo, pASIC, ViaLink, DeskFab, QuickRAM, QuickPCI and QuickWorks are registered trademarks of QuickLogic Corporation; Eclipse, EclipsePlus, Eclipse II, QuickFC, QuickDSP, QuickDR, QuickSD, QuickTools, QuickCore, QuickPro, SpDE, WebASIC, and WebESP are trademarks of QuickLogic Corporation. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 87 |
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