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| TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91CU10 Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts (NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP91CU10 Low-Voltage CMOS 16-Bit Microcontrollers TMP91CU10F 1. Outline and Device Characteristics The TMP91CU10 is an original Toshiba TLCS-900/L1 Series 16-bit microcontroller. The TMP91CU10 integrates a 16-bit CPU, ROM, RAM, multi-functional timer and event counter, general-purpose serial interface, an A/D converter and various other units in a single chip, and has been developed for controlling medium- to large-scale equipment. The TMP91CU10 is housed in a 100-pin mini flat package. The device characteristics are as follows: (1) Original high-speed 16-bit CPU (900/H CPU) TLCS-90/900 instruction mnemonics (upwards compatible) 16-Mbyte linear address space General-purpose registers and register bank system 16-bit multiplication/division and bit transfer/arithmetic instructions High-speed DMA: 4 channels (1.18 s at 13.5 MHz) (1.0 s at 16 MHz) (2) Minimum instruction execution time 400 ns at 10 MHz (VCC = 2.0 V) for mask ROM products only 296 ns at 13.5 MHz (VCC = 3.0 V) (3) Internal RAM: 3 Kbytes Internal ROM: 96 Kbytes (4) External memory expansion Can be expanded up to 16 Mbytes (for both programs and data). AM8/16 pin (selects the external data bus width) Can mix 8- and 16-bit external data buses (dynamic bus sizing). (5) Chip Select and Wait controller: 3 blocks (6) 8-bit timer: 8 channels Including event count function: 2 channels 000707EBP1 For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice. 91CU10-1 2003-03-31 TMP91CU10 (7) 16-bit timer and event counter: 2 channels (8) General-purpose serial interface: 3 channels UART and Synchronous modes (9) 10-bit A/D converter: 8 channels (10) Watchdog timer (11) Interrupt functions 2 CPU interrupts (SWI instruction and Illegal instruction) 26 internal interrupts 10 external interrupts (12) I/O ports: 80 pins (13) Standby function: 4 Halt modes (Run, Idle2, Idle1, Stop) (14) Clock gear function Clock gear: High-frequency clock can be changed from fc to fc/16. Dual clock operation (15) Low operating voltage 2.0 to 3.6 V (16) Package Compact 14 mm 14 mm 1.4 mm (0.5 mm pitch) 7-level priority can be set. 7-level priority can be set. 91CU10-2 2003-03-31 TMP91CU10 AN0 to AN7 (P50 to P57) AVcc AVss VREFL VREFH 10-BIT 8-CH A/D CONVERTER DVCC [3] CPU (TLCS-900/H) DVSS [3] OSC1 Clock Gear OSC2 XT1 (P96) XT2 (P97) CLK ALE EA RESET X1 X2 TXD0 (P90) RXD0 (P91) SCLK0/ CTS0 (P92) TXD1 (P93) RXD1 (P94) SCLK1 (P95) TXD2 (P60) RXD2 (P61) SCLK2/ CTS2 (P62) TI0/INT1 (P70) TO1 (P71) 8-BIT TIMER (TIMER 0) 8-BIT TIMER (TIMER 1) 8-BIT TIMER (TIMER 2) TO3/INT2 (P72) TI4/INT3 (P73) TO5 (P74) 8-BIT TIMER (TIMER 3) 8-BIT TIMER (TIMER 4) 8-BIT TIMER (TIMER 5) 8-BIT TIMER (TIMER 6) TO7/INT4 (P75) 8-BIT TIMER (TIMER 7) SERIAL I/O (CH.2) SERIAL I/O (CH.1) SERIAL I/O (CH.0) XWA XBC XDE XHL XIX XIY XSP W B D H A C E L IX IY IZ SP 32 bits SR F PC RD (P30) WR (P31) HWR (P32) BUSRQ (P34) BUSAK (P35) R/ W (P36) AM8/16 P37 (P00 to P07) AD0 to AD7 (P10 to P17) AD8/A8 to AD15/A15 (P20 to P27) A0/A16 to A7/A23 PA0 to PA7 P63, P65 to P67 WATCHDOG TIMER PORT 0 3 KB RAM PORT 1 PORT 2 PORT A PORT 6 96 KB RAM CS/WAIT CONTROLLER (3-BLOCK) CS0 (P40) CS1 (P41) CS2 (P42) WAIT (P33) NMI INTO (P64) TI8/INT5 (P80) TI9/INT6 (P81) TO8 (P82) TO9 (P83) TIA/INT7 (P84) INTERRUPT CONTROLLER 16-BIT TIMER (TIMER 8) 16-BIT TIMER (TIMER 9) TIB/INT8 (P85) TOA/TOB (P86) ( ): Default function after reset Figure 1.1 TMP91CU10F Block Diagram 91CU10-3 2003-03-31 TMP91CU10 2. Pin Assignment and Functions The assignment of input and output pins for the TMP91CU10, their names and functions are described as follows: 2.1 Pin Assignment Figure 2.1.1 shows the pin assignment of the TMP91CU10. P66 P67 DVSS P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 VREFH VREFL AVSS AVCC P70/TI0/INT1 P71/TO1 P72/TO3/INT2 P73/TI4/INT3 P74/TO5 P75/TO7/INT4 P80/TI8/INT5 P81/TI9/INT6 P82/TO8 P83/TO9 P84/TIA/INT7 P85/TIB/INT8 P86/TOA/TOB P90/TXD0 P91/RXD0 P92/SCLK0/CTS0 P93/TXD1 P94/RXD1 P95/SCLK1 AM8/16 CLK DVCC 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P65 P64/INT0 P63 P62/SCLK2/CTS2 P61/RXD2 P60/TXD2 P42/CS2 P41/CS1 P40/CS0 P37 P36/R/W P35/BUSAK P34/BUSRQ P33/WAIT P32/HWR P31/WR P30/RD P27/A7/A23 P26/A6/A22 P25/A5/A21 P24/A4/A20 P23/A3/A19 P22/A2/A18 P21/A1/A17 P20/A0/A16 DVCC DVSS NMI P17/AD15/A15 P16/AD14/A14 P15/AD13/A13 P14/AD12/A12 P13/AD11/A11 P12/AD10/A10 P11/AD9/A9 P10/AD8/A8 P07/AD7 P06/AD6 DVSS X1 X2 EA RESET P96/XT1 P97/XT2 TEST1 TEST2 PA0 PA1 PA2 26 27 28 29 30 31 32 33 34 35 36 37 50 49 48 47 46 45 44 43 42 41 40 39 38 P05/AD5 P04/AD4 P03/AD3 P02/AD2 P01/AD1 P00/AD0 DVCC ALE PA7 PA6 PA5 PA4 PA3 Figure 2.1.1 Pin Assignment diagram 91CU10-4 2003-03-31 TMP91CU10 2.2 Pin Names and Functions The names of the input/output pins and their functions are described in Table 2.2.1. Table 2.2.1 Pin names and Functions (1/3) Pin name P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30 RD Number of pins 8 8 I/O I/O I/O Functions Port 0: I/O port that allows I/O to be selected at the bit level Address (lower): Bits 0 to 7 for address and data bus Port 1: I/O port that allows I/O to be selected at the bit level Address and data (upper): Bits 8 to 15 for address and data bus Address: Bits 8 to 15 for address bus Port 2: I/O port that allows I/O to be selected at the bit level (with pull-up resistor) Address: Bits 0 to 7 for address bus Address: Bits 16 to 23 for address bus Port 30: Output port Read: Strobe signal for reading external memory When P3 I/O I/O Output I/O Output Output Output Output Output Output I/O Output I/O Input I/O Input I/O Output I/O Output I/O I/O Output I/O Output I/O Output Input Input I/O Output I/O Input I/O I/O Input I/O I/O Input I/O 8 1 P31 WR 1 1 1 1 P32 HWR P33 WAIT P34 BUSRQ P35 BUSAK 1 P36 R/ W P37 P40 CS0 1 1 1 1 1 8 1 1 1 P41 CS1 P42 CS2 P50 to P57 AN0 to AN7 P60 TXD2 P61 RXD2 P62 SCLK2 CTS2 P63 P64 INT0 P65 to P67 1 1 3 Note: A DMAC controller's internal memory or I/O devices cannot be accessed using BUSRQ and BUSAK . 91CU10-5 2003-03-31 TMP91CU10 Table 2.2.1 Pin names and Function (2/3) Pin name P70 TI0 INT1 P71 TO1 P72 TO3 INT2 P73 TI4 INT3 P74 TO5 P75 TO7 INT4 P80 TI8 INT5 P81 TI9 INT6 P82 TO8 P83 TO9 P84 TIA INT7 P85 TIB INT8 P86 TOA TOB P90 TXD0 P91 RXD0 P92 SCLK0 CTS0 Number of pins 1 I/O I/O Input Input I/O Output I/O Output Input I/O Input Input I/O Output I/O Output Input I/O Input Input I/O Input Input I/O Output I/O Output I/O Input Input I/O Input Input I/O Output Output I/O Output I/O Input I/O I/O Input I/O Output I/O Input I/O I/O I/O Input I/O Output Functions Port 70: I/O port Timer Input 0: Timer 0 input pin Interrupt Request pin 1: Interrupt request on rising edge Port 71: I/O port Timer Output 1: Timer 0 or 1 output Port 72: I/O port Timer Output 3: Timer 2 or 3 output Interrupt Request pin 2: Interrupt request on rising edge Port 74: I/O port Timer Input 4: Timer 4 input Interrupt Request pin 3: Interrupt request on rising edge Port 75: I/O port Timer Output 5: Timer 4 or 5 output Port 76: I/O port Timer Output 7: Timer 6 or 7 output Interrupt Request pin 4: Interrupt request on rising edge Port 80: I/O port Timer Input 8: Timer 8 count or capture trigger signal input Interrupt Request pin 5: Interrupt request pin with programmable rising / falling edge Port 81: I/O port Timer Input 9: Timer 8 count or capture trigger signal input Interrupt Request pin 6: Interrupt request on rising edge Port 82: I/O port Timer Output 8: Timer 8 output pin Port 83: I/O port Timer Output 9: Timer 9 output pin Port 84: I/O port Timer Input A: Timer 9 count or capture trigger signal input Interrupt Request pin 7: Interrupt request pin with programmable rising / falling edge Port 85: I/O port Timer Input B: Timer 9 count or capture trigger signal input Interrupt Request pin 8: Interrupt request on rising edge Port 86: I/O port Timer Output A: Timer A output pin Timer Output B: Timer B output pin Port 90: I/O port Serial Send Data 0 (programmable open drain) Port 91: I/O port Serial Receive Data 0 Port 92: I/O port Serial Clock I/O 0 Serial Data Send Enable 0 (Clear to Send) Port 93: I/O port Serial Send Data 1 (programmable open drain) Port 94: I/O port Serial Receive Data 1 Port 95: I/O port Serial Clock I/O 1 Port 96: I/O port (open drain output) Low-frequency oscillator connecting pin Port 97: I/O port (open drain output) Low-frequency oscillator connecting pin 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 P93 TXD1 P94 RXD1 P95 SCLK1 P96 XT1 P97 XT2 1 1 1 1 1 91CU10-6 2003-03-31 TMP91CU10 Table 2.2.1 Pin names and Function (3/3) Pin name PA0 to PA7 ALE NMI Number of pins 3 1 1 1 1 1 I/O I/O Port A0 to A7: I/O ports Functions Output Input Output Input Input Address Latch Enable (can be disabled for reducing noise.) Non-Maskable Interrupt Request pin: Interrupt request pin with programmable falling edge or both edges. Clock Output: Outputs (external input clock/4) clock. Pulled-up during reset The Vcc pin should be connected. Address Mode: Selects external data bus width. The Vcc pin should be connected. The data bus width for external access is set by the Chip Select/WAIT Control register and the Port 1 Control register. CLK EA AM8/ 16 TEST1/TEST2 2 RESET Output /Input Input Input Input TEST1 Should be connected with TEST2 pin. Reset: Initializes LSI. (With pull-up resistor) Reference power supply input pin for AD converter (H) Reference power supply input pin for AD converter (L) Power supply pin for AD converter GND power supply pin for AD converter (0 V) 1 1 1 1 1 2 VREFH VREFL AVCC AVSS X1/X2 I/O Output /Input Oscillator connecting pin TEST1 should be connected with TEST2 pin. Power supply pin GND pin (0 V) TEST1/TEST2 2 DVCC1 DVSS 3 3 Note: All pins that have built-in pull-up / pull-down resistors (other than the RESET pin) can be disconnected from their built-in pull-up / pull-down resistors by software. 91CU10-7 2003-03-31 TMP91CU10 3. Operation This section describes the functions and basic operations of the TMP91CU10. Please also refer to Section 7, Precautions, which describes some points requiring careful attention. 3.1 CPU TMP91CU10 device has a built-in high-performance 16-bit CPU (TLCS-900/L1 CPU). (For a basic description of the CPU operation, see the information on the TLCS-900/L1 CPU). This section describes some CPU functions unique to the TMP91CU10 that are not described in the description of the TLCS-900/L1 CPU. 3.1.1 Reset Figure 3.1.1 shows the basic timing chart for a Reset operation. To reset a TMP91CU10 device, the RESET pin must be kept at 0 for at least ten consecutive system clock cycles (equivalent to 160 states: 24 s at 13.5 MHz). The pin must be kept within the specified operating voltage range and stable clock oscillation must be maintained. When a Reset signal is received, the CPU is set as follows: The Program Counter (PC) is set according to the Reset Vector that is stored from FFFF00H to FFFF02H. PC (7 to 0) data in location FFFF00H PC (15 to 8) data in location FFFF01H PC (23 to 16) data in location FFFF02H The Stack Pointer (XSP) for System mode is set to 100H. The Note 1: Resetting makes no change to the contents of any registed in the CPU except the Program Counter (PC), Status Register (SR) and Stack Pointer (XSP), nor to the data in the internal RAM. Note 2: The CLK pin is pulled up during a Reset. When the voltage is externally reduced, there is a possibility of malfunction. 91CU10-8 2003-03-31 45 Total of 220 1 cycles omitted 1 cycles omitted X1 CLK Sampling RESET Sampling A16 to A23 (P20 to P27 Input mode) (P40 to P41 Input mode) CS0, CS1 CS2 (P42 Input mode) R/W (P36 Input mode) ALE AD0 to AD15 Read Address Address RD (Starts 0WAIT Read Reset release.) cycle after Figure 3.1.1 TMP91CU10F Reset Timing Chart AD0 to AD15 91CU10-9 Address Data output Address WR HWR (P32 Input mode) P20 to P27, P42 (Input mode) (Input mode) (Input mode) (Output mode: open drain output) P96, P97 Write P32 to P37, P40 to P41 P60 to P67, P70 to P73 P80 to P87, P90 to P95 P50 to P57, A0 to A7 Symbols: High impedance TMP91CU10 2003-03-31 Internal pull-up or Internal pull-down TMP91CU10 3.2 Memory Map The TMP91CU10 uses an address area of 128 bytes as the internal I/O area, which is allocated from addresses 000000H to 00007FH. The CPU can access this internal I/O using a short internal code in Direct Addressing Mode. Figure 3.2.1 shows the memory map and the accessible area for each CPU addressing mode. MCU MODE 000000H Internal I/O (128 bytes) 000080H Internal RAM (3 Kbytes) 000100H Direct area (n) 000C80H 64 Kbytes area (nn) 010000H External memory FE8000H 16-Mbyte area (R) (-R) (R+) (R-R8/16) (R+d8/16) (nnn) Internal ROM (96 Kbytes) FFFF00H Vector Table (256 bytes) FFFFFFH ( =Internal area) Note: The stack pointer XSP is set to 100H after a Reset. Figure 3.2.1 TMP91CU10 Memory Map 91CU10-10 2003-03-31 TMP91CU10 4. 4.1 Electrical Characteristics Absolute Maximum Ratings "X" used in an expression shows a frequency for the clock fFPH selected by SYSCR1 Parameter Power Supply Voltage Input Voltage Output Current (total) Output Current (total) Power Dissipation (Ta=85 C) Soldering Temperature (10 s) Storage Temperature Operating Temperature Symbol Vcc VIN IOL IOH PD TSOLDER TSTG TOPR Rating 0.5 to 4.0 0.5 to Vcc + 0.5 120 80 600 260 -65 to 150 40 to 85 Unit V V mA mA mW C C C Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. 4.2 DC Characteristics (1/2) Parameter Power Supply Voltage AVCC=VCC AVSS=VSS=0V Symbol VCC Condition fc = 4 to 16 MHz fs = 30 to 34 kHz (Ta = 40 to 85 C) fc = 4 to 10 MHz fs = 30 to 34 kHz (Ta = 40 to 85 C) Min Typ. (Note1) Max Unit 2.7 3.6 2.2 (Note 2) 0.8 0.4 0.3 Vcc 0.3 0.25 Vcc 0.3 0.2 Vcc 2.2 2.0 0.7 Vcc 0.75 Vcc Vcc+0.3 V V AD0 to 15 Input Low Volt ag Port2 to A(exceptP87, P5) RESET , NIMI , INT0 EA , AM8/ 16 VIL VIL1 VIL2 VIL3 VIL4 VIH VIH1 VIH2 VIH3 VIH4 Vcc 2.7 V Vcc < 2.7 V Vcc = 2.7 to 3.6 V X1, Port5 AD0 to 15 Vcc 2.7 V Input High Voltage Vcc < 2.7 V Port2 to A(exceptP87) RESET , NIMI , INT0 Vcc = 2.7 to 3.6 V EA , AM8/ 16 X1 Vcc 0.3 0.8 Vcc Note 1: Typical values are for Ta = 25 C and Vcc = 5 V unless otherwise noted. Note 2: The operation of the A/D converter is guaranteed at Vcc = 2.7 to 3.6 V. 91CU10-182 2003-03-31 TMP91CU10 4.2 DC Characteristics (2/2) Parameter Symbol VOL VOH1 Condition IOL = 1.6 mA (Vcc = 2.7 to 3.6 V) IOH = 400 A (Vcc = 2.2 V 10%) IOH = 400 A (Vcc = 3 V 10 %) VEXT = 1.5 V REXT = 1.1 k (Vcc = 3 V 10%) 0.0 0.2 VIN VIN Vcc Vcc 0.2 Min Typ. (Note1) Max 0.45 Unit Output Low Voltage 1.4 2.4 1.0 3.5 V Output High Voltage VOH2 IDAR (Note2) ILI ILO VSTOP RRST CIO VTH PKL PKH Icc Darlington Drive Current (8 Output Pins max.) Input Leakage Current Output Leakage Current Power Down Voltage (@STOP,RAM Back up) RESET Pull Up Resister Pin Capacitance Schmitt Width RESET , NIMI , INT0 mA 0.02 0.05 2.0 50 80 5 10 6.0 250 500 10 0.4 1.0 200 500 300 500 14 10 6 1.1 8.0 4.5 2.5 0.5 40 32 18 6 23 17 11 2.8 12 9.5 6.5 1.5 55 45 35 20 10 0.2 20 50 A A mA mA k A V k pF V VIL2 = 0.2 Vcc, VIH2 = 0.8 Vcc Vcc = 3 V 10% Vcc = 2.2 V 10% fc = 1 MHz Programmable Pull Down Resistor Programmable Pull Up Resistor NORMAL2 RUN IDLE2 IDLE1 NORMAL2 RUN IDLE2 IDLE1 SLOW RUN IDLE2 IDLE1 STOP Vcc = 3 V 10% Vcc = 2.2 V 10% Vcc = 3 V 10% Vcc = 2.2 V 10% Vcc = 3 V 10% fc = 13.5 MHz (Typ. : Vcc = 3.0 V) Vcc = 2.2 V 10 fc = 10 MHz (Typ. : Vcc = 2.2 V) Vcc = 3 V 10% fs = 32.768 kHz (Typ. : Vcc = 3.0 V) Ta Ta Ta 50 C 70 C 85 C Vcc = 2.0 to 3.6 V 30 80 80 80 Note 1: Typical values are for Ta = 25 C and Vcc = 5 V unless otherwise noted. Note 2: I-DAR is guaranteed for up to eight ports. Note 3: ICC measurement condition (NORMAL2): All functions are operational; output pins are open and input pins are fixed. 91CU10-183 2003-03-31 TMP91CU10 4.3 AC Characteristics (1) Vcc 2.5 to 3.6 V No. 1 2 3 4 5 6 7 8 9 Parameter Osc. Period (=x) CLK width A0 to A23 Valid CLK Hold CLK Valid A0 to A23 Hold A0 to A15 Valid ALE Fall ALE Fall A0 to A15 Hold ALE High Width ALE Fall RD / WR Fall RD / WR Fall RD / WR Fall Symbol tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD tAWH tAWL tCW tAPH tAPH2 tCP Variable Min 62.5 2x 0.5x 1.5x 0.5x 0.5x x 0.5x 0.5x x 1.5x 0.5x 40 20 70 15 20 40 25 20 25 50 25 3.0x 3.5x 2.0x 2.0x 0 x 2.0x 2.0x 0.5x 15 40 55 15 3.5x 3.0x 2.0x + 0 2.5x 2.5x + 50 200 120 90 80 40 55 65 60 12.5 MHz Min 80 120 20 50 25 20 40 15 20 55 70 15 130 215 100 120 0 65 120 105 25 190 160 160 80 250 200 16 MHz Min 74 108 7 26 30 7 24 10 7 34 61 0 182 194 103 108 0 54 108 68 5 199 162 148 65 235 359 Max 31250 Max Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns RD / WR Rise ALE Rise 10 A0 to A15 Valid 11 A0 to A23 Valid 12 RD / WR Rise A0 to A23 Hold 13 A0 to A15 Valid D0 to D15 Input 14 A0 to A23 Valid D0 to D15 Input 15 16 17 18 RD Fall D0 to D15 Input RD Low Pulse Width RD Rise D0 to D15 Hold RD Rise A0 to A15 Output 19 WR Low Pulse Width 20 D0 to D15 Valid 21 22 A0 to A23 Valid 23 A0 to A15 Valid 24 RD/WR Fall WR Rise WAIT Input WAIT Input WR Rise D0 to D15 Hold (1WAIT + n mode) (1WAIT + n mode) WAIT Hold (1WAIT + n mode) 25 A0 to A23 Valid PORT Input 26 A0 to A23 Valid PORT Hold 27 WR Rise PORT Valid AC Measuring Conditions Output Level: High 2.2 V/Low 0.8 V, CL=50 pF (However, CL = 100 pF for AD0 to AD15, A0 to A23, ALE RD , WR , HWR , R/ W , CLK ) Input Level: High 2.4 V/Low 0.45 V (AD0 to AD15) High 0.8 Vcc/Low 0.2 Vcc (except for AD0 to AD15) 91CU10-184 2003-03-31 TMP91CU10 (2) Vcc 2.2 V 10 % No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Parameter Osc. Period (=x) CLK width A0 to A23 Valid CLK Hold CLK Valid A0 to A23 Hold A0 to A15 Valid ALE Fall ALE Fall A0 to A15 Hold ALE High Width ALE Fall RD / WR Fall RD / WR Fall RD / WR Fall Symbol tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD tAWH tAWL tCW tAPH tAPH2 tCP 2.0x 0 x 100 2x 0.5x 1.5x 0.5x 0.5x x Variable Min 40 30 80 35 35 35 40 50 40 3.0x 3.5x 2.0x 40 110 125 115 10 MHz Min 100 160 20 70 15 15 40 15 10 50 100 10 190 225 85 160 0 75 Max 31250 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 60 0.5x 0.5x x 50 1.5x 0.5x RD / WR Rise ALE Rise A0 to A15 Valid A0 to A23 Valid RD / WR Rise A0 to A23 Hold A0 to A15 Valid D0 to D15 Input A0 to A23 Valid D0 to D15 Input RD Fall D0 to D15 Input RD Low Pulse Width RD Rise D0 to D15 Hold RD Rise A0 to A15 Output WR Low Pulse Width 25 40 120 40 3.5x 3.0x 130 100 2.0x 2.0x 0.5x 160 80 10 220 200 200 2.5x 120 200 200 200 130 D0 to D15 Valid A0 to A23 Valid A0 to A15 Valid RD / WR Fall WR Rise WR Rise D0 to D15 Hold WAIT Input ns ns ns ns ns ns (1WAIT + n mode) WAIT Input WAIT Hold (1WAIT + n mode) 2.0x + 0 (1WAIT + n mode) A0 to A23 Valid PORT Input A0 to A23 Valid PORT Hold WR Rise PORT Valid 2.5x + 50 AC Measuring Conditions Output Level: High Input Level: High 0.7 Vcc/Low 0.3 V 0.9 Vcc/Low 0.1 V Vcc , CL = 50 pF Vcc 91CU10-185 2003-03-31 TMP91CU10 (3) Read Cycle tOSC X1 tCLK CLK tAK A0 to A23 tKA CS0 to 2 R/ W tAWH tAWL tCW WAIT tAPH tAPH2 Port Input tCA tRR tACL tLC AD0 to AD15 tAL A0 to AD15 tLA tRD tADL D0 to D15 tCL tHR tADH RD tACH tRAE tLL ALE 91CU10-186 2003-03-31 TMP91CU10 (4) Write Cycle X1 CLK A0 to A23 CS0 to 2 R/ W WAIT Port Output WR , HWR tWW tDW AD0 to A15 A0 to A15 D0 to D15 tWD ALE 91CU10-187 2003-03-31 TMP91CU10 4.4 A/D Conversion Characteristics AVCC = VCC, AVSS = VSS Parameter Symbol VREFH VREFL VAIN IREF (VREFL = 0 V) Vcc Vss VREFL 0.5 0.02 1 10 Min 0.2 V Typ. Vcc Vss Vcc Max Vss + 0.2 V VREFH 1.5 5.0 3 Unit V mA A LSB Analog Reference Voltage (+) Analog Reference Voltage ( ) Analog Input Voltage Range Analog Current for Analog Reference Voltage Vcc = 3 V 10% Note 1: 1LSB = (VREFH - VREFL) / 2 [V] Note 2: The operation of the A/D converter is guaranteed only when fc (the high frequency oscillator) is used (it is not guaranteed when fs is used). It is guaranteed when fFPH 4 MHz. Note 3: The value Icc includes the current which flows through the AVCC pin. Note 4: The operation of the TMP91CU10 is guaranteed within 2.7 to 3.6 V. 91CU10-188 2003-03-31 TMP91CU10 4.5 Serial Channel Timing (1) I/O Interface Mode SCLK Input Mode Parameter SCLK Cycle Output Data Rising Falling SCLK Edge Symbol tSCY or tOSS Edge* of tOHS tHSR tSRD Variable Min 16x tSCY/2 5x 50 32.768 kHz Min 488 s 91.5 s Note ) 13.5 MHz Min 1.18 172 Unit s ns Max Max Max SCLK Rising Edge or Falling Edge * Output Data Hold SCLK Rising Edge or Falling Edge* Input Data Hold SCLK Rising Edge or Falling Edge* Effective Data Input 5x 100 0 tSCY 5x 100 152 s 0 336 s 270 0 714 ns ns ns Note: System clock is fs, or input clock to prescaler is divisor clock of fs. *) The rising edge is used in SCLK Rising mode. The falling edge is used SCLK Falling mode. SCLK Output mode Parameter SCLK Cycle (Programmable) Output Data Hold SCLK Rising Edge Hold SCLK Rising Edge Effective Data Input Input SCLK Rising Edge SCLK Rising Edge Symbol tSCY tOSS Variable Min 16x tSCY/2 5x 50 2x 80 0 tSCY 2x 150 32.768 kHz Min 488 s 427 s 60 s 0 Note ) 13.5 MHz Min 1.18 886 68 0 Unit s ns ns ns Max 8192x Max 250 ms Max 655.4 Output Data tOHS Data tHSR tSRD 428 s 886 ns Note: System clock is fs, or input clock to prescaler is divisor clock of fs. tSCY SCLK SCLK Output mode (only rising edge is used) or SCLK Input mode (SCLK Falling SCLK SCLK Input mode (SCLK Falling Edge mode) OUTPUT DATA TxD INPUT DATA RxD tOSS 0 tOHS 1 tSRD 0 VALID 1 VALID tHSR 2 VALID 3 VALID 2 3 91CU10-189 2003-03-31 TMP91CU10 4.6 Event Counter (TI0, TI4, TI8, TI9, TIA,TIB) Parameter Clock Cycle Low Level Clock Pulse Width High Level Clock Pulse Width Symbol tVCK tVCKL tVCKH Variable Min 8X + 100 4X + 40 4X + 40 13.5 MHz Min 692 336 336 Max Max Unit ns ns ns 4.7 Interrupt and Capture (1) NMI , INT0 interrupts Parameter NMI , INT0 to 4 Low Level Pulse Symbol tINTAL tINTAH Variable Min 4X 4X 13.5 MHz Min 296 296 Max Max Unit ns ns Width NMI , INT0 High Level Pulse Width (2) INT5 to 8 interrupts, capture The INT4 to 7 input pulse width depends on the CPU operation clock and timer (9-bit prescaler). The following shows the pulse width for each clock. System clock selected tINTBL (INT5 to 8 low level pulse Prescaler clock selected width) 00 (fFPH) 8X + 100 8XT + 0.1 128X + 0.1 tINTBH (INT5 to 8 high level pulse width) Variable Min 8X + 100 8XT + 0.1 128X + 0.1 Unit 13.5 MHz Min 692 244.3 9.572 ns Min 692 244.3 9.572 0(fc) 01 (fs) 10 (fc/16) 00 (fFPH) 01 (fs) s 1 (fs) (Note 2) 8XT + 0.1 244.3 8XT + 0.1 244.3 Note 1: XT represents the frequency of the low frequency clock fs. Calculated at fs = 32.768 kHz. Note 2: When using fs as the system clock, fc/16 cannot be selected as the prescaler clock. tSCH SCOUT tSCL 91CU10-190 2003-03-31 TMP91CU10 4.8 Timing Chart for Bus Request / Bus Acknowledge (Note1) CLK tBRC tCBAL tBRC tCBAH BUSRQ BUSAK tBAA AD0 to AD15,A0 to A23, CS0 to CS2 ,R/ W tABA (Note2) (Note2) RD , WR , HWR ALE Parameter BUSRQ BUSRQ Set up Time to Symbol tBRC tCBAL tCBAH tABA tBAA Variable Min 120 1.5x + 120 0.5x + 40 0 0 80 80 0 0 13.5 MHz Min 120 231 77 80 80 Max Max Unit ns ns ns ns ns CLK CLK CLK BUSAK BUSAK Falling Edge BUSAK Rising Edge Output Buffer off to BUSAK BUSAK to Output Buffer on Note 1: Even if the BUSRQ signal goes low, the bus will not be released while the WAIT signal is low. The bus will only be released when BUSRQ goes low while WAIT is high. Note 2: This line shows only that the output buffer is in the off state.It does not indicate that the signal level is fixed. Just after the bus is released, the signal level set before the bus was released is maintained dynamically by the external capacitance. Therefore, to fix the signal level using an external resistor during bus release, careful design is necessary as fixing of the level is delayed. The internal programmable pull-up/pull-down resistor is switched between the active and non-active states by the internal signal. 91CU10-191 2003-03-31 |
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