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SEMICONDUCTOR ADVANCE INFORMATION
MOTOROLA
Order this document by: DSP56366/D
Rev 1.3 12/01
Advance Information
DSP56366
24-Bit Audio Digital Signal Processor
The DSP56366 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56366 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Motorola SymphonyTM DSP family, as shown in Figure 1. This design provides a two-fold performance increase over Motorola's popular Symphony family of DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct memory access (DMA). The DSP56366 offers 120 million instructions per second (MIPS) using an internal 120 MHz clock at 3.3 V.
1 2 16 8 4 6 5
MEMORY EXPANSION AREA
TRIPLE TIMER DAX (SPDIF Tx.) INTERFACE HOST INTERFACE ESAI INTERFACE ESAI_1 SHI INTERFACE PROGRAM RAM /INSTR. CACHE 3K x 24 PROGRAM ROM 40K x 24 Bootstrap ROM X MEMORY RAM 13K X 24 ROM 32K x 24 Y MEMORY RAM 7K X 24 ROM 8K x 24
PIO_EB
PM_EB
ADDRESS GENERATION UNIT SIX CHANNELS DMA UNIT
YAB XAB PAB DAB
XM_EB
YM_EB
PERIPHERAL EXPANSION AREA
EXTERNAL ADDRESS BUS SWITCH DRAM & SRAM BUS INTERFACE & I - CACHE EXTERNAL DATA BUS SWITCH
18 ADDRESS 10 CONTROL
24-BIT DSP56300 Core
DDB YDB
INTERNAL DATA BUS
XDB PDB GDB
24 DATA
PLL CLOCK GENERATOR
PROGRAM INTERRUPT CONTROLLER PROGRAM DECODE CONTROLLE PROGRAM ADDRESS GENERATOR
POWER MNGMNT
DATA ALU 24X24+56->56-BIT MAC TWO 56-BIT ACCUMULATORS BARREL SHIFTER JTAG OnCETM
4
EXTAL RESET PINIT/NMI
MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD
24 BITS BUS
Figure 1 DSP56366 Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Advance Infomation
(c) 2000, 2001 MOTOROLA, INC.
TABLE OF CONTENTS SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5 APPENDIX A APPENDIX B INDEX SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 POWER CONSUMPTION BENCHMARK . . . . . . . . . . . . . . . . . . . . . . . . A-1 IBIS MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1 FOR TECHNICAL ASSISTANCE:
Telephone: Email: Internet:
1-800-521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR "asserted" "deasserted" Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN
Note:
Logic State True False True False
Signal State Asserted Deasserted Asserted Deasserted
Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
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DSP56366 Advance Information
MOTOROLA
DSP56366 Features
FEATURES
DSP56300 Modular Chassis
* * * * * * * * * * 120 Million Instructions Per Second (MIPS) with an 120 MHz clock at 3.3V. Object Code Compatible with the 56K core. Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support. Program Control with position independent code support and instruction cache support. Six-channel DMA controller. PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors (1 to 16) and power saving clock divider (2i: i=0 to 7). Reduces clock noise. Internal address tracing support and OnCE for Hardware/Software debugging. JTAG port. Very low-power CMOS design, fully static design with operating frequencies down to DC. STOP and WAIT low-power standby modes.
On-chip Memory Configuration
* * * * * 7Kx24 Bit Y-Data RAM and 8Kx24 Bit Y-Data ROM. 13Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM. 40Kx24 Bit Program ROM. 3Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM. 1K of Program RAM may be used as Instruction Cache or for Program ROM patching. 2Kx24 Bit from Y Data RAM and 5Kx24 Bit from X Data RAM can be switched to Program RAM resulting in up to 10Kx24 Bit of Program RAM.
Off-chip Memory Expansion
* * * * External Memory Expansion Port. Off-chip expansion up to two 16M x 24-bit word of Data memory. Off-chip expansion up to 16M x 24-bit word of Program memory. Simultaneous glueless interface to SRAM and DRAM.
Advance Information MOTOROLA DSP56366 iii
DSP56366 Features
Peripheral Modules
* * Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony, AC97, network and other programmable protocols. Serial Audio Interface I(ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony, AC97, network and other programmable protocols The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT support HCKR and HCKT (high frequency clocks) Serial Host Interface (SHI): SPI and I2C protocols, multi master capability, 10-word receive FIFO, support for 8, 16 and 24-bit words. Byte-wide parallel Host Interface (HDI08) with DMA support. Triple Timer module (TEC). Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF, IEC958, CP340 and AES/EBU digital audio formats. Pins of unused peripherals (except SHI) may be programmed as GPIO lines.
* * * * *
144-pin plastic TQFP package.
Documentation
Table 1 lists the documents that provide a complete description of the DSP56366 and are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information). Table 1
Document Name DSP56300 Family Manual
DSP56366 Documentation
Description Order Number DSP56300FM/AD
Detailed description of the 56000-family architecture and the 24-bit core processor and instruction set Detailed description of memory, peripherals, and interfaces Electrical and timing specifications; pin and package descriptions Brief description of the chip
DSP56366 User's Manual DSP56366 Technical Data Sheet DSP56366 Product Brief
DSP56366UM/D DSP56366/D DSP56366P/D
Advance Information iv DSP56366 MOTOROLA
SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
The input and output signals of the DSP56366 are organized into functional groups, which are listed in Table 1-1 and illustrated in Figure 1-1. The DSP56366 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs. Table 1-1 DSP56366 Functional Signal Groupings
Functional Group Power (VCC) Ground (GND) Clock and PLL Address bus Data bus Bus control Interrupt and mode control HDI08 SHI ESAI ESAI_1 Digital audio transmitter (DAX) Timer JTAG/OnCE Port Port C3 Port E5 Port D4 Port B2 Port A1 Number of Signals 20 18 3 18 24 10 5 16 5 12 6 2 1 4 Detailed Description Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 1-6 Table 1-7 Table 1-8 Table 1-9 Table 1-10 Table 1-11 Table 1-12 Table 1-13 Table 1-14 Table 1-15
MOTOROLA
DSP56366 Advance Information
1-1
Signal/Connection Descriptions Signal Groupings
Table 1-1 DSP56366 Functional Signal Groupings (Continued)
Functional Group Notes: 1. 2. 3. 4. 5. Number of Signals Detailed Description
Port A is the external memory interface port, including the external address bus, data bus, and control signals. Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals. Port C signals are the GPIO port signals which are multiplexed with the ESAI signals. Port D signals are the GPIO port signals which are multiplexed with the DAX signals. Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.
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Signal/Connection Descriptions Signal Groupings
PORT A ADDRESS BUS
A0-A17 VCCA (3) GNDA (4)
DSP56366
OnCE ON-CHIP EMULATION/ JTAG PORT TDI
TCK TDO TMS
PORT A DATA BUS
D0-D23 VCCD (4) GNDD (4)
PARALLEL HOST PORT (HDI08) Port B
HAD(7:0) [PB0-PB7] HAS/HA0 [PB8] HA8/HA1 [PB9] HA9/HA2 [PB10] HRW/HRD [PB11] HDS/HWR [PB12] HCS/HA10 [PB13] HOREQ/HTRQ [PB14] HACK/HRRQ [PB15] VCCH GNDH
PORT A BUS CONTROL
AA0-AA2/RAS0-RAS2 CAS RD WR TA BR BG BB VCCC (2) GNDC (2)
SERIAL AUDIO INTERFACE (ESAI)
SCKT[PC3]
Port C
FST [PC4] HCKT [PC5] SCKR [PC0] FSR [PC1] HCKR [PC2] SDO0[PC11] / SDO0_1[PE11] SDO1[PC10] / SDO1_1[PE10] SDO2/SDI3[PC9] / SDO2_1/SDI3_1[PE9] SDO3/SDI2[PC8] / SDO3_1/SDI2_1[PE8] SDO4/SDI1 [PC7] SDO5/SDI0 [PC6]
INTERRUPT AND MODE CONTROL
MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET
PLL AND CLOCK
EXTAL PINIT/NMI PCAP VCCP GNDP
SERIAL AUDIO INTERFACE(ESAI_1)
SCKT_1[PE3]
Port E
FS T_1[PE4] SCKR_1[PE0] FSR_1[PE1] SDO4_1/SDI1_1[PE7] SDO5_1/SDI0_1[PE6] VCCS (2) GNDS (2)
QUIET POWER
VCCQH (3) VCCQL (4) GNDQ (4)
SPDIF TRANSMITTER (DAX)
ADO [PD1] ACI [PD0]
Port D
SERIAL HOST INTERFACE (SHI)
MOSI/HA0 SS/HA2 MISO/SDA SCK/SCL HREQ
TIMER 0
TIO0 [TIO0]
Figure 1-1 Signals Identified by Functional Group
MOTOROLA
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1-3
Signal/Connection Descriptions Power
POWER
Table 1-2 Power Inputs
Power Name VCCP Description PLL Power--VCCP is VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. There is one VCCP input. Quiet Core (Low) Power--VCCQL is an isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCQL inputs. Quiet External (High) Power--VCCQH is a quiet power source for I/O lines. This input must be tied externally to all other chip power inputs. The user must provide adequate decoupling capacitors. There are three VCCQH inputs. Address Bus Power--VCCA is an isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are three VCCA inputs. Data Bus Power--VCCD is an isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCD inputs. Bus Control Power--VCCC is an isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are two VCCC inputs. Host Power--VCCH is an isolated power for the HDI08 I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There is one VCCH input. SHI, ESAI, ESAI_1, DAX and Timer Power --VCCS is an isolated power for the SHI, ESAI, ESAI_1, DAX and Timer. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are two VCCS inputs.
VCCQL (4)
VCCQH (3)
VCCA (3)
VCCD (4)
VCCC (2)
VCCH
VCCS (2)
GROUND
Table 1-3 Grounds
Ground Name Description PLL Ground--GNDP is a ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 F capacitor located as close as possible to the chip package. There is one GNDP connection.
GNDP
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Signal/Connection Descriptions Clock and PLL
Table 1-3 Grounds
Ground Name Description Quiet Ground--GNDQ is an isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDQ connections. Address Bus Ground--GNDA is an isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDA connections. Data Bus Ground--GNDD is an isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDD connections. Bus Control Ground--GNDC is an isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GNDC connections. Host Ground--GNDh is an isolated ground for the HD08 I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There is one GNDH connection. SHI, ESAI, ESAI_1, DAX and Timer Ground--GNDS is an isolated ground for the SHI, ESAI, ESAI_1, DAX and Timer. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GNDS connections.
GNDQ (4)
GNDA (4)
GNDD (4)
GNDC (2)
GNDH
GNDS (2)
CLOCK AND PLL
Table 1-4 Clock and PLL Signals
Signal Name Type State during Reset Signal Description
EXTAL
Input
Input
External Clock Input--An external clock source must be connected to EXTAL in order to supply the clock to the internal clock generator and PLL. This input cannot tolerate 5 V. PLL Capacitor--PCAP is an input connecting an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP may be tied to VCC, GND, or left floating. PLL Initial/Nonmaskable Interrupt--During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET de assertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized to internal system clock. This input cannot tolerate 5 V.
PCAP
Input
Input
PINIT/NMI
Input
Input
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1-5
Signal/Connection Descriptions External Memory Expansion Port (Port A)
EXTERNAL MEMORY EXPANSION PORT (PORT A)
When the DSP56366 enters a low-power standby mode (stop or wait), it releases bus mastership and tristates the relevant port A signals: A0-A17, D0-D23, AA0/RAS0-AA2/RAS2, RD, WR, BB, CAS.
External Address Bus
Table 1-5 External Address Bus Signals
Signal Name Type State during Reset Signal Description
A0-A17
Outpu t
Tri-stated
Address Bus--When the DSP is the bus master, A0-A17 are active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A0-A17 do not change state when external memory spaces are not being accessed.
External Data Bus
Table 1-6 External Data Bus Signals
Signal Name Type State during Reset Signal Description Data Bus--When the DSP is the bus master, D0-D23 are activehigh, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D0-D23 are tri-stated.
D0-D23
Input/Output
Tri-stated
External Bus Control
Table 1-7 External Bus Control Signals
Signal Name Type State during Reset Signal Description
AA0-AA2/ RAS0- RAS2
Outpu t
Tri-stated
Address Attribute or Row Address Strobe--When defined as AA, these signals can be used as chip selects or additional address lines. When defined as RAS, these signals can be used as RAS for DRAM interface. These signals are tri-statable outputs with programmable polarity.
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MOTOROLA
Signal/Connection Descriptions External Memory Expansion Port (Port A)
Table 1-7 External Bus Control Signals (Continued)
Signal Name Type State during Reset Signal Description
CAS
Outpu t
Tri-stated
Column Address Strobe-- When the DSP is the bus master, CAS is an active-low output used by DRAM to strobe the column address. Otherwise, if the bus mastership enable (BME) bit in the DRAM control register is cleared, the signal is tri-stated. Read Enable--When the DSP is the bus master, RD is an active-low output that is asserted to read external memory on the data bus (D0-D23). Otherwise, RD is tristated. Write Enable--When the DSP is the bus master, WR is an active-low output that is asserted to write external memory on the data bus (D0-D23). Otherwise, WR is tristated. Transfer Acknowledge--If the DSP is the bus master and there is no external bus activity, or the DSP is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be added to the wait states inserted by the BCR by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to the internal system clock. The number of wait states is determined by the TA input or by the bus control register (BCR), whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles. In order to use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access cannot be extended by TA deassertion, otherwise improper operation may result. TA can operate synchronously or asynchronously, depending on the setting of the TAS bit in the operating mode register (OMR). TA functionality may not be used while performing DRAM type accesses, otherwise improper operation may result. Bus Request--BR is an active-low output, never tri-stated. BR is asserted when the DSP requests bus mastership. BR is deasserted when the DSP no longer needs the bus. BR may be asserted or deasserted independent of whether the DSP56366 is a bus master or a bus slave. Bus "parking" allows BR to be deasserted even though the DSP56366 is the bus master. (See the description of bus "parking" in the BB signal description.) The bus request hold (BRH) bit in the BCR allows BR to be asserted under software control even though the DSP does not need the bus. BR is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. BR is only affected by DSP requests for the external bus, never for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset to the bus slave state.
RD
Outpu t
Tri-stated
WR
Outpu t
Tri-stated
TA
Input
Ignored Input
BR
Outpu t
Output (deasserted )
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1-7
Signal/Connection Descriptions Interrupt and Mode Control
Table 1-7 External Bus Control Signals (Continued)
Signal Name Type State during Reset Signal Description
BG
Input
Ignored Input
Bus Grant--BG is an active-low input. BG is asserted by an external bus arbitration circuit when the DSP56366 becomes the next bus master. When BG is asserted, the DSP56366 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution. For proper BG operation, the asynchronous bus arbitration enable bit (ABE) in the OMR register must be set. Bus Busy--BB is a bidirectional active-low input/output. BB indicates that the bus is active. Only after BB is deasserted can the pending bus master become the bus master (and then assert the signal again). The bus master may keep BB asserted after ceasing bus activity regardless of whether BR is asserted or deasserted. This is called "bus parking" and allows the current bus master to reuse the bus without rearbitration until another device requires the bus. The deassertion of BB is done by an "active pull-up" method (i.e., BB is driven high and then released and held high by an external pull-up resistor). For proper BB operation, the asynchronous bus arbitration enable bit (ABE) in the OMR register must be set. BB requires an external pull-up resistor.
BB
Input/ Outpu t
Input
INTERRUPT AND MODE CONTROL
The interrupt and mode control signals select the chip's operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines.
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Signal/Connection Descriptions Interrupt and Mode Control
Table 1-8 Interrupt and Mode Control
Signal Name Type State during Reset Signal Description
MODA/IRQA
Input
Input
Mode Select A/External Interrupt Request A--MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. If the processor is in the stop standby state and the MODA/IRQA pin is pulled to GND, the processor will exit the stop state. This input is 5 V tolerant. Mode Select B/External Interrupt Request B--MODB/IRQB is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. This input is 5 V tolerant. Mode Select C/External Interrupt Request C--MODC/IRQC is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. This input is 5 V tolerant. Mode Select D/External Interrupt Request D--MODD/IRQD is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. This input is 5 V tolerant. Reset--RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET is being asserted. This input is 5 V tolerant.
MODB/IRQB
Input
Input
MODC/IRQC
Input
Input
MODD/IRQD
Input
Input
RESET
Input
Input
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1-9
Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08)
PARALLEL HOST INTERFACE (HDI08)
The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The HDI08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware.
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Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08)
Table 1-9 Host Interface
Signal Name Type State during Reset Signal Description Host Data--When HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, these signals are lines 0-7 of the bidirectional, tri-state data bus. Host Address/Data--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, these signals are lines 0-7 of the address/data bidirectional, multiplexed, tri-state bus. GPIO disconnected Port B 0-7--When the HDI08 is configured as GPIO, these signals are individually programmable as input, output, or internally disconnected. The default state after reset for these signals is GPIO disconnected. These inputs are 5 V tolerant. Host Address Input 0--When the HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 0 of the host address input bus. Host Address Strobe--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is the host address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is programmable, but is configured active-low (HAS) following reset. Port B 8--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant. Host Address Input 1--When the HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 1 of the host address (HA1) input bus. Host Address 8--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 8 of the host address (HA8) input bus.
H0-H7
Input/ output
HAD0-HAD7
Input/ output Input, output, or disconnected
PB0-PB7
HA0
Input
HAS/HAS
Input GPIO disconnected
PB8
Input, output, or disconnected
HA1
Input
HA8
Input GPIO disconnected
PB9
Input, output, or disconnected
Port B 9--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant.
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1-11
Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08)
Table 1-9 Host Interface (Continued)
Signal Name Type State during Reset Signal Description Host Address Input 2--When the HDI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line 2 of the host address (HA2) input bus. Host Address 9--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 9 of the host address (HA9) input bus. Port B 10--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant. Host Read/Write--When HDI08 is programmed to interface a singledata-strobe host bus and the HI function is selected, this signal is the Host Read/Write (HRW) input. Host Read Data--When HDI08 is programmed to interface a doubledata-strobe host bus and the HI function is selected, this signal is the host read data strobe (HRD) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HRD) after reset. Port B 11--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant. Host Data Strobe--When HDI08 is programmed to interface a singledata-strobe host bus and the HI function is selected, this signal is the host data strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HDS) following reset. Host Write Data--When HDI08 is programmed to interface a doubledata-strobe host bus and the HI function is selected, this signal is the host write data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HWR) following reset. Port B 12--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant.
HA2
Input
HA9
Input GPIO disconnected
PB10
Input, Output, or Disconnected
HRW
Input
HRD/ HRD
Input GPIO disconnected Input, Output, or Disconnected
PB11
HDS/ HDS
Input
HWR/ HWR
Input
GPIO disconnected
PB12
Input, output, or disconnected
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Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08)
Table 1-9 Host Interface (Continued)
Signal Name Type State during Reset Signal Description Host Chip Select--When HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is the host chip select (HCS) input. The polarity of the chip select is programmable, but is configured active-low (HCS) after reset. Host Address 10--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 10 of the host address (HA10) input bus. Port B 13--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant. Host Request--When HDI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host request (HOREQ) output. The polarity of the host request is programmable, but is configured as active-low (HOREQ) following reset. The host request may be programmed as a driven or open-drain output. Transmit Host Request--When HDI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the transmit host request (HTRQ) output. The polarity of the host request is programmable, but is configured as active-low (HTRQ) following reset. The host request may be programmed as a driven or open-drain output. Port B 14--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant.
HCS
Input
HA10
Input
GPIO disconnected
PB13
Input, output, or disconnected
HOREQ/ HOREQ
Output
HTRQ/ HTRQ
Output
GPIO disconnected
PB14
Input, output, or disconnected
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Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08)
Table 1-9 Host Interface (Continued)
Signal Name Type State during Reset Signal Description Host Acknowledge--When HDI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host acknowledge (HACK) Schmitt-trigger input. The polarity of the host acknowledge is programmable, but is configured as active-low (HACK) after reset. Receive Host Request--When HDI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the receive host request (HRRQ) output. The polarity of the host request is programmable, but is configured as active-low (HRRQ) after reset. The host request may be programmed as a driven or open-drain output. Port B 15--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.
HACK/ HACK
Input
HRRQ/ HRRQ
Output GPIO disconnected Input, output, or disconnected
PB15
The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant.
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Signal/Connection Descriptions Serial Host Interface
SERIAL HOST INTERFACE
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode. Table 1-10 Serial Host Interface Signals
Signal Name Signal Type State during Reset Signal Description
SCK
Input or output
Tristated SCL Input or output
SPI Serial Clock--The SCK signal is an output when the SPI is configured as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol. I2C Serial Clock--SCL carries the clock for I2C bus transactions in the I2C mode. SCL is a Schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. SCL should be connected to VCC through a pull-up resistor. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. SPI Master-In-Slave-Out--When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted. An external pull-up resistor is not required for SPI operation. I2C Data and Acknowledge--In I2C mode, SDA is a Schmitt-trigger input when receiving and an open-drain output when transmitting. SDA should be connected to VCC through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events. A high-to-low transition of the SDA line while SCL is high is a unique situation, and is defined as the start event. A low-to-high transition of SDA while SCL is high is a unique situation defined as the stop event. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant.
MISO
Input or output
SDA
Input or open-drain output
Tristated
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Signal/Connection Descriptions Serial Host Interface
Table 1-10 Serial Host Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description
MOSI
Input or output
SPI Master-Out-Slave-In--When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. Tristated I2C Slave Address 0--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for I2C slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when configured for the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. SPI Slave Select--This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI master mode, this signal should be kept deasserted (pulled high). If it is asserted while configured as SPI master, a bus error condition is flagged. If SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state. Tristated I2C Slave Address 2--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for the I2C Slave mode, the HA2 signal is used to form the slave device address. HA2 is ignored in the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. Host Request--This signal is an active low Schmitt-trigger input when configured for the master mode but an active low output when configured for the slave mode. When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. When configured for the master mode, HREQ is an input. When asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer. This signal is tri-stated during hardware, software, personal reset, or when the HREQ1-HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in this state. This input is 5 V tolerant.
HA0
Input
SS
Input
HA2
Input
HREQ
Input or Output
Tristated
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Signal/Connection Descriptions Enhanced Serial Audio Interface
ENHANCED SERIAL AUDIO INTERFACE
Table 1-11 Enhanced Serial Audio Interface Signals
Signal Name Signal Type State during Reset Signal Description High Frequency Clock for Receiver--When programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock. Port C 2--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. High Frequency Clock for Transmitter--When programmed as an input, this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock. Port C 5--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Frame Sync for Receiver--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). FSR Input or output GPIO disconnected When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. Port C 1--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
HCKR
Input or output GPIO disconnected
PC2
Input, output, or disconnected
HCKT
Input or output GPIO disconnected
PC5
Input, output, or disconnected
PC1
Input, output, or disconnected
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Signal/Connection Descriptions Enhanced Serial Audio Interface
Table 1-11 Enhanced Serial Audio Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description Frame Sync for Transmitter--This is the transmitter frame sync input/ output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). Port C 4--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Receiver Serial Clock--SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. Port C 0--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Transmitter Serial Clock--This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. GPIO disconnected Port C 3--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
FST
Input or output GPIO disconnected
PC4
Input, output, or disconnected
SCKR
Input or output GPIO disconnected
PC0
Input, output, or disconnected
SCKT
Input or output
PC3
Input, output, or disconnected
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Signal/Connection Descriptions Enhanced Serial Audio Interface
Table 1-11 Enhanced Serial Audio Interface Signals (Continued)
Signal Name SDO5 SDI0 PC6 Signal Type Output Input Input, output, or disconnected GPIO disconnected State during Reset Signal Description Serial Data Output 5--When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0--When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register. Port C 6--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO4 SDI1 PC7 Output Input Input, output, or disconnected GPIO disconnected Serial Data Output 4--When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1--When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. Port C 7--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO3/ SDO3_1 Serial Data Output 3--When programmed as a transmitter, SDO3 is used to transmit data from the TX3 serial transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 3. Serial Data Input 2--When programmed as a receiver, SDI2 is used to receive serial data into the RX2 serial receive shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input 2. Port C 8--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 8 signal. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
Output
SDI2/ SDI2_1
Input GPIO disconnected Input, output, or disconnected
PC8/PE8
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Signal/Connection Descriptions Enhanced Serial Audio Interface
Table 1-11 Enhanced Serial Audio Interface Signals (Continued)
Signal Name SDO2/ SDO2_1 Signal Type State during Reset Signal Description Serial Data Output 2--When programmed as a transmitter, SDO2 is used to transmit data from the TX2 serial transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 2. Serial Data Input 3--When programmed as a receiver, SDI3 is used to receive serial data into the RX3 serial receive shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input 3. Port C 9--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 9 signal. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO1/ SDO1_1 Serial Data Output 1--SDO1 is used to transmit data from the TX1 serial transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 1. GPIO disconnected Port C 10--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 10 signal. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO0/ SDO0_1 Serial Data Output 0--SDO0 is used to transmit data from the TX0 serial transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 0. GPIO disconnected Port C 11--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 11 signal. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
Output
SDI3/ SDI3_1
Input GPIO disconnected Input, output, or disconnected
PC9/PE9
Output
PC10/ PE10
Input, output, or disconnected
Output
PC11/ PE11
Input, output, or disconnected
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Signal/Connection Descriptions Enhanced Serial Audio Interface_1
ENHANCED SERIAL AUDIO INTERFACE_1
Table 1-12 Enhanced Serial Audio Interface_1 Signals
Signal Name Signal Type State during Reset Signal Description Frame Sync for Receiver_1--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). FSR_1 Input or output GPIO disconnected When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. Port E 1--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 5 V. Frame Sync for Transmitter_1--This is the transmitter frame sync input/ output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). Port E 4--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 5 V.
PE1
Input, output, or disconnected
FST_1
Input or output GPIO disconnected
PE4
Input, output, or disconnected
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Signal/Connection Descriptions Enhanced Serial Audio Interface_1
Table 1-12 Enhanced Serial Audio Interface_1 Signals
Signal Name Signal Type State during Reset Signal Description Receiver Serial Clock_1--SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. Port E 0--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 5 V. Transmitter Serial Clock_1--This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. GPIO disconnected Port E 3--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 5 V. SDO5_1 SDI0_1 PE6 Output Input Input, output, or disconnected GPIO disconnected Serial Data Output 5_1--When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0_1--When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register. Port E 6--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 5 V.
SCKR_1
Input or output GPIO disconnected
PE0
Input, output, or disconnected
SCKT_1
Input or output
PE3
Input, output, or disconnected
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Signal/Connection Descriptions spdif tRANSMITTER Digital Audio Interface
Table 1-12 Enhanced Serial Audio Interface_1 Signals
Signal Name SDO4_1 SDI1_1 PE7 Signal Type Output Input Input, output, or disconnected GPIO disconnected State during Reset Signal Description Serial Data Output 4_1--When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1_1--When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. Port E 7--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
SPDIF TRANSMITTER DIGITAL AUDIO INTERFACE
Table 1-13 Digital Audio Interface (DAX) Signals
Signal Name Type State During Reset Signal Description Audio Clock Input--This is the DAX clock input. When programmed to use an external clock, this input supplies the DAX clock. The external clock frequency must be 256, 384, or 512 times the audio sampling frequency (256 x Fs, 384 x Fs or 512 x Fs, respectively). GPIO Disconnected Port D 0--When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. ADO Output Input, output, or disconnected Digital Audio Data Output--This signal is an audio and non-audio output in the form of AES/EBU, CP340 and IEC958 data in a biphase mark format. Port D 1--When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant.
ACI
Input
PD0
Input, output, or disconnected
PD1
GPIO Disconnected
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Signal/Connection Descriptions Timer
TIMER
Table 1-14 Timer Signal
Signal Name Type State during Reset Signal Description Timer 0 Schmitt-Trigger Input/Output--When timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 0 control/status register (TCSR0). If TIO0 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected to Vcc through a pull-up resistor in order to ensure a stable logic level at this input. This input is 5 V tolerant.
TIO0
Input or Output
Input
JTAG/OnCE INTERFACE
Table 1-15 JTAG/OnCE Interface
Signal Name Signal Type State during Reset Signal Description
TCK
Input
Input
Test Clock--TCK is a test clock input signal used to synchronize the JTAG test logic. It has an internal pull-up resistor. This input is 5 V tolerant. Test Data Input--TDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 5 V tolerant. Test Data Output--TDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. Test Mode Select--TMS is an input signal used to sequence the test controller's state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 5 V tolerant.
TDI
Input
Input
TDO
Output
Tri-stated
TMS
Input
Input
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Signal/Connection Descriptions
MOTOROLA
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Signal/Connection Descriptions
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SECTION 2 SPECIFICATIONS
INTRODUCTION
The DSP56366 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs and outputs. The DSP56366 specifications are preliminary and are from design simulations, and may not be fully tested or guaranteed. Finalized specifications will be published after full characterization and device qualifications are complete.
MAXIMUM RATINGS CAUTION
This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either GND or VCC). The suggested value for a pullup or pulldown resistor is 10 k.
Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist.
MOTOROLA
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Specifications Thermal Characteristics
Table 2-1 Maximum Ratings
Rating1 Supply Voltage All input voltages excluding "5 V tolerant" inputs3 All "5 V tolerant" input voltages3 Current drain per pin excluding VCC and GND Operating temperature range Storage temperature Notes: 1. 2. 3. Symbol VCC VIN VIN5 I TJ Ta TSTG Value1, 2 Unit V V V mA
-0.3 to +4.0
GND -0.3 to VCC + 0.3 GND - 0.3 to VCC + 3.95 10
-40 to +105 -40 to +85 -55 to +125
C C
GND = 0 V, VCC = 3.3 V 0.16 V, TJ = -40C to +105C, CL = 50 pF Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. CAUTION: All "5 V Tolerant" input voltages must not be more than 3.95 V greater than the supply voltage; this restriction applies to "power on", as well as during normal operation. In any case, the input voltages cannot be more than 5.75 V. "5 V Tolerant" inputs are inputs that tolerate 5 V.
THERMAL CHARACTERISTICS
Table 2-2 Thermal Characteristics
Characteristic Junction-to-ambient thermal resistance1, 2 Natural Convection Junction-to-case thermal resistance3 Thermal characterization parameter4 Natural Convection Notes: 1. Symbol RJA or JA RJC or JC JT TQFP Value 37 7 2.0 Unit
C/W C/W C/W
2. 3. 4.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
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Specifications DC Electrical Characteristics
DC ELECTRICAL CHARACTERISTICS
Table 2-3 DC Electrical Characteristics6
Characteristics Supply voltage Input high voltage Symbol VCC Min 3.14 Typ 3.3 Max 3.46 Unit V
* D(0:23), BG, BB, TA, ESAI_1(except * RESET, PINIT/NMI and all JTAG/ESAI/Timer/HDI08/DAX/ ESAI_1(only SDO4_1)/SHI(SPI mode)
SDO4_1) MOD1/IRQ1,
VIH
2.0
--
VCC V
VIHP VIHP VIHX VIL
2.0 1.5 0.8 x VCC
-- -- --
VCC + 3.95 VCC + 3.95 VCC
* SHI(I2C mode) * EXTAL8
Input low voltage
* D(0:23), BG, BB, TA, ESAI_1(except * MOD /IRQ1, RESET, PINIT/NMI and all JTAG/ESAI/Timer/HDI08/DAX/ ESAI_1(only SDO4_1)/SHI(SPI mode) * SHI(I2C mode) * EXTAL
8 SDO4_1) 1
-0.3
--
0.8
VILP VILP VILX IIN ITSI
-0.3 -0.3 -0.3 -10 -10
-- -- -- -- --
0.8 0.3 x VCC 0.2 x VCC 10 10
V
Input leakage current High impedance (off-state) input current (@ 2.4 V / 0.4 V) Output high voltage
A A
* TTL (IOH = -0.4 mA)5,7 A)5
VOH
2.4 VCC - 0.01
-- --
-- --
V V
* CMOS (IOH = -10
Output low voltage
* TTL (IOL = 3.0 mA, open-drain pins IOL = 6.7 mA)5,7 * CMOS (IOL = 10 A)5
Internal supply current2 at internal clock of 120MHz
VOL
-- --
-- --
0.4 0.01
V
* In Normal mode * In Wait mode * In Stop mode4
PLL supply current Input capacitance5
ICCI ICCW ICCS
-- -- -- --
116 7.3 1 1 --
200 25 10 2.5 10
mA mA mA mA pF
CIN
--
MOTOROLA
DSP56366 Advance Information
2-3
Specifications DC Electrical Characteristics
Table 2-3 DC Electrical Characteristics6 (Continued)
Characteristics Notes: 1. 2. Symbol Min Typ Max Unit
3. 4. 5. 6. 7. 8.
Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC,and MODD/IRQD pins Power Consumption Considerations on page 4-4 provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCC = 3.3 V at TJ = 105C. Maximum internal supply current is measured with VCC = 3.46 V at TJ = 105C. Deleted. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float). Periodically sampled and not 100% tested VCC = 3.3 V .16 V; TJ = - 40C to +105C, CL = 50 pF This characteristic does not apply to PCAP. Driving EXTAL to the low VIHX or the high VILX value may cause additional power consumption (DC current). To minimize power consumption, the minimum VIHX should be no lower than 0.9 x VCC and the maximum VILX should be no higher than 0.1 x VCC.
2-4
DSP56366 Advance Information
MOTOROLA
Specifications AC Electrical Characteristics
AC ELECTRICAL CHARACTERISTICS
The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.3 V and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 8 of the previous table. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal's transition. DSP56366 output levels are measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively. Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15 MHz and rated speed.
MOTOROLA
DSP56366 Advance Information
2-5
Specifications Internal Clocks
INTERNAL CLOCKS
Table 2-4 Internal Clocks
Characteristics Internal operation frequency with PLL enabled Internal operation frequency with PLL disabled Internal clock high period * With PLL disabled * With PLL enabled and MF 4 * With PLL enabled and MF > 4 Internal clock low period * With PLL disabled * With PLL enabled and MF 4 * With PLL enabled and MF > 4 Internal clock cycle time with PLL enabled Internal clock cycle time with PLL disabled Instruction cycle time Notes: 1. DF = Division Factor Ef = External frequency ETC = External clock cycle MF = Multiplication Factor PDF = Predivision Factor TC = internal clock cycle See the PLL and Clock discussion of the PLL. TL -- 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF -- -- -- ETC -- -- ETC x PDF x DF/MF 2 x ETC TC -- 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF -- -- -- TH -- 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF ETC -- -- -- 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF Symbol Min f f -- -- Expression1, 2 Typ (Ef x MF)/ (PDF x DF) Ef/2 Max -- --
TC TC ICYC
2.
Generation section in the DSP56300 Family Manual for a detailed
2-6
DSP56366 Advance Information
MOTOROLA
Specifications EXTERNAL CLOCK OPERATION
EXTERNAL CLOCK OPERATION
The DSP56366 system clock is an externally supplied square wave voltage source connected to EXTAL(Figure 2-1).
VIHC EXTAL VIL ETH 2 4 ETL 3 ETC Midpoint
Note:
The midpoint is 0.5 (VIHC + VILC).
Figure 2-1 External Clock Timing
Table 2-5 Clock Operation
No. 1 Characteristics Frequency of EXTAL (EXTAL Pin Frequency) The rise and fall time of this external clock should be 3 ns maximum. Symbol Ef Min 0 Max 120.0
2
* With PLL disabled (46.7%-53.3% duty cycle6) * With PLL enabled (42.5%-57.5% duty cycle6) * With PLL disabled (46.7%-53.3% duty cycle6) * With PLL enabled (42.5%-57.5% duty cycle6)
EXTAL cycle time
2
EXTAL input high1, 2
ETH
3.89 ns 3.54 ns
157.0 s 157.0 s 273.1 s
EXTAL input
low1, 2
3
ETL
3.89 ns 3.54 ns
4
* With PLL disabled * With PLL enabled * With PLL disabled * With PLL enabled
1. 2. 3. 4. 5. 6. Instruction cycle time = ICYC = TC4
ETC
8.33 ns 8.33 ns
7 Notes:
ICYC
16.66 ns
8.33 ns 8.53 s Measured at 50% of the input transition The maximum value for PLL enabled is given for minimum VCO and maximum MF.
The maximum value for PLL enabled is given for minimum VCO and maximum DF. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met.
MOTOROLA
DSP56366 Advance Information
2-7
Specifications Phase Lock Loop (PLL) Characteristics
PHASE LOCK LOOP (PLL) CHARACTERISTICS
Table 2-6 PLL Characteristics
Characteristics VCO frequency when PLL enabled (MF x Ef x 2/PDF) PLL external capacitor (PCAP pin to VCCP) (CPCAP1) Min 30 Max 240 Unit MHz
* @ MF 4 * @ MF > 4
Notes: 1.
(MF x 580) - 100 MF x 830
(MF x 780) - 140 MF x 1470
pF
CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for CPCAP can be computed from one of the following equations: (MF x 680)-120, for MF 4, or MF x 1100, for MF > 4.
2-8
DSP56366 Advance Information
MOTOROLA
Specifications Reset, Stop, Mode Select, and Interrupt Timing
RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing6
No. 8 Characteristics Delay from RESET assertion to all pins at reset value3 Required RESET duration4 9 Expression -- 50 x ETC 1000 x ETC 2.5 x TC Min -- 416.7 8.3 20.8 Max 26.0 -- -- -- Unit ns ns s ns
* Power on, external clock generator, PLL disabled * Power on, external clock generator, PLL enabled * During normal operation
Delay from asynchronous RESET deassertion to first external address output (internal reset deassertion)5
10
* Minimum * Maximum
13 14 15 16 Mode select setup time Mode select hold time Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory access address out valid
3.25 x TC + 2.0 20.25 TC + 7.50
29.1 -- 30.0 0.0 5.5 5.5
-- 176.2 -- -- -- --
ns ns ns ns ns ns
17
* Caused by first interrupt instruction fetch * Caused by first interrupt instruction execution
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts1 Delay from RD assertion to interrupt request deassertion for level sensitive fast interrupts1 Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts1
4.25 x TC + 2.0 7.25 x TC + 2.0 10 x TC + 5.0
37.4 62.4 88.3
-- -- --
ns ns ns
18
19
3.75 x TC + WS x TC - 10.94 3.25 x TC + WS x TC - 10.94
--
Note 7
ns
20
--
Note 7
ns
* DRAM for all WS
21
(WS + 3.5) x TC - 10.94 (WS + 3.5) x TC - 10.94 (WS + 3) x TC - 10.94 (WS + 2.5) x TC - 10.94
-- -- -- -- 4.9
Note 7 Note 7 Note 7 Note 7 --
ns
* SRAM WS = 1 * SRAM WS = 2, 3 * SRAM WS 4
24 Duration for IRQA assertion to recover from Stop state
MOTOROLA
DSP56366 Advance Information
2-9
Specifications Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing6 (Continued)
No. Characteristics Delay from IRQA assertion to fetch of first instruction (when exiting Stop)2, 3 Expression Min Max Unit
25
* PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) * PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop Delay)
Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)2, 3
PLC x ETC x PDF + (128 K - PLC/2) x TC PLC x ETC x PDF + (23.75 0.5) x TC (8.25 0.5) x TC
--
--
ms
-- 64.6
-- 72.9
ms ns
26
* PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) * PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay)
Interrupt Requests Rate
PLC x ETC x PDF + (128K - PLC/2) x TC PLC x ETC x PDF + (20.5 0.5) x TC 5.5 x TC
--
--
ms
--
--
ms
45.8
--
ns
* HDI08, ESAI, ESAI_1, SHI, DAX, Timer
27
12TC 8TC 8TC 12TC
-- -- -- --
100.0 66.7 66.7 100.0
ns ns ns ns
* DMA * IRQ, NMI (edge trigger) * IRQ (level trigger)
DMA Requests Rate
* Data read from HDI08, ESAI, ESAI_1, SHI, DAX
28
6TC 7TC 2TC 3TC
-- -- --
50.0 58.0 16.7 25.0
ns ns ns
* Data write to HDI08, ESAI, ESAI_1, SHI, DAX * Timer * IRQ, NMI (edge trigger)
2-10
DSP56366 Advance Information
MOTOROLA
Specifications Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing6 (Continued)
No. 29 Notes: Characteristics Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory (DMA source) access address out valid 1. Expression 4.25 x TC + 2.0 Min 37.4 Max -- Unit ns
When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. This timing depends on several settings: For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by the PCTL Bit 17 and OMR Bit 6 settings. For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs: the stop delay counter completes count or PLL lock procedure completion. PLC value for PLL disable is 0. The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 120 MHz it is 4096/120 MHz = 34.1 s). During the stabilization period, TC, TH, and TL will not be constant, and their width may vary, so timing may vary as well.
2.
3. 4.
Periodically sampled and not 100% tested RESET duration is measured during the time in which RESET is asserted, VCC is valid, and the EXTAL input is active and valid. When the VCC is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. If PLL does not lose lock VCC = 3.3 V 0.16 V; TJ = -40C to + 105C, CL = 50 pF WS = number of wait states (measured in clock cycles, number of TC). Use expression to compute maximum value. VIH
5. 6. 7.
RESET 9 8 All Pins Reset Value 10
A0-A17
First Fetch
AA0460
Figure 2-2 Reset Timing
MOTOROLA
DSP56366 Advance Information
2-11
Specifications Reset, Stop, Mode Select, and Interrupt Timing A0-A17
First Interrupt Instruction Execution/Fetch
RD 20 WR 21 IRQA, IRQB, IRQC, IRQD, NMI 17 19
a) First Interrupt Instruction Execution General Purpose I/O 18 IRQA, IRQB, IRQC, IRQD, NMI b) General Purpose I/O
Figure 2-3 External Fast Interrupt Timing
IRQA, IRQB, IRQC, IRQD, NMI 15 IRQA, IRQB, IRQC, IRQD, NMI
16
AA0463
Figure 2-4 External Interrupt Timing (Negative Edge-Triggered)
2-12
DSP56366 Advance Information
MOTOROLA
Specifications Reset, Stop, Mode Select, and Interrupt Timing
RESET
VIH 13 14
MODA, MODB, MODC, MODD, PINIT
VIH VIL
VIH VIL
IRQA, IRQB, IRQD, NMI
AA0465
Figure 2-5 Operating Mode Select Timing
24 IRQA
25 A0-A17 First Instruction Fetch
AA0466
Figure 2-6 Recovery from Stop State Using IRQA
26
IRQA 25 A0-A17
First IRQA Interrupt Instruction Fetch AA0467
Figure 2-7 Recovery from Stop State Using IRQA Interrupt Service
MOTOROLA
DSP56366 Advance Information
2-13
Specifications Reset, Stop, Mode Select, and Interrupt Timing
A0-A17
DMA Source Address
RD
WR 29 First Interrupt Instruction Execution
AA1104
IRQA, IRQB, IRQC, IRQD, NMI
Figure 2-8 External Memory Access (DMA Source) Timing
2-14
DSP56366 Advance Information
MOTOROLA
Specifications External Memory Expansion Port (Port A)
EXTERNAL MEMORY EXPANSION PORT (PORT A)
SRAM Timing
Table 2-8 SRAM Read and Write Accesses3
No. Characteristics Symbol Expression1 (WS + 1) x TC - 4.0 [1 WS 3] tRC, tWC (WS + 2) x TC - 4.0 [4 WS 7] (WS + 3) x TC - 4.0 [WS 8] 101 Address and AA valid to WR assertion tAS 0.25 x TC - 2.0 [WS = 1] 1.25 x TC - 2.0 [WS 4] 102 WR assertion pulse width tWP 1.5 x TC - 4.0 [WS = 1] All frequencies: WS x TC - 4.0 [2 WS 3] (WS - 0.5) x TC - 4.0 [WS 4] WR deassertion to address not valid tWR 0.25 x TC - 2.0 [1 WS 3] 1.25 x TC - 2.0 [4 WS 7] 103 2.25 x TC - 2.0 [WS 8] All frequencies: 1.25 x TC - 4.0 [4 WS 7] 2.25 x TC - 4.0 [WS 8] 104 Address and AA valid to input data valid 105 RD assertion to input data valid 106 RD deassertion to data not valid (data hold time) 107 Address valid to WR deassertion2 108 Data valid to WR deassertion (data setup time) tAA, tAC tOE tOHZ tAW tDS (tDW) (WS + 0.75) x TC - 4.0 [WS 1] (WS - 0.25) x TC - 3.0 [WS 1] (WS + 0.75) x TC - 7.0 [WS 1] (WS + 0.25) x TC - 7.0 [WS 1] Min 12.0 46.0 87.0 0.1 8.4 8.5 12.7 25.2 0.1 8.4 16.7 6.4 14.7 -- -- 0.0 10.6 3.2 Max -- -- -- -- -- -- -- -- -- -- -- -- -- 7.6 3.4 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
100 Address valid and AA assertion pulse width
MOTOROLA
DSP56366 Advance Information
2-15
Specifications External Memory Expansion Port (Port A)
Table 2-8 SRAM Read and Write Accesses3 (Continued)
No. Characteristics Symbol Expression1 0.25 x TC - 2.0 [1 WS 3] 109 Data hold time from WR deassertion tDH 1.25 x TC - 2.0 [4 WS 7] 2.25 x TC - 2.0 [WS 8] 0.75 x TC - 3.7 [WS = 1] 110 WR assertion to data active -- 0.25 x TC - 3.7 [2 WS 3] -0.25 x TC - 3.7 [WS 4] 0.25 x TC + 0.2 [1 WS 3] 111 WR deassertion to data high impedance -- 1.25 x TC + 0.2 [4 WS 7] 2.25 x TC + 0.2 [WS 8] 1.25 x TC - 4.0 [1 WS 3] 112 Previous RD deassertion to data active (write) -- 2.25 x TC - 4.0 [4 WS 7] 3.25 x TC - 4.0 [WS 8] RD deassertion time 113 0.75 x TC - 4.0 [1 WS 3] 1.75 x TC - 4.0 [4 WS 7] 2.75 x TC - 4.0 [WS 8] 0.5 x TC - 4.0 [WS = 1] 114 WR deassertion time TC - 2.0 [2 WS 3] 2.5 x TC - 4.0 [4 WS 7] 3.5 x TC - 4.0 [WS 8] 115 Address valid to RD assertion 116 RD assertion pulse width 0.5 x TC - 4.0 (WS + 0.25) x TC -4.0 0.25 x TC - 2.0 [1 WS 3] 117 RD deassertion to address not valid 1.25 x TC - 2.0 [4 WS 7] 2.25 x TC - 2.0 [WS 8] Min 0.1 8.4 16.7 2.5 0.0 0.0 -- -- -- 6.4 14.7 23.1 2.2 10.6 18.9 0.2 6.3 16.8 25.2 0.2 6.4 0.1 8.4 16.7 Max -- -- -- -- -- -- 2.3 10.6 18.9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ns ns ns
2-16
DSP56366 Advance Information
MOTOROLA
Specifications External Memory Expansion Port (Port A)
Table 2-8 SRAM Read and Write Accesses3 (Continued)
No. Characteristics Symbol Expression1 0.25 x TC + 2.0 Min 4.1 0.0 Max -- -- Unit ns ns
118 TA setup before RD or WR deassertion4 119 TA hold after RD or WR deassertion Notes: 1. 2. 3. 4.
WS is the number of wait states specified in the BCR. Timings 100, 107 are guaranteed by design, not tested. All timings for 100 MHz are measured from 0.5 * Vcc to .05 * Vcc In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active
100 A0-A17 AA0-AA2 113 RD 115 WR 104 119 TA D0-D23 Data In
AA0468
116
117
105
106
118
Figure 2-9 SRAM Read Access
MOTOROLA
DSP56366 Advance Information
2-17
Specifications External Memory Expansion Port (Port A) 100 A0-A17 AA0-AA2 107 101 WR 114 RD 119 TA 108 109 D0-D23 Data Out 118 102 103
Figure 2-10 SRAM Write Access
2-18
DSP56366 Advance Information
MOTOROLA
Specifications External Memory Expansion Port (Port A)
DRAM Timing
The selection guides provided in Figure 2-11 and Figure 2-14 should be used for primary selection only. Final selection should be based on the timing provided in the following tables. As an example, the selection guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode DRAM. However, by using the information in the appropriate table, a designer may choose to evaluate whether fewer wait states might be used by determining which timing prevents operation at 100 MHz, running the chip at a slightly lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available), and control factors such as capacitive and resistive load to improve overall system performance.
DRAM Type (tRAC ns) 100 Note: This figure should be use for primary selection. For exact and detailed timings see the following tables.
80
70
60
50 40 66 80 100
120
Chip Frequency (MHz)
1 Wait States 2 Wait States
3 Wait States 4 Wait States
AA047
Figure 2-11 DRAM Page Mode Wait States Selection Guide
MOTOROLA
DSP56366 Advance Information
2-19
Specifications External Memory Expansion Port (Port A)
Table 2-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3
No. Characteristics Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses 132 133 134 135 136 137 CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS deassertion4 138 tCAC tAA tOFF tRSH tRHCP tCAS tCRP 0.75 x TC - 4.0 2 x TC - 4.0 0.75 x TC - 4.0 1.75 x TC - 6.0 3.25 x TC - 6.0 4.25 x TC - 6.0 6.25 x TC - 6.0 tCP tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH 0.5 x TC - 4.0 0.5 x TC - 4.0 0.75 x TC - 4.0 2 x TC - 4.0 0.75 x TC - 3.8 0.25 x TC - 3.7 0.5 x TC - 4.2 1.5 x TC - 4.5 1.75 x TC - 4.3 1.75 x TC - 4.3 0.25 x TC - 4.0 0.75 x TC - 4.0 Symbol Expression 20 MHz6 Min 2 x TC tPC 1.25 x TC TC - 7.5 1.5 x TC - 7.5 62.5 -- -- 0.0 33.5 96.0 33.5 81.5 156.5 206.5 306.5 21.0 21.0 33.5 96.0 33.7 8.8 20.8 70.5 83.2 83.2 8.5 33.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 42.5 67.5 -- -- -- -- -- 41.7 -- -- 0.0 21.0 62.7 21.0 52.3 102.2 135.5 202.1 12.7 12.7 21.0 62.7 21.2 4.6 12.5 45.5 54.0 54.0 4.3 21.0 -- 25.8 42.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100.0 Max -- 30 MHz6 Min 66.7 Max -- ns Unit
131
* BRW[1:0] = 00 * BRW[1:0] = 01 * BRW[1:0] = 10 * BRW[1:0] = 11
139 140 141 142 143 144 145 146 147 148 149 150
CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (Write) CAS assertion to data not valid (write)
2-20
DSP56366 Advance Information
MOTOROLA
Specifications External Memory Expansion Port (Port A)
Table 2-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 (Continued)
No. 151 152 153 154 155 156 Notes: Characteristics WR assertion to CAS assertion Last RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid WR assertion to data active WR deassertion to data high impedance 1. 2. 3. 4. 5. 6.
5
Symbol tWCS tROH tGA tGZ
Expression TC - 4.3 1.5 x TC - 4.0 TC - 7.5 0.75 x TC - 0.3 0.25 x TC
20 MHz6 Min 45.7 71.0 -- 0.0 37.2 -- Max -- -- 42.5 -- -- 12.5
30 MHz6 Min 29.0 46.0 -- 0.0 24.7 -- Max -- -- 25.8 -- -- 8.3
Unit ns ns ns ns ns ns
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 2 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See Figure 2-14.).
Table 2-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 7
No. Characteristics Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses 132 133 134 135 136 137 CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width tCAC tAA tOFF tRSH tRHCP tCAS 1.75 x TC - 4.0 3.25 x TC - 4.0 1.5 x TC - 4.0 Symbol Expression 66 MHz Min 45.4 Max -- 80 MHz Min 37.5 Max -- ns 1.25 x TC 1.5 x TC - 7.5 1.5 x TC - 6.5 2.5 x TC - 7.5 2.5 x TC - 6.5 41.1 -- -- -- -- 0.0 22.5 45.2 18.7 -- 15.2 -- 30.4 -- -- -- -- -- 34.4 -- -- -- -- 0.0 17.9 36.6 14.8 -- -- 12.3 -- 24.8 -- -- -- -- ns ns ns ns ns ns ns ns Unit
2 x TC tPC
131
MOTOROLA
DSP56366 Advance Information
2-21
Specifications External Memory Expansion Port (Port A)
Table 2-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 7 (Continued)
No. Characteristics Last CAS deassertion to RAS deassertion5 138 Symbol Expression 66 MHz Min 24.4 47.2 62.4 92.8 14.9 11.2 22.5 41.5 15.1 3.9 18.5 33.5 33.4 33.6 0.1 -- 22.5 10.9 33.9 -- -- 0.0 0.75 x TC - 0.3 0.25 x TC 11.1 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 19.0 -- -- -- 3.8 80 MHz Min 19.0 37.8 50.3 75.3 11.6 8.5 17.9 33.5 11.8 2.6 14.6 26.8 26.8 27.0 -- 0.1 17.9 8.2 27.3 -- -- 0.0 9.1 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15.4 -- -- 3.1 Unit
tCRP
2.0 x TC - 6.0 3.5 x TC - 6.0 4.5 x TC - 6.0 6.5 x TC - 6.0
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
* BRW[1:0] = 00 * BRW[1:0] = 01 * BRW[1:0] = 10 * BRW[1:0] = 11
139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) WR assertion to CAS assertion Last RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid WR assertion to data active WR deassertion to data high impedance
6
tCP tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS tROH tGA tGZ
1.25 x TC - 4.0 TC - 4.0 1.75 x TC - 4.0 3 x TC - 4.0 1.25 x TC - 3.8 0.5 x TC - 3.7 1.5 x TC - 4.2 2.5 x TC - 4.5 2.75 x TC - 4.3 2.5 x TC - 4.3 0.25 x TC - 3.7 0.25 x TC - 3.0 1.75 x TC - 4.0 TC - 4.3 2.5 x TC - 4.0 1.75 x TC - 7.5 1.75 x TC - 6.5
2-22
DSP56366 Advance Information
MOTOROLA
Specifications External Memory Expansion Port (Port A)
Table 2-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 7 (Continued)
No. Notes: 1. 2. 3. 4. 5. 6. 7. Characteristics Symbol Expression 66 MHz Min Max 80 MHz Min Max Unit
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56366. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 3 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. There are no DRAMs fast enough to fit to two wait states Page mode @ 100MHz (See Figure 2-11)
Table 2-11 DRAM Page Mode Timings, Three Wait States1, 2, 3
No. Characteristics Symbol tPC tCAC tAA tOFF tRSH tRHCP tCAS tCRP 2.5 x TC - 4.0 4.5 x TC - 4.0 2 x TC - 4.0 2.25 x TC - 6.0 3.75 x TC - 6.0 4.75 x TC - 6.0 6.75 x TC - 6.0 tCP tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS 1.5 x TC - 4.0 TC - 4.0 2.5 x TC - 4.0 4 x TC - 4.0 1.25 x TC - 4.0 0.75 x TC - 4.0 2.25 x TC - 4.2 3.5 x TC - 4.5 3.75 x TC - 4.3 3.25 x TC - 4.3 0.5 x TC - 4.0 Expression 2 x TC 1.25 x TC 2 x TC - 7.0 3 x TC - 7.0 Min 40.0 35.0 -- -- 0.0 21.0 41.0 16.0 -- -- 41.5 61.5 11.0 6.0 21.0 36.0 8.5 3.5 18.3 30.5 33.2 28.2 1.0 Max -- -- 13.0 23.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ns
Page mode cycle time for two consecutive accesses of the same 131 direction Page mode cycle time for mixed (read and write) accesses 132 CAS assertion to data valid (read) 133 Column address valid to data valid (read) 134 CAS deassertion to data not valid (read hold time) 135 Last CAS assertion to RAS deassertion 136 Previous CAS deassertion to RAS deassertion 137 CAS assertion pulse width Last CAS deassertion to RAS assertion5
* BRW[1:0] = 00
138 * BRW[1:0] = 01
* BRW[1:0] = 10 * BRW[1:0] = 11
139 CAS deassertion pulse width 140 Column address valid to CAS assertion 141 CAS assertion to column address not valid 142 Last column address valid to RAS deassertion 143 WR deassertion to CAS assertion 144 CAS deassertion to WR assertion 145 CAS assertion to WR deassertion 146 WR assertion pulse width 147 Last WR assertion to RAS deassertion 148 WR assertion to CAS deassertion 149 Data valid to CAS assertion (write)
MOTOROLA
DSP56366 Advance Information
2-23
Specifications External Memory Expansion Port (Port A)
Table 2-11 DRAM Page Mode Timings, Three Wait States1, 2, 3 (Continued)
No. Characteristics Symbol tDH tWCS tROH tGA tGZ 0.75 x TC - 0.3 0.25 x TC Expression 2.5 x TC - 4.0 1.25 x TC - 4.3 3.5 x TC - 4.0 2.5 x TC - 7.0 Min 21.0 8.2 31.0 -- 0.0 7.2 -- Max -- -- -- 18.0 -- -- 2.5 Unit ns ns ns ns ns ns ns
150 CAS assertion to data not valid (write) 151 WR assertion to CAS assertion 152 Last RD assertion to RAS deassertion 153 RD assertion to data valid 154 RD deassertion to data not valid6 155 WR assertion to data active 156 WR deassertion to data high impedance Notes: 1. 2. 3. 4. 5. 6.
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56366. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 4 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
2-24
DSP56366 Advance Information
MOTOROLA
Specifications External Memory Expansion Port (Port A)
Table 2-12 DRAM Page Mode Timings, Four Wait States1, 2, 3
No. 131 132 133 134 135 136 137 Characteristics Page mode cycle time for two consecutive accesses of the same direction. Page mode cycle time for mixed (read and write) accesses CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS assertion5 tCAC tAA tOFF tRSH tRHCP tCAS tCRP 3.5 x TC - 4.0 6 x TC - 4.0 2.5 x TC - 4.0 2.75 x TC - 6.0 4.25 x TC - 6.0 5.25 x TC - 6.0 7.25 x TC - 6.0 tCP tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS tROH tGA tGZ 0.75 x TC - 0.3 0.25 x TC 2 x TC - 4.0 TC - 4.0 3.5 x TC - 4.0 5 x TC - 4.0 1.25 x TC - 4.0 1.25 x TC - 4.0 3.25 x TC - 4.2 4.5 x TC - 4.5 4.75 x TC - 4.3 3.75 x TC - 4.3 0.5 x TC - 4.0 3.5 x TC - 4.0 1.25 x TC - 4.3 4.5 x TC - 4.0 3.25 x TC - 7.0 Symbol tPC Expression 5 x TC 4.5 x TC 2.75 x TC - 7.0 3.75 x TC - 7.0 Min 41.7 37.5 -- -- 0.0 25.2 46.0 16.8 -- -- 37.7 54.4 12.7 4.3 25.2 37.7 6.4 6.4 22.9 33.0 35.3 26.9 0.2 25.2 6.1 33.5 -- 0.0 5.9 -- Max -- -- 15.9 24.2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20.1 -- -- 2.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
* BRW[1:0] = 00
138
* BRW[1:0] = 01 * BRW[1:0] = 10 * BRW[1:0] = 11
139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) WR assertion to CAS assertion Last RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid6 WR assertion to data active WR deassertion to data high impedance
MOTOROLA
DSP56366 Advance Information
2-25
Specifications External Memory Expansion Port (Port A)
Table 2-12 DRAM Page Mode Timings, Four Wait States1, 2, 3 (Continued)
No. Notes: 1. 2. 3. 4. 5. 6. Characteristics Symbol Expression Min Max The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56366. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 3 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
RAS 136 131 CAS 137 140
Row Add Column Address
135
139 141
Column Address
138 142
Last Column Address
A0-A17
151 145 WR 146 RD 155 149 D0-D23
Data Out
144
143 147
148
156 150
Data Out Data Out AA0473
Figure 2-12 DRAM Page Mode Write Accesses
2-26
DSP56366 Advance Information
MOTOROLA
Specifications External Memory Expansion Port (Port A)
RAS
136 131 CAS 137 140 A0-A17
Row Add Column Address
135
139 141
Column Address
138 142
Last Column Address
143 WR 132 133 153 RD 134 154 D0-D23
Data In Data In Data In AA0474
152
Figure 2-13 DRAM Page Mode Read Accesses
MOTOROLA
DSP56366 Advance Information
2-27
Specifications External Memory Expansion Port (Port A) DRAM Type (tRAC ns) 100 Note:This figure should be use for primary selection. For exact and detailed timings see the following tables.
80
70
60
50
40
66
80
100
120 11 Wait States 15 Wait States
Chip Frequency (MHz)
4 Wait States 8 Wait States
AA0475
Figure 2-14 DRAM Out-of-Page Wait States Selection Guide
Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2
No. 157 158 159 160 161 162 163 Characteristics3 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width Symbol tRC tRAC tCAC tAA tOFF tRP tRAS 1.75 x TC - 4.0 3.25 x TC - 4.0 Expression 5 x TC 2.75 x TC - 7.5 1.25 x TC - 7.5 1.5 x TC - 7.5 20 MHz4 Min 250.0 -- -- -- 0.0 83.5 158.5 Max -- 130.0 55.0 67.5 -- -- -- 30 MHz4 Min 166.7 -- -- -- 0.0 54.3 104.3 Max -- 84.2 34.2 42.5 -- -- -- ns ns ns ns ns ns ns Unit
2-28
DSP56366 Advance Information
MOTOROLA
Specifications External Memory Expansion Port (Port A)
Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (Continued)
No. 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 Characteristics3 CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion RAS deassertion to WR assertion CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion Symbol tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS Expression 1.75 x TC - 4.0 2.75 x TC - 4.0 1.25 x TC - 4.0 1.5 x TC 2 1.25 x TC 2 2.25 x TC - 4.0 1.75 x TC - 4.0 1.75 x TC - 4.0 1.25 x TC - 4.0 0.25 x TC - 4.0 1.75 x TC - 4.0 3.25 x TC - 4.0 2 x TC - 4.0 1.5 x TC - 3.8 0.75 x TC - 3.7 0.25 x TC - 3.7 1.5 x TC - 4.2 3 x TC - 4.2 4.5 x TC - 4.5 4.75 x TC - 4.3 4.25 x TC - 4.3 2.25 x TC - 4.0 1.75 x TC - 4.0 3.25 x TC - 4.0 3 x TC - 4.3 20 MHz4 Min 83.5 133.5 58.5 73.0 60.5 108.5 83.5 83.5 58.5 8.5 83.5 158.5 96.0 71.2 33.8 8.8 70.8 145.8 220.5 233.2 208.2 108.5 83.5 158.5 145.7 Max -- -- -- 77.0 64.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30 MHz4 Min 54.3 87.7 37.7 48.0 39.7 71.0 54.3 54.3 37.7 4.3 54.3 104.3 62.7 46.2 21.3 4.6 45.8 95.8 145.5 154.0 137.4 71.0 54.3 104.3 95.7 Max -- -- -- 52.0 43.7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
MOTOROLA
DSP56366 Advance Information
2-29
Specifications External Memory Expansion Port (Port A)
Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (Continued)
No. Characteristics3 CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid3 WR assertion to data active WR deassertion to data high impedance 1. 2. 3. 4. Symbol Expression 20 MHz4 Min tCSR tRPC tROH tGA tGZ 0.75 x TC - 0.3 0.25 x TC 0.5 x TC - 4.0 1.25 x TC - 4.0 4.5 x TC - 4.0 4 x TC - 7.5 21.0 58.5 221.0 -- 0.0 37.2 -- Max -- -- -- 192.5 -- -- 12.5 30 MHz4 Min 12.7 37.7 146.0 -- 0.0 24.7 -- Max -- -- -- 125.8 -- -- 8.3 ns ns ns ns ns ns ns Unit
189 190 191 192 193 194 195 Notes:
The number of wait states for out of page access is specified in the DCR. The refresh period is specified in the DCR. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (See Figure 2-17.).
Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2
No. Characteristics4 Symbol tRC tRAC tCAC tAA tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD 3.25 x TC - 4.0 5.75 x TC - 4.0 3.25 x TC - 4.0 4.75 x TC - 4.0 2.25 x TC - 4.0 2.5 x TC 2 1.75 x TC 2 Expression3 9 x TC 4.75 x TC - 7.5 4.75 x TC - 6.5 2.25 x TC - 7.5 2.25 x TC - 6.5 3 x TC - 7.5 3 x TC - 6.5 66 MHz Min 136.4 -- -- -- -- -- -- 0.0 45.2 83.1 45.2 68.0 30.1 35.9 24.5 Max -- 64.5 -- 26.6 -- 40.0 -- -- -- -- -- -- -- 39.9 28.5
80 MHz
Min 112.5 -- -- -- -- -- -- 0.0 36.6 67.9 36.6 55.5 24.1 29.3 19.9 Max -- -- 52.9 -- 21.6 -- 31.0 -- -- -- -- -- -- 33.3 23.9
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
157 Random read or write cycle time 158 RAS assertion to data valid (read) 159 CAS assertion to data valid (read) 160 Column address valid to data valid (read) 161 CAS deassertion to data not valid (read hold time) 162 RAS deassertion to RAS assertion 163 RAS assertion pulse width 164 CAS assertion to RAS deassertion 165 RAS assertion to CAS deassertion 166 CAS assertion pulse width 167 RAS assertion to CAS assertion 168 RAS assertion to column address valid
2-30
DSP56366 Advance Information
MOTOROLA
Specifications External Memory Expansion Port (Port A)
Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (Continued)
No. Characteristics4 Symbol tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH tGA valid4 tGZ Expression3 4.25 x TC - 4.0 2.75 x TC - 4.0 3.25 x TC - 4.0 1.75 x TC - 4.0 0.75 x TC - 4.0 3.25 x TC - 4.0 5.75 x TC - 4.0 4 x TC - 4.0 2 x TC - 3.8 1.25 x TC - 3.7 0.25 x TC - 3.7 0.25 x TC - 3.0 3 x TC - 4.2 5.5 x TC - 4.2 8.5 x TC - 4.5 8.75 x TC - 4.3 7.75 x TC - 4.3 4.75 x TC - 4.0 3.25 x TC - 4.0 5.75 x TC - 4.0 5.5 x TC - 4.3 1.5 x TC - 4.0 1.75 x TC - 4.0 8.5 x TC - 4.0 7.5 x TC - 7.5 7.5 x TC - 6.5 0.0 0.75 x TC - 0.3 0.25 x TC 66 MHz Min 59.8 37.7 45.2 22.5 7.4 45.2 83.1 56.6 26.5 15.2 0.1 -- 41.3 79.1 124.3 128.3 113.1 68.0 45.2 83.1 79.0 18.7 22.5 124.8 -- -- 0.0 11.1 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 106.1 -- -- -- 3.8
80 MHz
Min 49.1 30.4 36.6 17.9 5.4 36.6 67.9 46.0 21.2 11.9 -- 0.1 33.3 64.6 101.8 105.1 92.6 55.4 36.6 67.9 64.5 14.8 17.9 102.3 -- -- 0.0 9.1 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 87.3 -- -- 3.1
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
169 CAS deassertion to RAS assertion 170 CAS deassertion pulse width 171 Row address valid to RAS assertion 172 RAS assertion to row address not valid 173 Column address valid to CAS assertion 174 CAS assertion to column address not valid 175 RAS assertion to column address not valid 176 Column address valid to RAS deassertion 177 WR deassertion to CAS assertion 178 CAS deassertion to WR5 assertion
179 RAS deassertion to WR5 assertion 180 CAS assertion to WR deassertion 181 RAS assertion to WR deassertion 182 WR assertion pulse width 183 WR assertion to RAS deassertion 184 WR assertion to CAS deassertion 185 Data valid to CAS assertion (write) 186 CAS assertion to data not valid (write) 187 RAS assertion to data not valid (write) 188 WR assertion to CAS assertion 189 CAS assertion to RAS assertion (refresh) 190 RAS deassertion to CAS assertion (refresh) 191 RD assertion to RAS deassertion 192 RD assertion to data valid 193 RD deassertion to data not
194 WR assertion to data active 195 WR deassertion to data high impedance
MOTOROLA
DSP56366 Advance Information
2-31
Specifications External Memory Expansion Port (Port A)
Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (Continued)
No. Notes: 1. 2. 3. 4. 5. Characteristics4 Symbol Expression3 66 MHz Min Max
80 MHz
Min Max
Unit
The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56366. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Either tRCH or tRRH must be satisfied for read cycles.
2-32
DSP56366 Advance Information
MOTOROLA
Specifications External Memory Expansion Port (Port A)
Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2
No. Characteristics4 Symbol tRC tRAC tCAC tAA tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH 4.25 x TC - 4.0 7.75 x TC - 4.0 5.25 x TC - 4.0 6.25 x TC - 4.0 3.75 x TC - 4.0 2.5 x TC 4.0 1.75 x TC 4.0 5.75 x TC - 4.0 4.25 x TC - 4.0 4.25 x TC - 4.0 1.75 x TC - 4.0 0.75 x TC - 4.0 5.25 x TC - 4.0 7.75 x TC - 4.0 6 x TC - 4.0 3.0 x TC - 4.0 1.75 x TC - 4.0 0.25 x TC - 2.0 5 x TC - 4.2 7.5 x TC - 4.2 11.5 x TC - 4.5 11.75 x TC - 4.3 10.25 x TC - 4.3 5.75 x TC - 4.0 5.25 x TC - 4.0 7.75 x TC - 4.0 6.5 x TC - 4.3 1.5 x TC - 4.0 2.75 x TC - 4.0 11.5 x TC - 4.0 Expression3 12 x TC 6.25 x TC - 7.0 3.75 x TC - 7.0 4.5 x TC - 7.0 Min 120.0 -- -- -- 0.0 38.5 73.5 48.5 58.5 33.5 21.0 13.5 53.5 38.5 38.5 13.5 3.5 48.5 73.5 56.0 26.0 13.5 0.5 45.8 70.8 110.5 113.2 103.2 53.5 48.5 73.5 60.7 11.0 23.5 111.0 Max -- 55.5 30.5 38.0 -- -- -- -- -- -- 29.0 21.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
157 Random read or write cycle time 158 RAS assertion to data valid (read) 159 CAS assertion to data valid (read) 160 Column address valid to data valid (read) 161 CAS deassertion to data not valid (read hold time) 162 RAS deassertion to RAS assertion 163 RAS assertion pulse width 164 CAS assertion to RAS deassertion 165 RAS assertion to CAS deassertion 166 CAS assertion pulse width 167 RAS assertion to CAS assertion 168 RAS assertion to column address valid 169 CAS deassertion to RAS assertion 170 CAS deassertion pulse width 171 Row address valid to RAS assertion 172 RAS assertion to row address not valid 173 Column address valid to CAS assertion 174 CAS assertion to column address not valid 175 RAS assertion to column address not valid 176 Column address valid to RAS deassertion 177 WR deassertion to CAS assertion 178 CAS deassertion to WR5 assertion 179 RAS deassertion to WR5 assertion 180 CAS assertion to WR deassertion 181 RAS assertion to WR deassertion 182 WR assertion pulse width 183 WR assertion to RAS deassertion 184 WR assertion to CAS deassertion 185 Data valid to CAS assertion (write) 186 CAS assertion to data not valid (write) 187 RAS assertion to data not valid (write) 188 WR assertion to CAS assertion 189 CAS assertion to RAS assertion (refresh) 190 RAS deassertion to CAS assertion (refresh) 191 RD assertion to RAS deassertion
MOTOROLA
DSP56366 Advance Information
2-33
Specifications External Memory Expansion Port (Port A)
Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (Continued)
No. Characteristics4 Symbol tGA tGZ 0.75 x TC - 0.3 0.25 x TC Expression3 10 x TC - 7.0 Min -- 0.0 7.2 -- Max 93.0 -- -- 2.5 Unit ns ns ns ns
192 RD assertion to data valid 193 RD deassertion to data not valid4 194 WR assertion to data active 195 WR deassertion to data high impedance Notes: 1. 2. 3. 4. 5.
The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56366. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Either tRCH or tRRH must be satisfied for read cycles.
Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2
No. Characteristics3 Symbol tRC tRAC tCAC tAA tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH Expression 16 x TC 8.25 x TC - 5.7 4.75 x TC - 5.7 5.5 x TC - 5.7 0.0 6.25 x TC - 4.0 9.75 x TC - 4.0 6.25 x TC - 4.0 8.25 x TC - 4.0 4.75 x TC - 4.0 3.5 x TC 2 2.75 x TC 2 7.75 x TC - 4.0 6.25 x TC - 4.0 6.25 x TC - 4.0 2.75 x TC - 4.0 0.75 x TC - 4.0 6.25 x TC - 4.0 9.75 x TC - 4.0 7 x TC - 4.0 5 x TC - 3.8 1.75 x TC - 3.7 Min 133.3 -- -- -- 0.0 48.1 77.2 48.1 64.7 35.6 27.2 20.9 60.6 48.1 48.1 18.9 2.2 48.1 77.2 54.3 37.9 10.9 Max -- 63.0 33.9 40.1 -- -- -- -- -- -- 31.2 24.9 -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
157 Random read or write cycle time 158 RAS assertion to data valid (read) 159 CAS assertion to data valid (read) 160 Column address valid to data valid (read) 161 CAS deassertion to data not valid (read hold time) 162 RAS deassertion to RAS assertion 163 RAS assertion pulse width 164 CAS assertion to RAS deassertion 165 RAS assertion to CAS deassertion 166 CAS assertion pulse width 167 RAS assertion to CAS assertion 168 RAS assertion to column address valid 169 CAS deassertion to RAS assertion 170 CAS deassertion pulse width 171 Row address valid to RAS assertion 172 RAS assertion to row address not valid 173 Column address valid to CAS assertion 174 CAS assertion to column address not valid 175 RAS assertion to column address not valid 176 Column address valid to RAS deassertion 177 WR deassertion to CAS assertion 178 CAS deassertion to WR5 assertion
2-34
DSP56366 Advance Information
MOTOROLA
Specifications External Memory Expansion Port (Port A)
Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (Continued)
No. Characteristics3 Symbol tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH tGA tGZ 0.75 x TC - 0.3 0.25 x TC Expression 0.25 x TC - 2.0 6 x TC - 4.2 9.5 x TC - 4.2 15.5 x TC - 4.5 15.75 x TC - 4.3 14.25 x TC - 4.3 8.75 x TC - 4.0 6.25 x TC - 4.0 9.75 x TC - 4.0 9.5 x TC - 4.3 1.5 x TC - 4.0 4.75 x TC - 4.0 15.5 x TC - 4.0 14 x TC - 5.7 Min 0.1 45.8 75.0 124.7 126.9 114.4 68.9 48.1 77.2 74.9 8.5 35.6 125.2 -- 0.0 5.9 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- 111.0 -- -- 2.1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
179 RAS deassertion to WR5 assertion 180 CAS assertion to WR deassertion 181 RAS assertion to WR deassertion 182 WR assertion pulse width 183 WR assertion to RAS deassertion 184 WR assertion to CAS deassertion 185 Data valid to CAS assertion (write) 186 CAS assertion to data not valid (write) 187 RAS assertion to data not valid (write) 188 WR assertion to CAS assertion 189 CAS assertion to RAS assertion (refresh) 190 RAS deassertion to CAS assertion (refresh) 191 RD assertion to RAS deassertion 192 RD assertion to data valid 193 RD deassertion to data not valid3 194 WR assertion to data active 195 WR deassertion to data high impedance Notes: 1. 2. 3. 4.
The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Either tRCH or tRRH must be satisfied for read cycles.
MOTOROLA
DSP56366 Advance Information
2-35
Specifications External Memory Expansion Port (Port A) 157 162 RAS 167 169 170 CAS 171 173 174 175 A0-A17
Row Address Column Address
163 165
162
164 166
168
172 177 191 WR 160 159 RD 158 192 D0-D23
176 179
168
193 161
Data In AA0476
Figure 2-15 DRAM Out-of-Page Read Access
2-36
DSP56366 Advance Information
MOTOROLA
Specifications External Memory Expansion Port (Port A) 157 162 RAS 167 169 168 170 CAS 171 173 172 176 A0-A17 Row Address 181 175 188 WR 182 184 183 RD 185 194 D0-D23 Data Out
AA0477
163 165 164
162
166
174
Column Address
180
187 186 195
Figure 2-16 DRAM Out-of-Page Write Access
MOTOROLA
DSP56366 Advance Information
2-37
Specifications External Memory Expansion Port (Port A) 157 162 RAS 190 170 CAS 189 177 WR
AA0478
163
162
165
Figure 2-17 DRAM Refresh Access
2-38
DSP56366 Advance Information
MOTOROLA
Specifications External Memory Expansion Port (Port A)
Arbitration Timings
Table 2-17 Asynchronous Bus Arbitration timing
No. Characteristics
BB assertion window from BG input negation. Delay from BB assertion to BG assertion
Expression
120 MHz Min
-- 21.7
Max
25.8 --
Unit
250 251
2 .5* Tc + 5 2 * Tc + 5
ns ns
Comments: 1. Bit 13 in the OMR register must be set to enter Asynchronous Arbitration mode 2. If Asynchronous Arbitration mode is active, none of the timings in Table 2-17 is required. 3. In order to guarantee timings 250, and 251, it is recommended to assert BG inputs to different 56300 devices (on the same bus) in a non overlap manner as shown in Figure 2-18.
BG1
BB 250
BG2 251
Figure 2-18 Asynchronous Bus Arbitration Timing
BG1
BG2
250+251
Figure 2-19 Asynchronous Bus Arbitration Timing
MOTOROLA DSP56366 Advance Information 2-39
Specifications External Memory Expansion Port (Port A)
Background explanation for Asynchronous Bus Arbitration: The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs. These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this delay, a 56300 part may assume mastership and assert BB for some time after BG is negated. This is the reason for timing 250. Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other 56300 components which are potential masters on the same bus. If BG input is asserted before that time, a situation of BG asserted, and BB negated, may cause another 56300 component to assume mastership at the same time. Therefore some non-overlap period between one BG input active to another BG input active is required. Timing 251 ensures that such a situation is avoided.
2-40
DSP56366 Advance Information
MOTOROLA
Specifications Parallel Host Interface (HDI08) Timing
PARALLEL HOST INTERFACE (HDI08) TIMING
Table 2-18 Host Interface (HDI08) Timing1, 2
No. Characteristics3
Read data strobe assertion width4 HACK read assertion width Read data strobe deassertion width4 HACK read deassertion width
Expression
120 MHz Min Max
18.3 9.9 -- --
Unit
317 318
TC + 9.9 --
ns ns
Read data strobe deassertion width4 after "Last Data Register" reads5,6, or between two consecutive CVR, ICR, 319 or ISR reads7 HACK deassertion width after "Last Data Register" reads5,6 320 Write data strobe assertion width8 HACK write assertion width Write data strobe deassertion width8 HACK write deassertion width * after ICR, CVR and "Last Data Register" writes5 * after IVR writes, or * after TXH:TXM writes (with HBE=0), or
2.5 x TC + 6.6
27.4
--
ns
--
13.2
--
ns
2.5 x TC + 6.6
27.4
--
ns
321
* after TXL:TXM writes (with HBE=1)
322 HAS assertion width 323 HAS deassertion to data strobe assertion9 Host data input setup time before write data strobe 324 deassertion8 Host data input setup time before HACK write deassertion Host data input hold time after write data strobe 325 deassertion8 Host data input hold time after HACK write deassertion Read data strobe assertion to output data active from high impedance4 326 HACK read assertion to output data active from high impedance 327 Read data strobe assertion to output data valid4 HACK read assertion to output data valid -- -- --
16.5 9.9 0.0 9.9
-- -- -- -- ns ns ns
--
3.3
--
ns
--
3.3
--
ns
--
--
24.2
ns
Read data strobe deassertion to output data high 328 impedance4 HACK read deassertion to output data high impedance 329 Output data hold time after read data strobe deassertion4 Output data hold time after HACK read deassertion
--
--
9.9
ns
-- TC +9.9 -- --
3.3 18.2 9.9 --
-- -- -- 19.1
ns ns ns ns
330 HCS assertion to read data strobe deassertion4 331 HCS assertion to write data strobe deassertion8 332 HCS assertion to output data valid
MOTOROLA
DSP56366 Advance Information
2-41
Specifications Parallel Host Interface (HDI08) Timing
Table 2-18 Host Interface (HDI08) Timing1, 2 (Continued)
No. Characteristics3 Expression
-- -- --
120 MHz Min Max
0.0 4.7 3.3 -- -- --
Unit
ns ns ns
333 HCS hold time after data strobe deassertion9 334 335 Address (AD7-AD0) setup time before HAS deassertion (HMUX=1) Address (AD7-AD0) hold time after HAS deassertion (HMUX=1)
A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W setup time before data strobe assertion9 336 * Read * Write 337 338 339 A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W hold time after data strobe deassertion9 Delay from read data strobe deassertion to host request assertion for "Last Data Register" read4, 5, 10 Delay from write data strobe deassertion to host request assertion for "Last Data Register" write5, 8, 10 TC 2 x TC
--
0 4.7
-- -- -- -- --
ns
--
3.3 8.3 16.7
ns ns ns
Delay from data strobe assertion to host request 340 deassertion for "Last Data Register" read or write (HROD = 0)5, 9, 10 Delay from data strobe assertion to host request 341 deassertion for "Last Data Register" read or write (HROD = 1, open drain Host Request)5, 9, 10, 11 Delay from DMA HACK deassertion to HOREQ assertion * For "Last Data Register" read5 342 * For "Last Data Register" write * For other cases 343 Delay from DMA HACK assertion to HOREQ deassertion * HROD = 05
5
--
--
19.1
ns
--
--
300.0
ns
2 x TC + 19.1 1.5 x TC + 19.1
35.8 31.6 0.0
-- -- -- 20.2
ns
--
--
ns
Delay from DMA HACK assertion to HOREQ deassertion 344 for "Last Data Register" read or write * HROD = 1, open drain Host Request5, 11
--
--
300.0
ns
2-42
DSP56366 Advance Information
MOTOROLA
Specifications Parallel Host Interface (HDI08) Timing
Table 2-18 Host Interface (HDI08) Timing1, 2 (Continued)
No.
Notes: 1. 2.
Characteristics3
Expression
120 MHz Min Max
Unit
See Host Port Usage Considerations in the DSP56366 User's Manual. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. 3. VCC = 3.3 V 0.16 V; TJ = -40C to +105C, CL = 50 pF 4. The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode. 5. The "last data register" is the register at address $7, which is the last location to be read or written in data transfers. 6. This timing is applicable only if a read from the "last data register" is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal. 7. This timing is applicable only if two consecutive reads from one of these registers are executed. 8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode. 9. The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single data strobe mode. 10. The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode. 11. In this calculation, the host request signal is pulled up by a 4.7 k resistor in the open-drain mode.
317 HACK 327 HD7-HD0 326 329 328
318
HOREQ
AA1105
Figure 2-20 Host Interrupt Vector Register (IVR) Read Timing Diagram
MOTOROLA
DSP56366 Advance Information
2-43
Specifications Parallel Host Interface (HDI08) Timing
HA0-HA2 336 330 HCS 337 333
317 HRD, HDS 318 328 332 327 326 HD0-HD7 340 341 HOREQ, HRRQ, HTRQ 338 319 329
AA0484
Figure 2-21 Read Timing Diagram, Non-Multiplexed Bus
2-44
DSP56366 Advance Information
MOTOROLA
Specifications Parallel Host Interface (HDI08) Timing
HA0-HA2 336 337 331 333 HCS
320 HWR, HDS 321 324 325 HD0-HD7 340 341 HOREQ, HRRQ, HTRQ
AA0485
339
Figure 2-22 Write Timing Diagram, Non-Multiplexed Bus
MOTOROLA
DSP56366 Advance Information
2-45
Specifications Parallel Host Interface (HDI08) Timing
HA8-HA10 322 HAS 336 337
323 317
HRD, HDS 334 335 327 329 HAD0-HAD7 Address 326 340 341 HOREQ, HRRQ, HTRQ
AA0486
318 319 328
Data
338
Figure 2-23 Read Timing Diagram, Multiplexed Bus
2-46
DSP56366 Advance Information
MOTOROLA
Specifications Parallel Host Interface (HDI08) Timing
HA8-HA10 322 HAS 336
323 320
HWR, HDS 334 335 HAD0-HAD7 Address 340 341 HOREQ, HRRQ, HTRQ
AA0487
324
321 325
Data 339
Figure 2-24 Write Timing Diagram, Multiplexed Bus
HOREQ (Output)
343 344 320 342
321
HACK (Input)
TXH/M/L Write 324 325
H0-H7 (Input)
Data Valid
Figure 2-25 Host DMA Write Timing Diagram
MOTOROLA
DSP56366 Advance Information
2-47
Specifications Parallel Host Interface (HDI08) Timing
HOREQ (Output)
343 342 342 317 RXH Read 327 328 329 Data Valid 318
HACK (Input)
H0-H7 (Output)
326
Figure 2-26 Host DMA Read Timing Diagram
2-48
DSP56366 Advance Information
MOTOROLA
Specifications Serial Host Interface SPI Protocol Timing
SERIAL HOST INTERFACE SPI PROTOCOL TIMING
Table 2-19 Serial Host Interface SPI Protocol Timing
No. Characteristics1 Mode Filter Mode Bypassed 140 Tolerable spike width on clock or data in -- Narrow Wide Bypassed 141 Minimum serial clock cycle = tSPICC(min) Master Narrow Wide Bypassed Master 142 Serial clock high period Slave Narrow Wide Bypassed Narrow Wide Bypassed Master 143 Serial clock low period Slave Master Slave Narrow Wide Bypassed Narrow Wide 144 Serial clock rise/fall time -- -- Bypassed SS assertion to first SCK edge CPHA = 0 146 Slave CPHA = 1 Bypassed Narrow Wide Bypassed 147 Last SCK edge to SS not asserted Slave Narrow Wide Bypassed Master/ 148 Data input valid to SCK edge (data input setSlave up time) Narrow Wide 10 0 0 12 102 189 0 MAX{(20-TC), 0} MAX{(40-TC), 0} 10 0 0 12 102 189 0 11.7 31.7 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns Slave Narrow Wide Expression -- -- -- 6xTC+46 6xTC+152 6xTC+223 0.5xtSPICC -10 0.5xtSPICC -10 0.5xtSPICC -10 2.5xTC+12 2.5xTC+102 2.5xTC+189 0.5xtSPICC -10 0.5xtSPICC -10 0.5xtSPICC -10 2.5xTC+12 2.5xTC+102 2.5xTC+189 -- -- 3.5xTC+15 0 0 Min -- -- -- 96 202 273 38 91 126.5 32.8 122.8 209.8 38 91 126.5 32.8 122.8 209.8 -- -- 44.2 0 0 Max 0 50 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 2000 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MOTOROLA
DSP56366 Advance Information
2-49
Specifications Serial Host Interface SPI Protocol Timing
Table 2-19 Serial Host Interface SPI Protocol Timing (Continued)
No. Characteristics1 Mode Filter Mode Bypassed 149 SCK last sampling edge to data input not valid 150 SS assertion to data out active 151 SS deassertion to data high impedance2 152 SCK edge to data out valid (data out delay time) Master/ Slave Slave Slave Master/ Slave Narrow Wide -- -- Bypassed Narrow Wide Bypassed 153 SCK edge to data out not valid (data out hold time) 154 SS assertion to data out valid (CPHA = 0) 157 First SCK sampling edge to HREQ output deassertion Master/ Slave Narrow Wide Slave -- Bypassed Slave Narrow Wide Bypassed 158 Last SCK sampling edge to HREQ output not deasserted (CPHA = 1) 159 SS deassertion to HREQ output not deasserted (CPHA = 0) 160 SS deassertion pulse width (CPHA = 0) Slave Narrow Wide Slave Slave -- -- Bypassed 161 HREQ in assertion to first SCK edge Master Narrow Wide 162 HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) (CPHA = 1) 163 Notes: First SCK edge to HREQ in not asserted (HREQ in hold time) 1. 2. Master Master -- -- Expression 2.5xTC+10 2.5xTC+30 2.5xTC+50 2 9 2xTC+33 2xTC+123 2xTC+210 TC+5 TC+55 TC+106 TC+33 2.5xTC+30 2.5xTC+120 2.5xTC+217 2.5xTC+30 2.5xTC+80 2.5xTC+136 2.5xTC+30 TC+6 0.5 x tSPICC + 2.5xTC+43 0.5 xtSPICC + 2.5xTC+43 0.5 xtSPICC + 2.5xTC+43 0 0 Min 30.8 50.8 70.8 2 -- -- -- -- 13.3 63.3 114.3 -- -- -- -- 50.8 100.8 156.8 50.8 14.3 111.8 164.8 200.3 0 0 Max -- -- -- -- 9 49.7 139.7 226.7 -- -- -- 41.3 50.8 140.8 237.8 -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
VCC = 3.16 V 0.16 V; TJ = -40C to +105C, CL = 50 pF Periodically sampled, not 100% tested
2-50
DSP56366 Advance Information
MOTOROLA
Specifications Serial Host Interface SPI Protocol Timing
SS (Input) 143 142 SCK (CPOL = 0) (Output) 142 143 SCK (CPOL = 1) (Output) 148 149 MISO (Input)
MSB Valid
141 144 144
144
141 144
148
LSB Valid
149
152 MOSI (Output) 161 HREQ (Input) MSB
153 LSB
163
AA0271
Figure 2-27 SPI Master Timing (CPHA = 0)
MOTOROLA
DSP56366 Advance Information
2-51
Specifications Serial Host Interface SPI Protocol Timing
SS (Input) 143 142 SCK (CPOL = 0) (Output) 142 143 SCK (CPOL = 1) (Output) 149 MISO (Input)
MSB Valid LSB Valid
141 144 144
141 144 144
148
148 149
152 MOSI (Output) 161 163 HREQ (Input) MSB 162
153 LSB
AA0272
Figure 2-28 SPI Master Timing (CPHA = 1)
2-52
DSP56366 Advance Information
MOTOROLA
Specifications Serial Host Interface SPI Protocol Timing
SS (Input) 143 142 SCK (CPOL = 0) (Input) 146 142 143 SCK (CPOL = 1) (Input) 154 150 MISO (Output) 148 149 MOSI (Input)
MSB Valid LSB Valid
141 144 144 160
147
144
141 144
153 MSB
152
153
151 LSB 148 149
157 HREQ (Output)
159
AA0273
Figure 2-29 SPI Slave Timing (CPHA = 0)
MOTOROLA
DSP56366 Advance Information
2-53
Specifications Serial Host Interface SPI Protocol Timing
SS (Input) 143 142 SCK (CPOL = 0) (Input) 146 142 143 SCK (CPOL = 1) (Input) 152 150 MISO (Output) 148 149 MOSI (Input) HREQ (Output)
AA0274
MSB Valid LSB Valid
141 144 144
147
144
144
152
153
151 LSB 148 149
MSB
157
158
Figure 2-30 SPI Slave Timing (CPHA = 1)
2-54
DSP56366 Advance Information
MOTOROLA
Specifications Serial Host Interface (SHI) I2C Protocol Timing
SERIAL HOST INTERFACE (SHI) I2C PROTOCOL TIMING
Table 2-20 SHI I2C Protocol Timing
No. Characteristics1,2,3 Tolerable spike width on SCL or SDA Filters bypassed Narrow filters enabled Wide filters enabled 171 171 172 173 174 175 176 177 178 179 180 SCL clock frequency SCL clock cycle Bus free time Start condition set-up time Start condition hold time SCL low period SCL high period SCL and SDA rise time SCL and SDA fall time Data set-up time Data hold time DSP clock frequency 181 Filters bypassed Narrow filters enabled Wide filters enabled 182 183 184 SCL low to data out valid Stop condition set-up time HREQ in deassertion to last SCL edge (HREQ in set-up time) First SCL sampling edge to HREQ output deassertion 186 Filters bypassed Narrow filters enabled Wide filters enabled Last SCL edge to HREQ output not deasserted 187 Filters bypassed Narrow filters enabled Wide filters enabled TVD;DAT TSU;STO tSU;RQI TNG;RQO 2 x TC + 30 2 x TC + 120 2 x TC + 208 TAS;RQO 2 x TC + 30 2 x TC + 80 2 x TC + 135 46.7 96.7 151.6 -- -- -- 46.7 96.7 151.6 -- -- -- ns -- -- -- 46.7 136.7 224.7 -- -- -- 46.7 136.7 224.7 ns FDSP 10.6 11.8 13.1 -- 4.0 0.0 -- -- -- 3.4 -- -- 28.5 39.7 61.0 -- 0.6 0.0 -- -- -- 0.9 -- -- MHz MHz MHz s s ns FSCL TSCL TBUF TSU;STA THD;STA TLOW THIGH TR TF TSU;DAT THD;DAT -- -- -- -- -- 10 4.7 4.7 4.0 4.7 4.0 -- -- 250 0.0 0 50 100 100 -- -- -- -- -- -- 1000 300 -- -- -- -- -- -- 2.5 1.3 0.6 0.6 1.3 1.3 20 + 0.1 x Cb 20 + 0.1 x Cb 100 0.0 0 50 100 400 -- -- -- -- -- -- 300 300 -- 0.9 ns ns ns kHz s s s s s s ns ns ns s Symbol/ Expression Standard Mode4 Min Max Fast Mode5 Min Max Unit
MOTOROLA
DSP56366 Advance Information
2-55
Specifications Serial Host Interface (SHI) I2C Protocol Timing
Table 2-20 SHI I2C Protocol Timing (Continued)
No. Characteristics1,2,3 HREQ in assertion to first SCL edge 188 Filters bypassed Narrow filters enabled Wide filters enabled 189 Notes: First SCL edge to HREQ in not asserted (HREQ in hold time) 1. 2. 3. 4. 5. tHO;RQI Symbol/ Expression Standard Mode4 Min Max Fast Mode5 Min Max Unit
TAS;RQI 0.5 x TI2CCP 0.5 x TC - 21
4440 4373 4373 0.0
-- -- -- --
1041 999 958 0.0
-- -- -- --
ns
ns
VCC = 3.16 V 0.16 V; TJ = -40C to +105C Pull-up resistor: RP (min) = 1.5 kOhm Capacitive load: Cb (max) = 400 pF It is recommended to enable the wide filters when operating in the I2C Standard Mode. It is recommended to enable the narrow filters when operating in the I2C Fast Mode.
Programming the Serial Clock
The programmed serial clock cycle, T I2CCP , is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock control register). The expression for T I2CCP is T I2CCP = [TC x 2 x (HDM[7:0] + 1) x (7 x (1 - HRS) + 1)] where - - HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed. HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be selected.
In I2C mode, the user may select a value for the programmed serial clock cycle from 6 x TC to 4096 x TC (if HDM[7:0] = $FF and HRS = 0) (if HDM[7:0] = $02 and HRS = 1)
2-56
DSP56366 Advance Information
MOTOROLA
Specifications Serial Host Interface (SHI) I2C Protocol Timing
The programmed serial clock cycle (TI2CCP ), SCL rise time (TR), and the filters selected should be chosen in order to achieve the desired SCL serial clock cycle (TSCL), as shown in Table 2-21. Table 2-21 SCL Serial Clock Cycle (TSCL) generated as Master
Filters bypassed Narrow filters enabled Wide filters enabled
TI2CCP + 2.5 x TC + 45ns + TR TI2CCP + 2.5 x TC + 135ns + TR TI2CCP + 2.5 x TC + 223ns + TR
EXAMPLE: For DSP clock frequency of 120 MHz (i.e. TC = 8.33ns), operating in a standard mode I2C environment (FSCL = 100 kHz (i.e. TSCL = 10s), TR = 1000ns), with wide filters enabled: TI2CCP = 10s - 2.5x8.33ns - 223ns - 1000ns = 8756ns Choosing HRS = 0 gives HDM[7:0] = 8756ns / (2 x 8.33ns x 8) - 1 = 64.67 Thus the HDM[7:0] value should be programmed to $41 (=65). The resulting TI2CCP will be: T I2CCP = [TC x 2 x (HDM[7:0] + 1) x (7 x (1 - HRS) + 1)] T I2CCP = [8.33ns x 2 x (65 + 1) x (7 x (1 - 0) + 1)] T I2CCP = [8.33ns x 2 x 66 x 8] = 8796.48ns
MOTOROLA
DSP56366 Advance Information
2-57
Specifications Serial Host Interface (SHI) I2C Protocol Timing
171 173 SCL 177 172 SDA 179
Start MSB LSB ACK Stop
176
175
178
180
Stop
174 188 HREQ 189
186 184
182
183 187
AA0275
Figure 2-31 I2C Timing
2-58
DSP56366 Advance Information
MOTOROLA
Specifications Enhanced Serial Audio Interface Timing
ENHANCED SERIAL AUDIO INTERFACE TIMING
Table 2-22 Enhanced Serial Audio Interface Timing
No. Characteristics1, 2, 3 Symbol Expression 4 x TC 3 x TC TXC:max[3*tc; t454] Clock high period 431 * For internal clock -- 2 x TC - 10.0 1.5 x TC -- 2 x TC - 10.0 1.5 x TC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min 33.3 25.0 27.2 6.7 12.5 6.7 12.5 -- -- -- -- -- -- -- -- -- -- -- -- 0.0 19.0 5.0 3.0 23.0 1.0 1.0 23.0 3.0 0.0 0.0 19.0 6.0 0.0 -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- 37.0 22.0 37.0 22.0 39.0 24.0 39.0 24.0 36.0 21.0 37.0 22.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a x ck i ck s x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Condition4 i ck x ck x ck ns ns Unit
430 Clock cycle5
tSSICC
* For external clock
Clock low period 432 * For internal clock
* For external clock
433 RXC rising edge to FSR out (bl) high 434 RXC rising edge to FSR out (bl) low 435 RXC rising edge to FSR out (wr) high6 436 RXC rising edge to FSR out (wr) low6 437 RXC rising edge to FSR out (wl) high 438 RXC rising edge to FSR out (wl) low 439 Data in setup time before RXC (SCK in synchronous mode) falling edge 440 Data in hold time after RXC falling edge 441 FSR input (bl, wr) high before RXC falling edge 6 442 FSR input (wl) high before RXC falling edge 443 FSR input hold time after RXC falling edge 444 Flags input setup before RXC falling edge 445 Flags input hold time after RXC falling edge 446 TXC rising edge to FST out (bl) high 447 TXC rising edge to FST out (bl) low 448 TXC rising edge to FST out (wr) high6 449 TXC rising edge to FST out (wr) low6
--
-- -- -- -- --
MOTOROLA
DSP56366 Advance Information
2-59
Specifications Enhanced Serial Audio Interface Timing
Table 2-22 Enhanced Serial Audio Interface Timing (Continued)
No. Characteristics1, 2, 3 Symbol -- -- -- -- -- -- -- -- Expression -- -- -- -- 23 + 0.5 x TC 21.0 -- -- -- -- -- -- -- -- -- -- -- Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.0 21.0 -- -- 2.0 21.0 4.0 0.0 -- -- 40.0 -- -- Max 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 27.2 21.0 31.0 16.0 34.0 20.0 -- -- 27.0 31.0 -- -- -- -- 32.0 18.0 -- 27.5 27.5 Condition4 x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck -- -- x ck i ck x ck i ck x ck i ck Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
450 TXC rising edge to FST out (wl) high 451 TXC rising edge to FST out (wl) low 452 TXC rising edge to data out enable from high impedance 453 TXC rising edge to transmitter #0 drive enable assertion 454 TXC rising edge to data out valid 455 TXC rising edge to data out high impedance7 456 TXC rising7edge to transmitter #0 drive enable deassertion 457 FST input (bl, wr) setup time before TXC falling edge6 458 FST input (wl) to data out enable from high impedance 459 FST input (wl) to transmitter #0 drive enable assertion 460 FST input (wl) setup time before TXC falling edge 461 FST input hold time after TXC falling edge 462 Flag output valid after TXC rising edge 463 HCKR/HCKT clock cycle 464 HCKT input rising edge to TXC output 465 HCKR input rising edge to RXC output
--
-- -- -- -- -- -- --
2-60
DSP56366 Advance Information
MOTOROLA
Specifications Enhanced Serial Audio Interface Timing
Table 2-22 Enhanced Serial Audio Interface Timing (Continued)
No. Notes: 1. 2. Characteristics1, 2, 3 Symbol Expression Min Max Condition4 Unit
3.
4.
5. 6.
7.
VCC = 3.16 V 0.16 V; TJ = -40C to +105C, CL = 50 pF i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that TXC and RXC are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that TXC and RXC are the same clock) bl = bit length wl = word length wr = word length relative TXC(SCKT pin) = transmit clock RXC(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. Periodically sampled and not 100% tested
MOTOROLA
DSP56366 Advance Information
2-61
Specifications Enhanced Serial Audio Interface Timing
430 TXC (Input/Output) 431 432
446 FST (Bit) Out
447
450 FST (Word) Out 454 452 Data Out 459 Transmitter #0 Drive Enable 457 461 FST (Bit) In 458 FST (Word) In 460 461 453 456
First Bit Last Bit
451
454 455
Flags Out
462
See Note
Note:
In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period.
AA0490
Figure 2-32 ESAI Transmitter Timing
2-62
DSP56366 Advance Information
MOTOROLA
Specifications Enhanced Serial Audio Interface Timing 430 431 RXC (Input/Output) 433 FSR (Bit) Out 437 FSR (Word) Out 439 Data In 441 FSR (Bit) In 442 FSR (Word) In 444 Flags In
AA0491
432 434
438
440 First Bit Last Bit
443
443
445
Figure 2-33 ESAI Receiver Timing
MOTOROLA
DSP56366 Advance Information
2-63
Specifications Enhanced Serial Audio Interface Timing
HCKT 463
SCKT(output)
464
Figure 2-34 ESAI HCKT Timing
HCKR 463
SCKR (output)
465
Figure 2-35 ESAI HCKR Timing
2-64
DSP56366 Advance Information
MOTOROLA
Specifications Digital Audio Transmitter Timing
DIGITAL AUDIO TRANSMITTER TIMING
Table 2-23 Digital Audio Transmitter Timing
120 MHz No. Characteristic Expression Min
ACI frequency (see note) 220 221 222 223 Note: ACI period ACI high duration ACI low duration ACI rising edge to ADO valid 1 / (2 x TC) 2 x TC 0.5 x TC 0.5 x TC 1.5 x TC -- 16.7 4.2 4.2 --
Unit Max
60 -- -- -- 12.5 MHz ns ns ns ns
In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the DSP56366 internal clock frequency. For example, if the DSP56366 is running at 120 MHz internally, the ACI frequency should be less than 60 MHz.
ACI 220 223 ADO
AA1280
221
222
Figure 2-36 Digital Audio Transmitter Timing
MOTOROLA
DSP56366 Advance Information
2-65
Specifications Timer Timing
TIMER TIMING
Table 2-24 Timer Timing
No.
480 TIO Low 481 TIO High Note:
Characteristics
Expression
2 x TC + 2.0 2 x TC + 2.0
120 MHz Min Max
18.7 18.7 -- --
Unit
ns ns
VCC = 3.3 V 0.16 V; TJ = -40C to +105C, CL = 50 pF
TIO 480 481
AA0492
Figure 2-37 TIO Timer Event Input Restrictions
2-66
DSP56366 Advance Information
MOTOROLA
Specifications GPIO Timing
GPIO TIMING
Table 2-25 GPIO Timing
No. 4902 491 492 493 4942 495 496 Notes: Characteristics1 EXTAL edge to GPIO out valid (GPIO out delay time) EXTAL edge to GPIO out not valid (GPIO out hold time) GPIO In valid to EXTAL edge (GPIO in set-up time) EXTAL edge to GPIO in not valid (GPIO in hold time) Fetch to EXTAL edge before GPIO change GPIO out rise time GPIO out fall time 1. 2. VCC = 3.3 V 0.16 V; TJ = -40C to +105C, CL = 50 pF Valid only when PLL enabled with multiplication factor equal to one. 6.75 x TC-1.8 -- -- Expression Min -- 4.8 10.2 1.8 54.5 -- -- Max 32.8 -- -- -- -- 13 13 Unit ns ns ns ns ns ns ns
EXTAL (Input)
490 491
GPIO (Output) 492 GPIO (Input) A0-A17 494 Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register.
GPIO (Output) 495 496
493 Valid
Figure 2-38 GPIO Timing
MOTOROLA
DSP56366 Advance Information
2-67
Specifications JTAG Timing
JTAG TIMING
Table 2-26 JTAG Timing
All frequencies No. 500 501 502 503 504 505 506 507 508 509 510 511 Notes: Characteristics Min TCK frequency of operation (1/(TC x 3); maximum 22 MHz) TCK cycle time in Crystal mode TCK clock pulse width measured at 1.5 V TCK rise and fall times Boundary scan input data setup time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance 1. 2. 0.0 45.0 20.0 0.0 5.0 24.0 0.0 0.0 5.0 25.0 0.0 0.0 Max 22.0 -- -- 3.0 -- -- 40.0 40.0 -- -- 44.0 44.0 MHz ns ns ns ns ns ns ns ns ns ns ns Unit
VCC = 3.3 V 0.16 V; TJ = -40C to +105C, CL = 50 pF All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
501 502 TCK (Input)
VIH VM VIL
502
VM
503
503
AA0496
Figure 2-39 Test Clock Input Timing Diagram
2-68
DSP56366 Advance Information
MOTOROLA
Specifications JTAG Timing
TCK (Input) Data Inputs
VIL 504
VIH 505
Input Data Valid 506
Data Outputs 507 Data Outputs 506 Data Outputs
Output Data Valid
Output Data Valid
AA0497
Figure 2-40 Boundary Scan (JTAG) Timing Diagram
TCK (Input) TDI TMS (Input)
VIL 508
VIH 509
Input Data Valid 510
TDO (Output) 511 TDO (Output) 510 TDO (Output)
Output Data Valid
Output Data Valid
AA0498
Figure 2-41 Test Access Port Timing Diagram
MOTOROLA
DSP56366 Advance Information
2-69
Specifications JTAG Timing
2-70
DSP56366 Advance Information
MOTOROLA
SECTION 3 PACKAGING
PIN-OUT AND PACKAGE INFORMATION
This section provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated for the package. The DSP56366 is available in a 144-pin LQFP package. Table 3-1 and Table 3-2 show the pin/name assignments for the packages.
LQFP Package Description
Top view of the 144-pin LQFP package is shown in Figure 3-1 with its pin-outs. The package drawing is shown in Figure 3-2.
MOTOROLA
DSP56366 Advance Information
3-1
Packaging Pin-out and Package Information
SCK/SCL SS#/HA2 HREQ# SDO0/SDO0_1 SDO1/SDO1_1 SDO2/SDI3/SDO2_1/SDI3_1 SDO3/SDI2/SDO3_1/SDI2_1 VCCS GNDS SDO4/SDI1 SDO5/SDI0 FST FSR SCKT SCKR HCKT HCKR VCCQL GNDQ VCCQH HDS/HWR HRW/HRD HACK/HRRQ HOREQ/HTRQ VCCS GNDS ADO ACI TIO0 HCS/HA10 HA9/HA2 HA8/HA1 HAS/HA0 HAD7 HAD6 HAD5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 38 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
MISO/SDA MOSI/HA0 TMS TCK TDI TDO SDO4_1/SDI1_1 MODA/IRQA# MODB/IRQB# MODCIRQC# MODD/IRQD# D23 D22 D21 GNDD VCCD D20 GNDQ VCCQL D19 D18 D17 D16 D15 GNDD VCCD D14 D13 D12 D11 D10 D9 GNDD VCCD D8 D7
D6 D5 D4 D3 GNDD VCCD D2 D1 D0 A17 A16 A15 GNDA VCCQH A14 A13 A12 VCCQL GNDQ A11 A10 GNDA VCCA A9 A8 A7 A6 GNDA VCCA A5 A4 A3 A2 GNDA VCCA A1
3-2
HAD4 VCCH GNDH HAD3 HAD2 HAD1 HAD0 RESET# VCCP PCAP GNDP SDO5_1/SDI0_1 VCCQH FST_1 AA2 CAS# SCKT_1 GNDQ EXTAL VCCQL VCCC GNDC FSR_1 SCKR_1 PINIT/NMI# TA# BR# BB# VCCC GNDC WR# RD# AA1 AA0 BG# A0
Figure 3-1 144-pin package
DSP56366 Advance Information
MOTOROLA
Packaging Pin-out and Package Information
Table 3-1 Signal Identification by Name
Signal Name
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 AA0 AA1 AA2 ACI ADO BB# BG# BR# CAS# D0 D1 D2 D3 D4 D5 D6 D7 D8
Pin No.
72 73 76 77 78 79 82 83 84 85 88 89 92 93 94 97 98 99 70 69 51 28 27 64 71 63 52 100 101 102 105 106 107 108 109 110 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23
Signal Name
Pin No.
113 114 115 116 117 118 121 122 123 124 125 128 131 132 133 55 13 59 12 50 75 81 87 96 58 66 104 112 120 130 39 47 19 54 90 127 GNDS GNDS
Signal Name
Pin No.
9 26 32 31 23 43 42 41 40 37 36 35 34 33 17 16 30 21 24 3 22 137 136 135 134 144 143 46 61 68 44 1 15 60 14 53
Signal Name
SDO0/SDO0_1 SDO1/SDO1_1 SDO2/SDI3/SDO2_1/SDI3_1 SDO3/SDI2/SDO3_1/SDI2_1 SDO4/SDI1 SDO4_1/SDI1_1 SDO5/SDI0 SDO5_1/SDI0_1 SS#/HA2 TA# TCK TDI TDO TIO0 TMS VCCA VCCA VCCA VCCC VCCC VCCD VCCD VCCD VCCD VCCH VCCQH VCCQH VCCQH VCCQL VCCQL VCCQL VCCQL VCCP VCCS VCCS WR#
Pin No.
4 5 6 7 10 138 11 48 2 62 141 140 139 29 142 74 80 86 57 65 103 111 119 129 38 20 95 49 18 56 91 126 45 8 25 67
HA8/HA1 HA9/HA2 HACK/HRRQ HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAS/HA0 HCKR HCKT HCS/HA10 HDS/HWR HOREQ/HTRQ HREQ# HRW/HRD MODA/IRQA# MODB/IRQB# MODC/IRQC# MODD/IRQD# MISO/SDA MOSI/HA0 PCAP PINIT/NMI# RD# RESET# SCK/SCL SCKR SCKR_1 SCKT SCKT_1
EXTAL FSR FSR_1 FST FST_1 GNDA GNDA GNDA GNDA GNDC GNDC GNDD GNDD GNDD GNDD GNDH GNDP GNDQ GNDQ GNDQ GNDQ
Table 3-2
Pin No.
1 2 3 4
Signal Identification by Pin Number
Signal Name Pin No.
73 74 75 76 A1 VCCA GNDA A2
Signal Name
SCK/SCL SS#/HA2 HREQ# SDO0/SDO0_1
Pin No.
37 38 39 40
Signal Name
Pin No.
109 110 111 112 D7 D8
Signal Name
HAD4 VCCH GNDH HAD3
VCCD GNDD
MOTOROLA
DSP56366 Advance Information
3-3
Packaging Pin-out and Package Information
Table 3-2
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 SDO1/SDO1_1 SDO2/SDI3/SDO2_1/ SDI3_1 SDO3/SDI2/SDO3_1/ SDI2_1 VCCS GNDS SDO4/SDI1 SDO5/SDI0 FST FSR SCKT SCKR HCKT HCKR VCCQL GNDQ VCCQH HDS/HWR HRW/HRD HACK/HRRQ HOREQ/HTRQ VCCS GNDS ADO ACI TIO0 HCS/HA10 HA9/HA2 HA8/HA1 HAS/HA0 HAD7 HAD6 HAD5 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Signal Identification by Pin Number (Continued)
HAD2 HAD1 HAD0 RESET# VCCP PCAP GNDP SDO5_1/SDI0_1 VCCQH FST_1 AA2 CAS# SCKT_1 GNDQ EXTAL VCCQL VCCC GNDC FSR_1 SCKR_1 PINIT/NMI# TA# BR# BB# VCCC GNDC WR# RD# AA1 AA0 BG# A0 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A3 A4 A5 VCCA GNDA A6 A7 A8 A9 VCCA GNDA A10 A11 GNDQ VCCQL A12 A13 A14 VCCQH GNDA A15 A16 A17 D0 D1 D2 VCCD GNDD D3 D4 D5 D6 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 D9 D10 D11 D12 D13 D14 VCCD GNDD D15 D16 D17 D18 D19 VCCQL GNDQ D20 VCCD GNDD D21 D22 D23 MODD/IRQD# MODC/IRQC# MODB/IRQB# MODA/IRQA# SDO4_1/SDI1_1 TDO TDI TCK TMS MOSI/HA0 MISO/SDA
3-4
DSP56366 Advance Information
MOTOROLA
Packaging Pin-out and Package Information
LQFP Package Mechanical Drawing
Figure 3-2 DSP56366 144-pin LQFP Package
MOTOROLA
DSP56366 Advance Information
3-5
Packaging Ordering Drawings
ORDERING DRAWINGS
The detailed package drawing is available on the Motorola web page at: http://www.mot-sps.com/cgi-bin/cases.pl Use package 918-03 for the search.
3-6
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MOTOROLA
SECTION 4 DESIGN CONSIDERATIONS
THERMAL DESIGN CONSIDERATIONS
An estimation of the chip junction temperature, TJ, in C can be obtained from the following equation:
T J = T A + ( P D x R JA )
Where:
TA = ambient temperature C RqJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package W
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance.
R JA = R JC + R CA
Where:
RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W
RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages. * To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink.
DSP56366 Advance Information 4-1
MOTOROLA
Design Considerations Electrical Design Considerations
* *
To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ - TT)/PD.
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, thermal characterization parameter or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
ELECTRICAL DESIGN CONSIDERATIONS
CAUTION
This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). The suggested value for a pullup or pulldown resistor is 10 kOhm.
Use the following list of recommendations to assure correct DSP operation: * * * * Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the board ground to each GND pin. Use at least six 0.01-0.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 1.2 cm (0.5 inch) per capacitor lead. Use at least a four-layer PCB with two inner layers for VCC and GND.
4-2
DSP56366 Advance Information
MOTOROLA
Design Considerations Power Consumption Considerations
*
Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQC, IRQD, TA and BG pins. Maximum PCB trace lengths on the order of 15 cm (6 inches) are recommended. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for the three pins with internal pull-up resistors (TMS, TDI, TCK). Take special care to minimize noise levels on the VCCP and GNDP pins. If multiple DSP56366 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. RESET must be asserted when the chip is powered up. A stable EXTAL signal must be supplied while RESET is being asserted. At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip VCC never exceeds 3.95 V.
*
* * * * *
POWER CONSUMPTION CONSIDERATIONS
Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by the following formula:
I = CxVxf
where
C = node/pin capacitance V = voltage swing f = frequency of node/pin toggle
Example 1 Current Consumption
For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 120 MHz clock, toggling at its maximum possible rate (60 MHz), the current consumption is I = 50 x 10
- 12
x 3.3 x 60 x 10 = 9.9mA
6
MOTOROLA
DSP56366 Advance Information
4-3
Design Considerations PLL Performance Issues
The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. The typical internal current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. For applications that require very low current consumption, do the following: * * * * * * Set the EBD bit when not accessing external memory. Minimize external memory accesses and use internal memory accesses. Minimize the number of pins that are switching. Minimize the capacitive load on the pins. Connect the unused inputs to pull-up or pull-down resistors. Disable unused peripherals.
One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current measurements, and the following equation to derive the current per MIPS value.
I MIPS = I MHz = ( I typF2 - I typF1 ) ( F2 - F1 )
where :
ItypF2 ItypF1 F2 F1
= = = =
current at F2 current at F1 high frequency (any specified operating frequency) low frequency (any specified operating frequency lower than F2)
Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application.
PLL PERFORMANCE ISSUES
The following explanations should be considered as general observations on expected PLL behavior. There is no testing that verifies these exact numbers. These observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges.
Phase Jitter Performance
The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and the internal DSP clock for a given device in specific temperature, voltage, input frequency and MF. These variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz
4-4
DSP56366 Advance Information
MOTOROLA
Design Considerations Host Port Considerations
and MF 4, this jitter is less than 0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than 2 ns.
Frequency Jitter Performance
The frequency jitter of the PLL is defined as the variation of the frequency of the internal DSP clock. For small MF (MF < 10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) this jitter is between 0.5% and approximately 2%. For large MF (MF > 500), the frequency jitter is 2-3%.
Input (EXTAL) Jitter Requirements
The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be 2%. The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values.
HOST PORT CONSIDERATIONS
Careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. This synchronization is a common problem when two asynchronous systems are connected, as they are in the host interface. The following paragraphs present considerations for proper operation.
Host Programming Considerations
* Unsynchronized Reading of Receive Byte Registers--When reading the receive byte registers, receive register high (RXH), receive register middle (RXM), or receive register low (RXL), the host interface programmer should use interrupts or poll the receive register data full (RXDF) flag that indicates whether data is available. This ensures that the data in the receive byte registers will be valid. Overwriting Transmit Byte Registers--The host interface programmer should not write to the transmit byte registers, transmit register high (TXH), transmit register middle (TXM), or transmit register low (TXL), unless the transmit register data empty (TXDE) bit is set, indicating that the transmit byte registers are empty. This ensures that the transmit byte registers will transfer valid data to the host receive (HRX) register. Synchronization of Status Bits from DSP to Host--HC, HOREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared from inside the DSP and read by the host processor (refer to the user's manual for descriptions of these status bits). The host can read these status bits
*
*
MOTOROLA
DSP56366 Advance Information
4-5
Design Considerations Host Port Considerations
very quickly without regard to the clock rate used by the DSP, but the state of the bit could be changing during the read operation. This is not generally a system problem, because the bit will be read correctly in the next pass of any host polling routine. However, if the host asserts HEN for more than timing number 31, with a minimum cycle time of timing number 31 + 32, then these status bits are guaranteed to be stable. Exercise care when reading status bits HF3 and HF2 as an encoded pair. If the DSP changes HF3 and HF2 from 00 to 11, there is a small probability that the host could read the bits during the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has significance, the host could read the wrong combination. Therefore, read the bits twice and check for consensus. * Overwriting the Host Vector--The host interface programmer should change the host vector (HV) register only when the host command (HC) bit is clear. This ensures that the DSP interrupt control logic will receive a stable vector. Cancelling a Pending Host Command Exception--The host processor may elect to clear the HC bit to cancel the host command exception request at any time before it is recognized by the DSP. Because the host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline delays), the DSP may execute the host command exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the same time that the HC bit is cleared. Variance in the Host Interface Timing--The host interface (HDI) may vary (e.g. due to the PLL lock time at reset). Therefore, a host which attempts to load (bootstrap) the DSP should first make sure that the part has completed its HI port programming (e.g., by setting the INIT bit in ICR then polling it and waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ together with the INIT and then polling INIT, ISR, and the HOREQ pin).
*
*
DSP Programming Considerations
* Synchronization of Status Bits from Host to DSP--DMA, HF1, HF0, HCP, HTDE, and HRDF status bits are set or cleared by the host processor side of the interface. These bits are individually synchronized to the DSP clock. (Refer to the user's manual for descriptions of these status bits.) Reading HF0 and HF1 as an Encoded Pair--Care must be exercised when reading status bits HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have significance). A very small probability exists that the DSP will read the status bits synchronized during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus.
*
4-6
DSP56366 Advance Information
MOTOROLA
SECTION 5 ORDERING INFORMATION
Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and to place an order. Table 5-1 Ordering Information
Part DSP56366 Notes: 1. 2. Supply Voltage 3.3 V Package Type Thin quad flat pack (TQFP) Pin Count 144 Frequency (MHz) 120 Order Number XCD56366PV120
Please consult the web site at www.dspaudio.motorola.com for current availability. Future products in the DSP56366 family may include other ROM-based options. For additional information on future part development, or to request customer-specific ROM-based support, call your local Motorola Semiconductor sales office or authorized distributor.
MOTOROLA
DSP56366 Advance Information
5-1
Ordering Information
5-2
DSP56366 Advance Information
MOTOROLA
APPENDIX A POWER CONSUMPTION BENCHMARK
The following benchmark program permits evaluation of DSP power usage in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate instructions with a set of synthetic DSP application data to emulate intensive sustained DSP operation.
;******************************************************************** ;******************************************************************** ;* ;* CHECKS Typical Power Consumption
;******************************************************************** page 200,55,0,0,0 nolist I_VEC EQU START EQU INT_PROG INT_XDAT INT_YDAT $000000 $8000 EQU $100 EQU $0 EQU $0 ; ; ; ; ; Interrupt vectors for program debug only MAIN (external) program starting address INTERNAL program memory starting address INTERNAL X-data memory starting address INTERNAL Y-data memory starting address
INCLUDE "ioequ.asm" INCLUDE "intequ.asm" list org ; movep #$0123FF,x:M_BCR; BCR: Area 3 : 1 w.s (SRAM) ; Default: 1 w.s (SRAM) ; movep #$0d0000,x:M_PCTL ; XTAL disable ; PLL enable ; CLKOUT disable ; ; Load the program ; move #INT_PROG,r0 move #PROG_START,r1 do #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ nop PLOAD_LOOP ; ; Load the X-data ; P:START
MOTOROLA
DSP56366 Advance Information
A-1
Power Consumption Benchmark
move move do move move XLOAD_LOOP ; ; Load the Y-data ; move move do move move YLOAD_LOOP ; jmp PROG_START move move move move ; clr clr move move move move bset ; sbr dor mac mac add mac mac move _end bra nop nop nop nop PROG_END nop nop
#INT_XDAT,r0 #XDAT_START,r1 #(XDAT_END-XDAT_START),XLOAD_LOOP p:(r1)+,x0 x0,x:(r0)+
#INT_YDAT,r0 #YDAT_START,r1 #(YDAT_END-YDAT_START),YLOAD_LOOP p:(r1)+,x0 x0,y:(r0)+
INT_PROG
#$0,r0 #$0,r4 #$3f,m0 #$3f,m4 a b #$0,x0 #$0,x1 #$0,y0 #$0,y1 #4,omr
; ebd
#60,_end x0,y0,a x:(r0)+,x1 x1,y1,a x:(r0)+,x0 a,b x0,y0,a x:(r0)+,x1 x1,y1,a b1,x:$ff sbr
y:(r4)+,y1 y:(r4)+,y0
y:(r4)+,y0
XDAT_START ; org
x:0
A-2
DSP56366 Advance Information
MOTOROLA
Power Consumption Benchmark
dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc
$262EB9 $86F2FE $E56A5F $616CAC $8FFD75 $9210A $A06D7B $CEA798 $8DFBF1 $A063D6 $6C6657 $C2A544 $A3662D $A4E762 $84F0F3 $E6F1B0 $B3829 $8BF7AE $63A94F $EF78DC $242DE5 $A3E0BA $EBAB6B $8726C8 $CA361 $2F6E86 $A57347 $4BE774 $8F349D $A1ED12 $4BFCE3 $EA26E0 $CD7D99 $4BA85E $27A43F $A8B10C $D3A55 $25EC6A $2A255B $A5F1F8 $2426D1 $AE6536 $CBBC37 $6235A4 $37F0D $63BEC2 $A5E4D3 $8CE810 $3FF09 $60E50E $CFFB2F $40753C $8262C5
MOTOROLA
DSP56366 Advance Information
A-3
Power Consumption Benchmark
dc dc dc dc dc dc dc dc dc dc dc XDAT_END YDAT_START ; org dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc
$CA641A $EB3B4B $2DA928 $AB6641 $28A7E6 $4E2127 $482FD4 $7257D $E53C72 $1A8C3 $E27540
y:0 $5B6DA $C3F70B $6A39E8 $81E801 $C666A6 $46F8E7 $AAEC94 $24233D $802732 $2E3C83 $A43E00 $C2B639 $85A47E $ABFDDF $F3A2C $2D7CF5 $E16A8A $ECB8FB $4BED18 $43F371 $83A556 $E1E9D7 $ACA2C4 $8135AD $2CE0E2 $8F2C73 $432730 $A87FA9 $4A292E $A63CCF $6BA65C $E06D65 $1AA3A $A1B6EB $48AC48 $EF7AE1 $6E3006 $62F6C7
A-4
DSP56366 Advance Information
MOTOROLA
Power Consumption Benchmark
dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc YDAT_END
$6064F4 $87E41D $CB2692 $2C3863 $C6BC60 $43A519 $6139DE $ADF7BF $4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF $6162BC $E4A245
MOTOROLA
DSP56366 Advance Information
A-5
Power Consumption Benchmark
A-6
DSP56366 Advance Information
MOTOROLA
APPENDIX B IBIS MODEL
[IBIS ver] 2.1 [File name] 56366.ibs [File Rev] 0.0 [Date] 29/6/2000 [Component] 56366 [Manufacturer] Motorola [Package] |variable typ R_pkg 45m L_pkg 2.5nH C_pkg 1.3pF
min 22m 1.1nH 1.2pF
max 75m 4.3nH 1.4pF
[Pin]signal_name model_name 1 sck ip5b_io 2 ss_ ip5b_io 3 hreq_ ip5b_io 4 sdo0 ip5b_io 5 sdo1 ip5b_io 6 sdoi23 ip5b_io 7 sdoi32 ip5b_io 8 svcc power 9 sgnd gnd 10 sdoi41 ip5b_io 11 sdoi50 ip5b_io 12 fst ip5b_io 13 fsr ip5b_io 14 sckt ip5b_io 15 sckr ip5b_io 16 hsckt ip5b_io 17 hsckr ip5b_io 18 qvccl power 19 gnd gnd 20 qvcch power 21 hp12 ip5b_io 22 hp11 ip5b_io 23 hp15 ip5b_io 24 hp14 ip5b_io 25 svcc power 26 sgnd gnd 27 ado ip5b_io 28 aci ip5b_io 29 tio ip5b_io 30 hp13 ip5b_io 31 hp10 ip5b_io
MOTOROLA
DSP56366 Advance Information
B-1
IBIS Model
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
hp9 hp8 hp7 hp6 hp5 hp4 svcc sgnd hp3 hp2 hp1 hp0 ires_ pvcc pcap pgnd sdo5 qvcch fst_1 aa2 cas_ sck_1 qgnd cxtldis_ qvccl cvcc cgnd fsr_1 sckr1 nmi_ ta_ br_ bb_ cvcc cgnd wr_ rd_ aa1 aa0 bg_ eab0 eab1 avcc agnd eab2 eab3 eab4 eab5 avcc agnd eab6 eab7 eab8
ip5b_io ip5b_io ip5b_io ip5b_io ip5b_io ip5b_io power gnd ip5b_io ip5b_io ip5b_io ip5b_io ip5b_i power power gnd ipbw_io power ipbw_io icbc_o icbc_o ipbw_io gnd iexlh_i power power gnd ipbw_io ipbw_io ipbw_i icbc_o icbc_o icbc_o power gnd icbc_o icbc_o icbc_o icbc_o icbc_o icba_o icba_o power gnd icba_o icba_o icba_o icba_o power gnd icba_o icba_o icba_o
B-2
DSP56366 Advance Information
MOTOROLA
IBIS Model
85 eab9 86 avcc 87 agnd 88 eab10 89 eab11 90 qgnd 91 qvcc 92 eab12 93 eab13 94 eab14 95 qvcch 96 agnd 97 eab15 98 eab16 99 eab17 100 edb0 101 edb1 102 edb2 103 dvcc 104 dgnd 105 edb3 106 edb4 107 edb5 108 edb6 109 edb7 110 edb8 111 dvcc 112 dgnd 113 edb9 114 edb10 115 edb11 116 edb12 117 edb13 118 edb14 119 dvcc 120 dgnd 121 edb15 122 edb16 123 edb17 124 edb18 125 edb19 126 qvccl 127 qgnd 128 edb20 129 dvcc 130 dgnd 131 edb21 132 edb22 133 edb23 134 irqd_ 135 irqc_ 136 irqb_ 137 irqa_
icba_o power gnd icba_o icba_o gnd power icba_o icba_o icba_o power gnd icba_o icba_o icba_o icba_io icba_io icba_io power gnd icba_io icba_io icba_io icba_io icba_io icba_io power gnd icba_io icba_io icba_io icba_io icba_io icba_io power gnd icba_io icba_io icba_io icba_io icba_io power gnd icba_io power gnd icba_io icba_io icba_io ip5b_i ip5b_i ip5b_i ip5b_i
MOTOROLA
DSP56366 Advance Information
B-3
IBIS Model
138 sdo4_1 ip5b_io 139 tdo ip5b_o 140 tdi ip5b_i 141 tck ip5b_i 142 tms ip5b_i 143 mosi ip5b_io 144 sda ip5b_io | [Model] ip5b_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | | [Model] ip5b_io Model_type I/O Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02
B-4
DSP56366 Advance Information
MOTOROLA
IBIS Model
-3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage
-4.69e+02 -4.18e+02 -3.67e+02 -3.16e+02 -2.65e+02 -2.14e+02 -1.63e+02 -1.13e+02 -7.83e+01 -4.43e+01 -1.02e+01 -5.10e-02 -3.65e-02 -2.65e-02 -1.62e-02 -5.49e-03 5.377e-03 1.516e-02 2.370e-02 3.098e-02 3.700e-02 4.175e-02 4.531e-02 4.779e-02 4.935e-02 5.013e-02 5.046e-02 5.063e-02 5.075e-02 5.085e-02 5.090e-02 4.771e-02 4.525e-02 4.657e-02 4.904e-02 5.221e-02 5.524e-02 5.634e-02 5.751e-02 5.634e-02 5.648e-02 5.664e-02 5.679e-02 5.693e-02 5.707e-02 5.722e-02 5.741e-02 5.766e-02 5.801e-02 5.824e-02
-3.30e+02 -2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.52e+01 -2.15e+01 -1.18e+00 -2.25e-02 -1.38e-02 -8.35e-03 -2.80e-03 2.744e-03 7.871e-03 1.252e-02 1.667e-02 2.026e-02 2.324e-02 2.553e-02 2.709e-02 2.803e-02 2.851e-02 2.876e-02 2.892e-02 2.904e-02 2.912e-02 2.876e-02 2.994e-02 3.321e-02 3.570e-02 3.801e-02 4.029e-02 4.253e-02 4.463e-02 4.645e-02 4.786e-02 4.881e-02 4.912e-02 4.795e-02 4.679e-02 4.688e-02 4.700e-02 4.712e-02 4.723e-02 4.733e-02 4.737e-02
-4.67e+02 -4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02 -2.12e+02 -1.61e+02 -1.10e+02 -7.58e+01 -4.17e+01 -7.69e+00 -5.63e-02 -4.28e-02 -3.12e-02 -1.91e-02 -6.52e-03 6.427e-03 1.823e-02 2.869e-02 3.776e-02 4.544e-02 5.171e-02 5.660e-02 6.023e-02 6.271e-02 6.419e-02 6.494e-02 6.525e-02 6.540e-02 6.549e-02 6.555e-02 6.561e-02 6.182e-02 6.049e-02 6.178e-02 6.450e-02 6.659e-02 6.867e-02 6.970e-02 6.938e-02 6.960e-02 6.983e-02 7.005e-02 7.026e-02 7.049e-02 7.074e-02 7.105e-02 7.147e-02 7.205e-02 7.242e-02
I(typ)
I(min)
I(max)
MOTOROLA
DSP56366 Advance Information
B-5
IBIS Model
| -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 |
2.922e-04 2.881e-04 2.853e-04 2.836e-04 2.825e-04 2.819e-04 2.815e-04 2.813e-04 2.812e-04 2.811e-04 2.810e-04 2.809e-04 2.808e-04 2.997e-04 1.750e-02 1.048e-02 3.487e-03 -3.40e-03 -9.69e-03 -1.52e-02 -2.02e-02 -2.46e-02 -2.84e-02 -3.14e-02 -3.37e-02 -3.55e-02 -3.68e-02 -3.78e-02 -3.85e-02 -3.91e-02 -3.96e-02 -4.01e-02 -4.04e-02 -4.08e-02 -4.11e-02 -4.14e-02 -4.17e-02 -4.32e-02 -4.08e-01 -2.73e+01 -6.13e+01 -9.54e+01 -1.38e+02 -1.89e+02 -2.40e+02 -2.91e+02 -3.42e+02 -3.93e+02 -4.44e+02 -4.95e+02 -5.21e+02
2.177e-04 2.175e-04 2.173e-04 2.172e-04 2.171e-04 2.170e-04 2.169e-04 2.167e-04 2.520e-04 3.078e-02 2.684e-02 2.277e-02 1.864e-02 1.447e-02 1.031e-02 6.181e-03 2.084e-03 -2.03e-03 -5.71e-03 -8.99e-03 -1.19e-02 -1.43e-02 -1.62e-02 -1.77e-02 -1.88e-02 -1.95e-02 -2.00e-02 -2.04e-02 -2.07e-02 -2.10e-02 -2.12e-02 -2.15e-02 -2.17e-02 -2.18e-02 -2.20e-02 -2.78e-02 -1.20e+00 -2.15e+01 -4.52e+01 -6.89e+01 -9.25e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.18e+02
4.123e-04 4.021e-04 3.946e-04 3.893e-04 3.857e-04 3.834e-04 3.820e-04 3.812e-04 3.808e-04 3.806e-04 3.804e-04 3.802e-04 3.801e-04 3.799e-04 3.797e-04 3.776e-04 4.568e-03 -4.22e-03 -1.24e-02 -1.95e-02 -2.61e-02 -3.21e-02 -3.73e-02 -4.18e-02 -4.55e-02 -4.85e-02 -5.09e-02 -5.27e-02 -5.41e-02 -5.51e-02 -5.60e-02 -5.67e-02 -5.74e-02 -5.79e-02 -5.84e-02 -5.89e-02 -5.94e-02 -5.98e-02 -6.10e-02 -6.84e-02 -7.73e+00 -4.18e+01 -7.59e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.41e+02
B-6
DSP56366 Advance Information
MOTOROLA
IBIS Model
[GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.030/0.465 0.605/0.676 1.320/0.366 | | dV/dt_f 1.290/0.671 0.829/0.122 1.520/0.431 | | [Model] ip5b_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01
MOTOROLA
DSP56366 Advance Information
B-7
IBIS Model
-1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00
-4.43e+01 -1.02e+01 -5.10e-02 -3.65e-02 -2.65e-02 -1.62e-02 -5.49e-03 5.377e-03 1.516e-02 2.370e-02 3.098e-02 3.700e-02 4.175e-02 4.531e-02 4.779e-02 4.935e-02 5.013e-02 5.046e-02 5.063e-02 5.075e-02 5.085e-02 5.090e-02 4.771e-02 4.525e-02 4.657e-02 4.904e-02 5.221e-02 5.524e-02 5.634e-02 5.751e-02 5.634e-02 5.648e-02 5.664e-02 5.679e-02 5.693e-02 5.707e-02 5.722e-02 5.741e-02 5.766e-02 5.801e-02 5.824e-02
-4.52e+01 -2.15e+01 -1.18e+00 -2.25e-02 -1.38e-02 -8.35e-03 -2.80e-03 2.744e-03 7.871e-03 1.252e-02 1.667e-02 2.026e-02 2.324e-02 2.553e-02 2.709e-02 2.803e-02 2.851e-02 2.876e-02 2.892e-02 2.904e-02 2.912e-02 2.876e-02 2.994e-02 3.321e-02 3.570e-02 3.801e-02 4.029e-02 4.253e-02 4.463e-02 4.645e-02 4.786e-02 4.881e-02 4.912e-02 4.795e-02 4.679e-02 4.688e-02 4.700e-02 4.712e-02 4.723e-02 4.733e-02 4.737e-02
-4.17e+01 -7.69e+00 -5.63e-02 -4.28e-02 -3.12e-02 -1.91e-02 -6.52e-03 6.427e-03 1.823e-02 2.869e-02 3.776e-02 4.544e-02 5.171e-02 5.660e-02 6.023e-02 6.271e-02 6.419e-02 6.494e-02 6.525e-02 6.540e-02 6.549e-02 6.555e-02 6.561e-02 6.182e-02 6.049e-02 6.178e-02 6.450e-02 6.659e-02 6.867e-02 6.970e-02 6.938e-02 6.960e-02 6.983e-02 7.005e-02 7.026e-02 7.049e-02 7.074e-02 7.105e-02 7.147e-02 7.205e-02 7.242e-02
I(typ) 2.922e-04 2.881e-04 2.853e-04 2.836e-04 2.825e-04 2.819e-04 2.815e-04 2.813e-04
I(min) 2.177e-04 2.175e-04 2.173e-04 2.172e-04 2.171e-04 2.170e-04 2.169e-04 2.167e-04
I(max) 4.123e-04 4.021e-04 3.946e-04 3.893e-04 3.857e-04 3.834e-04 3.820e-04 3.812e-04
B-8
DSP56366 Advance Information
MOTOROLA
IBIS Model
-1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [GND_clamp] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00
2.812e-04 2.811e-04 2.810e-04 2.809e-04 2.808e-04 2.997e-04 1.750e-02 1.048e-02 3.487e-03 -3.40e-03 -9.69e-03 -1.52e-02 -2.02e-02 -2.46e-02 -2.84e-02 -3.14e-02 -3.37e-02 -3.55e-02 -3.68e-02 -3.78e-02 -3.85e-02 -3.91e-02 -3.96e-02 -4.01e-02 -4.04e-02 -4.08e-02 -4.11e-02 -4.14e-02 -4.17e-02 -4.32e-02 -4.08e-01 -2.73e+01 -6.13e+01 -9.54e+01 -1.38e+02 -1.89e+02 -2.40e+02 -2.91e+02 -3.42e+02 -3.93e+02 -4.44e+02 -4.95e+02 -5.21e+02
2.520e-04 3.078e-02 2.684e-02 2.277e-02 1.864e-02 1.447e-02 1.031e-02 6.181e-03 2.084e-03 -2.03e-03 -5.71e-03 -8.99e-03 -1.19e-02 -1.43e-02 -1.62e-02 -1.77e-02 -1.88e-02 -1.95e-02 -2.00e-02 -2.04e-02 -2.07e-02 -2.10e-02 -2.12e-02 -2.15e-02 -2.17e-02 -2.18e-02 -2.20e-02 -2.78e-02 -1.20e+00 -2.15e+01 -4.52e+01 -6.89e+01 -9.25e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.18e+02
3.808e-04 3.806e-04 3.804e-04 3.802e-04 3.801e-04 3.799e-04 3.797e-04 3.776e-04 4.568e-03 -4.22e-03 -1.24e-02 -1.95e-02 -2.61e-02 -3.21e-02 -3.73e-02 -4.18e-02 -4.55e-02 -4.85e-02 -5.09e-02 -5.27e-02 -5.41e-02 -5.51e-02 -5.60e-02 -5.67e-02 -5.74e-02 -5.79e-02 -5.84e-02 -5.89e-02 -5.94e-02 -5.98e-02 -6.10e-02 -6.84e-02 -7.73e+00 -4.18e+01 -7.59e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.41e+02
I(typ) -5.21e+02 -4.69e+02 -4.18e+02 -3.67e+02 -3.16e+02 -2.65e+02
I(min) -3.65e+02 -3.30e+02 -2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02
I(max) -5.18e+02 -4.67e+02 -4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02
MOTOROLA
DSP56366 Advance Information
B-9
IBIS Model
-2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.030/0.465 0.605/0.676 1.320/0.366 | | dV/dt_f 1.290/0.671 0.829/0.122 1.520/0.431 | | [Model] icba_io Model_type I/O Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.68e+00 -9.00e-01 -2.70e-02 -1.19e+00 -2.90e-02 -7.00e-01 -1.32e-02 -1.25e-02 -1.63e-02 -5.00e-01 -9.33e-03 -4.69e-03 -1.10e-02 -3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03 -1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03
B-10
DSP56366 Advance Information
MOTOROLA
IBIS Model
1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01
1.945e-03 5.507e-03 8.649e-03 1.136e-02 1.364e-02 1.547e-02 1.688e-02 1.299e-01 1.366e-01 1.404e-01 1.423e-01 1.433e-01 1.440e-01 1.445e-01 1.450e-01 1.454e-01 1.458e-01 1.461e-01 1.464e-01 1.469e-01 1.490e-01 1.501e+00 1.813e+01 3.540e+01 5.269e+01 7.541e+01 1.012e+02 1.270e+02 1.527e+02 1.785e+02 2.043e+02 2.301e+02 2.559e+02 2.688e+02
9.285e-04 2.640e-03 4.168e-03 5.504e-03 6.636e-03 7.551e-03 8.240e-03 6.458e-02 6.746e-02 6.916e-02 7.006e-02 7.059e-02 7.098e-02 7.128e-02 7.154e-02 7.176e-02 7.196e-02 7.223e-02 8.810e-02 2.589e+00 1.451e+01 2.658e+01 3.866e+01 5.076e+01 6.461e+01 8.261e+01 1.006e+02 1.186e+02 1.366e+02 1.546e+02 1.726e+02 1.906e+02 2.086e+02 2.176e+02
2.307e-03 6.599e-03 1.048e-02 1.393e-02 1.693e-02 1.950e-02 2.162e-02 2.331e-02 1.755e-01 1.847e-01 1.907e-01 1.940e-01 1.958e-01 1.970e-01 1.979e-01 1.986e-01 1.993e-01 1.999e-01 2.004e-01 2.009e-01 2.015e-01 2.030e-01 2.385e-01 9.563e+00 2.682e+01 4.409e+01 6.258e+01 8.836e+01 1.141e+02 1.399e+02 1.657e+02 1.915e+02 2.173e+02 2.302e+02
I(typ) 2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 2.662e+01 9.360e+00 4.275e-02 8.208e-03 5.635e-03
I(min) 1.905e+02 1.725e+02 1.545e+02 1.365e+02 1.185e+02 1.005e+02 8.253e+01 6.454e+01 5.068e+01 3.859e+01 2.651e+01 1.444e+01 2.518e+00 2.012e-02 3.518e-03
I(max) 2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 2.662e+01 9.362e+00 4.663e-02 1.070e-02 7.068e-03
MOTOROLA
DSP56366 Advance Information
B-11
IBIS Model
-3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [GND_clamp] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01
3.370e-03 1.118e-03 -1.09e-03 -3.12e-03 -4.96e-03 -6.60e-03 -8.04e-03 -9.26e-03 -1.03e-02 -1.25e-01 -1.31e-01 -1.36e-01 -1.40e-01 -1.42e-01 -1.44e-01 -1.46e-01 -1.48e-01 -1.49e-01 -1.50e-01 -1.52e-01 -1.53e-01 -1.54e-01 -1.57e-01 -5.25e-01 -2.74e+01 -6.14e+01 -9.55e+01 -1.38e+02 -1.89e+02 -2.40e+02 -2.91e+02 -3.42e+02 -3.93e+02 -4.44e+02 -4.95e+02 -5.21e+02
2.053e-03 6.789e-04 -6.56e-04 -1.86e-03 -2.93e-03 -3.87e-03 -4.66e-03 -5.30e-03 -6.55e-02 -6.93e-02 -7.19e-02 -7.38e-02 -7.53e-02 -7.65e-02 -7.76e-02 -7.85e-02 -7.93e-02 -8.00e-02 -8.06e-02 -8.13e-02 -8.84e-02 -1.26e+00 -2.16e+01 -4.53e+01 -6.89e+01 -9.26e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.19e+02
4.233e-03 1.410e-03 -1.38e-03 -3.99e-03 -6.39e-03 -8.59e-03 -1.06e-02 -1.23e-02 -1.38e-02 -1.70e-01 -1.82e-01 -1.91e-01 -1.97e-01 -2.03e-01 -2.07e-01 -2.10e-01 -2.13e-01 -2.15e-01 -2.17e-01 -2.19e-01 -2.21e-01 -2.22e-01 -2.24e-01 -2.27e-01 -2.38e-01 -7.90e+00 -4.20e+01 -7.60e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.42e+02
I(typ) -5.20e+02 -4.69e+02 -4.18e+02 -3.67e+02 -3.16e+02 -2.65e+02 -2.14e+02 -1.63e+02 -1.13e+02 -7.83e+01 -4.43e+01 -1.02e+01 -1.22e-02
I(min) -3.65e+02 -3.30e+02 -2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.52e+01 -2.15e+01 -1.18e+00
I(max) -5.18e+02 -4.67e+02 -4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02 -2.12e+02 -1.60e+02 -1.10e+02 -7.58e+01 -4.17e+01 -7.67e+00 -1.17e-02
B-12
DSP56366 Advance Information
MOTOROLA
IBIS Model
-7.00e-01 -5.18e-04 -6.62e-03 -1.56e-03 -5.00e-01 -2.43e-06 -6.64e-05 -1.80e-05 -3.00e-01 -2.33e-09 -6.35e-07 -1.54e-08 -1.00e-01 -2.10e-11 -6.31e-09 -2.99e-11 0.000e+00 -1.70e-11 -1.95e-09 -1.91e-11 | [POWER_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.236e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.358e+00 1.444e+01 9.359e+00 -9.00e-01 3.399e-02 2.517e+00 3.554e-02 -7.00e-01 3.426e-04 1.577e-02 9.211e-04 -5.00e-01 2.840e-06 7.857e-05 1.655e-05 -3.00e-01 3.401e-09 6.836e-07 1.946e-08 -1.00e-01 6.162e-11 7.379e-09 7.622e-11 0.000e+00 5.758e-11 2.438e-09 6.240e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.680/0.164 1.360/0.329 1.900/0.124 | | dV/dt_f 1.690/0.219 1.310/0.442 1.880/0.155 | | [Model] icba_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02
MOTOROLA
DSP56366 Advance Information
B-13
IBIS Model
-2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00
-3.16e+02 -2.65e+02 -2.14e+02 -1.63e+02 -1.13e+02 -7.83e+01 -4.43e+01 -1.02e+01 -2.70e-02 -1.32e-02 -9.33e-03 -5.75e-03 -1.97e-03 1.945e-03 5.507e-03 8.649e-03 1.136e-02 1.364e-02 1.547e-02 1.688e-02 1.299e-01 1.366e-01 1.404e-01 1.423e-01 1.433e-01 1.440e-01 1.445e-01 1.450e-01 1.454e-01 1.458e-01 1.461e-01 1.464e-01 1.469e-01 1.490e-01 1.501e+00 1.813e+01 3.540e+01 5.269e+01 7.541e+01 1.012e+02 1.270e+02 1.527e+02 1.785e+02 2.043e+02 2.301e+02 2.559e+02 2.688e+02
-2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.52e+01 -2.15e+01 -1.19e+00 -1.25e-02 -4.69e-03 -2.81e-03 -9.48e-04 9.285e-04 2.640e-03 4.168e-03 5.504e-03 6.636e-03 7.551e-03 8.240e-03 6.458e-02 6.746e-02 6.916e-02 7.006e-02 7.059e-02 7.098e-02 7.128e-02 7.154e-02 7.176e-02 7.196e-02 7.223e-02 8.810e-02 2.589e+00 1.451e+01 2.658e+01 3.866e+01 5.076e+01 6.461e+01 8.261e+01 1.006e+02 1.186e+02 1.366e+02 1.546e+02 1.726e+02 1.906e+02 2.086e+02 2.176e+02
-3.14e+02 -2.63e+02 -2.12e+02 -1.60e+02 -1.10e+02 -7.58e+01 -4.17e+01 -7.68e+00 -2.90e-02 -1.63e-02 -1.10e-02 -6.76e-03 -2.32e-03 2.307e-03 6.599e-03 1.048e-02 1.393e-02 1.693e-02 1.950e-02 2.162e-02 2.331e-02 1.755e-01 1.847e-01 1.907e-01 1.940e-01 1.958e-01 1.970e-01 1.979e-01 1.986e-01 1.993e-01 1.999e-01 2.004e-01 2.009e-01 2.015e-01 2.030e-01 2.385e-01 9.563e+00 2.682e+01 4.409e+01 6.258e+01 8.836e+01 1.141e+02 1.399e+02 1.657e+02 1.915e+02 2.173e+02 2.302e+02
I(typ) 2.686e+02 2.428e+02
I(min) 1.905e+02 1.725e+02
I(max) 2.686e+02 2.428e+02
B-14
DSP56366 Advance Information
MOTOROLA
IBIS Model
-2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [GND_clamp] |voltage |
2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 2.662e+01 9.360e+00 4.275e-02 8.208e-03 5.635e-03 3.370e-03 1.118e-03 -1.09e-03 -3.12e-03 -4.96e-03 -6.60e-03 -8.04e-03 -9.26e-03 -1.03e-02 -1.25e-01 -1.31e-01 -1.36e-01 -1.40e-01 -1.42e-01 -1.44e-01 -1.46e-01 -1.48e-01 -1.49e-01 -1.50e-01 -1.52e-01 -1.53e-01 -1.54e-01 -1.57e-01 -5.25e-01 -2.74e+01 -6.14e+01 -9.55e+01 -1.38e+02 -1.89e+02 -2.40e+02 -2.91e+02 -3.42e+02 -3.93e+02 -4.44e+02 -4.95e+02 -5.21e+02
1.545e+02 1.365e+02 1.185e+02 1.005e+02 8.253e+01 6.454e+01 5.068e+01 3.859e+01 2.651e+01 1.444e+01 2.518e+00 2.012e-02 3.518e-03 2.053e-03 6.789e-04 -6.56e-04 -1.86e-03 -2.93e-03 -3.87e-03 -4.66e-03 -5.30e-03 -6.55e-02 -6.93e-02 -7.19e-02 -7.38e-02 -7.53e-02 -7.65e-02 -7.76e-02 -7.85e-02 -7.93e-02 -8.00e-02 -8.06e-02 -8.13e-02 -8.84e-02 -1.26e+00 -2.16e+01 -4.53e+01 -6.89e+01 -9.26e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.19e+02
2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 2.662e+01 9.362e+00 4.663e-02 1.070e-02 7.068e-03 4.233e-03 1.410e-03 -1.38e-03 -3.99e-03 -6.39e-03 -8.59e-03 -1.06e-02 -1.23e-02 -1.38e-02 -1.70e-01 -1.82e-01 -1.91e-01 -1.97e-01 -2.03e-01 -2.07e-01 -2.10e-01 -2.13e-01 -2.15e-01 -2.17e-01 -2.19e-01 -2.21e-01 -2.22e-01 -2.24e-01 -2.27e-01 -2.38e-01 -7.90e+00 -4.20e+01 -7.60e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.42e+02
I(typ)
I(min)
I(max)
MOTOROLA
DSP56366 Advance Information
B-15
IBIS Model
-3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -1.22e-02 -1.18e+00 -1.17e-02 -7.00e-01 -5.18e-04 -6.62e-03 -1.56e-03 -5.00e-01 -2.43e-06 -6.64e-05 -1.80e-05 -3.00e-01 -2.33e-09 -6.35e-07 -1.54e-08 -1.00e-01 -2.10e-11 -6.31e-09 -2.99e-11 0.000e+00 -1.70e-11 -1.95e-09 -1.91e-11 | [POWER_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.236e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.358e+00 1.444e+01 9.359e+00 -9.00e-01 3.399e-02 2.517e+00 3.554e-02 -7.00e-01 3.426e-04 1.577e-02 9.211e-04 -5.00e-01 2.840e-06 7.857e-05 1.655e-05 -3.00e-01 3.401e-09 6.836e-07 1.946e-08 -1.00e-01 6.162e-11 7.379e-09 7.622e-11 0.000e+00 5.758e-11 2.438e-09 6.240e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.680/0.164 1.360/0.329 1.900/0.124 | | dV/dt_f 1.690/0.219 1.310/0.442 1.880/0.155 | | [Model] icbc_o
B-16
DSP56366 Advance Information
MOTOROLA
IBIS Model
Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -2.51e-02 -1.18e+00 -2.65e-02 -7.00e-01 -1.30e-02 -1.16e-02 -1.58e-02 -5.00e-01 -9.33e-03 -4.67e-03 -1.10e-02 -3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03 -1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03 1.000e-01 1.945e-03 9.285e-04 2.307e-03 3.000e-01 5.507e-03 2.640e-03 6.599e-03 5.000e-01 8.649e-03 4.168e-03 1.048e-02 7.000e-01 1.136e-02 5.504e-03 1.393e-02 9.000e-01 1.364e-02 6.636e-03 1.693e-02 1.100e+00 1.547e-02 7.551e-03 1.950e-02 1.300e+00 1.688e-02 8.240e-03 2.162e-02 1.500e+00 9.632e-02 4.783e-02 2.331e-02 1.700e+00 1.012e-01 4.994e-02 1.302e-01 1.900e+00 1.039e-01 5.118e-02 1.369e-01 2.100e+00 1.053e-01 5.184e-02 1.412e-01 2.300e+00 1.060e-01 5.223e-02 1.436e-01 2.500e+00 1.065e-01 5.251e-02 1.449e-01 2.700e+00 1.069e-01 5.274e-02 1.458e-01 2.900e+00 1.073e-01 5.293e-02 1.464e-01 3.100e+00 1.076e-01 5.309e-02 1.470e-01 3.300e+00 1.078e-01 5.324e-02 1.475e-01 3.500e+00 1.081e-01 5.344e-02 1.479e-01 3.700e+00 1.083e-01 6.705e-02 1.483e-01 3.900e+00 1.086e-01 2.529e+00 1.487e-01 4.100e+00 1.103e-01 1.438e+01 1.491e-01 4.300e+00 1.437e+00 2.638e+01 1.503e-01 4.500e+00 1.800e+01 3.839e+01 1.810e-01 4.700e+00 3.519e+01 5.041e+01 9.452e+00 4.900e+00 5.241e+01 6.419e+01 2.664e+01 5.100e+00 7.505e+01 8.210e+01 4.384e+01 5.300e+00 1.007e+02 1.000e+02 6.224e+01
MOTOROLA
DSP56366 Advance Information
B-17
IBIS Model
5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00
1.264e+02 1.522e+02 1.779e+02 2.036e+02 2.293e+02 2.550e+02 2.678e+02
1.179e+02 1.359e+02 1.538e+02 1.717e+02 1.896e+02 2.075e+02 2.165e+02
8.794e+01 1.136e+02 1.394e+02 1.651e+02 1.908e+02 2.165e+02 2.293e+02
I(typ) 2.677e+02 2.420e+02 2.163e+02 1.906e+02 1.649e+02 1.392e+02 1.135e+02 8.778e+01 6.208e+01 4.368e+01 2.649e+01 9.302e+00 3.838e-02 8.115e-03 5.634e-03 3.370e-03 1.118e-03 -1.09e-03 -3.12e-03 -4.96e-03 -6.60e-03 -8.04e-03 -9.26e-03 -1.03e-02 -9.03e-02 -9.49e-02 -9.84e-02 -1.01e-01 -1.03e-01 -1.05e-01 -1.06e-01 -1.07e-01 -1.08e-01 -1.09e-01 -1.10e-01 -1.11e-01 -1.11e-01 -1.14e-01 -4.76e-01 -2.73e+01 -6.14e+01 -9.54e+01
I(min) 1.896e+02 1.716e+02 1.537e+02 1.358e+02 1.179e+02 9.996e+01 8.205e+01 6.413e+01 5.035e+01 3.834e+01 2.633e+01 1.433e+01 2.477e+00 1.789e-02 3.503e-03 2.053e-03 6.789e-04 -6.56e-04 -1.86e-03 -2.93e-03 -3.87e-03 -4.66e-03 -5.30e-03 -4.75e-02 -5.02e-02 -5.21e-02 -5.34e-02 -5.45e-02 -5.54e-02 -5.62e-02 -5.68e-02 -5.74e-02 -5.79e-02 -5.84e-02 -5.89e-02 -6.49e-02 -1.23e+00 -2.16e+01 -4.52e+01 -6.89e+01 -9.25e+01 -1.17e+02
I(max) 2.677e+02 2.420e+02 2.163e+02 1.906e+02 1.649e+02 1.392e+02 1.135e+02 8.778e+01 6.208e+01 4.368e+01 2.649e+01 9.303e+00 4.183e-02 1.045e-02 7.064e-03 4.233e-03 1.410e-03 -1.38e-03 -3.99e-03 -6.39e-03 -8.59e-03 -1.06e-02 -1.23e-02 -1.41e-02 -1.23e-01 -1.31e-01 -1.38e-01 -1.43e-01 -1.47e-01 -1.50e-01 -1.52e-01 -1.54e-01 -1.56e-01 -1.57e-01 -1.59e-01 -1.60e-01 -1.61e-01 -1.62e-01 -1.64e-01 -1.73e-01 -7.82e+00 -4.19e+01
B-18
DSP56366 Advance Information
MOTOROLA
IBIS Model
5.100e+00 -1.38e+02 5.300e+00 -1.89e+02 5.500e+00 -2.40e+02 5.700e+00 -2.91e+02 5.900e+00 -3.42e+02 6.100e+00 -3.93e+02 6.300e+00 -4.44e+02 6.500e+00 -4.95e+02 6.600e+00 -5.20e+02 | [GND_clamp] |voltage I(typ) | -3.30e+00 -5.20e+02 -3.10e+00 -4.69e+02 -2.90e+00 -4.18e+02 -2.70e+00 -3.67e+02 -2.50e+00 -3.16e+02 -2.30e+00 -2.65e+02 -2.10e+00 -2.14e+02 -1.90e+00 -1.63e+02 -1.70e+00 -1.13e+02 -1.50e+00 -7.83e+01 -1.30e+00 -4.42e+01 -1.10e+00 -1.02e+01 -9.00e-01 -1.03e-02 -7.00e-01 -3.74e-04 -5.00e-01 -1.72e-06 -3.00e-01 -1.67e-09 -1.00e-01 -2.03e-11 0.000e+00 -1.69e-11 | [POWER_clamp] |voltage I(typ) | -3.30e+00 2.677e+02 -3.10e+00 2.420e+02 -2.90e+00 2.163e+02 -2.70e+00 1.906e+02 -2.50e+00 1.649e+02 -2.30e+00 1.392e+02 -2.10e+00 1.135e+02 -1.90e+00 8.778e+01 -1.70e+00 6.208e+01 -1.50e+00 4.368e+01 -1.30e+00 2.649e+01 -1.10e+00 9.300e+00 -9.00e-01 2.962e-02 -7.00e-01 2.501e-04 -5.00e-01 2.066e-06 -3.00e-01 2.487e-09 -1.00e-01 5.672e-11 0.000e+00 5.334e-11
-1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.18e+02
-7.59e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.41e+02
I(min) -3.65e+02 -3.30e+02 -2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.51e+01 -2.15e+01 -1.17e+00 -5.73e-03 -5.06e-05 -4.65e-07 -4.80e-09 -1.61e-09
I(max) -5.18e+02 -4.67e+02 -4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02 -2.11e+02 -1.60e+02 -1.10e+02 -7.58e+01 -4.17e+01 -7.66e+00 -9.27e-03 -1.14e-03 -1.28e-05 -1.10e-08 -2.71e-11 -1.89e-11
I(min) 1.896e+02 1.716e+02 1.537e+02 1.358e+02 1.179e+02 9.996e+01 8.205e+01 6.413e+01 5.035e+01 3.834e+01 2.633e+01 1.433e+01 2.475e+00 1.354e-02 6.280e-05 5.128e-07 5.639e-09 1.992e-09
I(max) 2.677e+02 2.420e+02 2.163e+02 1.906e+02 1.649e+02 1.392e+02 1.135e+02 8.778e+01 6.208e+01 4.368e+01 2.649e+01 9.301e+00 3.075e-02 6.708e-04 1.204e-05 1.417e-08 6.832e-11 5.783e-11
MOTOROLA
DSP56366 Advance Information
B-19
IBIS Model
| [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.570/0.200 1.210/0.411 1.810/0.149 | | dV/dt_f 1.590/0.304 1.170/0.673 1.800/0.205 | | [Model] ipbw_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02 -3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02 -2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02 -1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.16e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.64e+00 -9.00e-01 -7.17e-03 -1.16e+00 -4.87e-03 -7.00e-01 -1.14e-04 -4.39e-03 -3.03e-04 -5.00e-01 -4.86e-07 -2.55e-05 -2.73e-06 -3.00e-01 -5.19e-10 -1.91e-07 -2.57e-09 -1.00e-01 -1.91e-11 -2.47e-09 -2.19e-11 0.000e+00 -1.68e-11 -1.17e-09 -1.84e-11 | [POWER_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02
B-20
DSP56366 Advance Information
MOTOROLA
IBIS Model
-1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.634e+01 2.613e+01 2.634e+01 -1.10e+00 9.237e+00 1.421e+01 9.237e+00 -9.00e-01 2.454e-02 2.430e+00 2.488e-02 -7.00e-01 8.741e-05 1.104e-02 2.050e-04 -5.00e-01 6.316e-07 4.079e-05 2.961e-06 -3.00e-01 8.479e-10 2.484e-07 3.721e-09 -1.00e-01 4.420e-11 3.001e-09 4.943e-11 0.000e+00 4.215e-11 1.346e-09 4.543e-11 | | [Model] ipbw_io Model_type I/O Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02 -3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02 -2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02 -1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.66e+00 -9.00e-01 -3.69e-02 -1.17e+00 -3.79e-02 -7.00e-01 -2.52e-02 -1.67e-02 -2.81e-02 -5.00e-01 -1.83e-02 -9.77e-03 -2.04e-02 -3.00e-01 -1.11e-02 -5.89e-03 -1.24e-02 -1.00e-01 -3.77e-03 -1.98e-03 -4.20e-03 1.000e-01 3.729e-03 1.940e-03 4.177e-03 3.000e-01 1.076e-02 5.578e-03 1.216e-02 5.000e-01 1.723e-02 8.907e-03 1.965e-02 7.000e-01 2.311e-02 1.191e-02 2.663e-02 9.000e-01 2.836e-02 1.455e-02 3.305e-02 1.100e+00 3.292e-02 1.680e-02 3.887e-02 1.300e+00 3.675e-02 1.862e-02 4.404e-02 1.500e+00 3.979e-02 1.997e-02 4.850e-02 1.700e+00 4.205e-02 2.085e-02 5.223e-02 1.900e+00 4.347e-02 2.136e-02 5.518e-02 2.100e+00 4.413e-02 2.162e-02 5.728e-02
MOTOROLA
DSP56366 Advance Information
B-21
IBIS Model
2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00
4.445e-02 4.465e-02 4.479e-02 4.492e-02 4.502e-02 4.511e-02 4.519e-02 4.526e-02 4.536e-02 4.614e-02 1.344e+00 1.783e+01 3.495e+01 5.208e+01 7.463e+01 1.002e+02 1.259e+02 1.515e+02 1.771e+02 2.027e+02 2.283e+02 2.539e+02 2.667e+02
2.176e-02 2.186e-02 2.194e-02 2.200e-02 2.206e-02 2.211e-02 2.219e-02 3.324e-02 2.452e+00 1.423e+01 2.615e+01 3.808e+01 5.001e+01 6.371e+01 8.154e+01 9.937e+01 1.172e+02 1.350e+02 1.529e+02 1.707e+02 1.885e+02 2.064e+02 2.153e+02
5.843e-02 5.899e-02 5.931e-02 5.953e-02 5.971e-02 5.986e-02 5.999e-02 6.010e-02 6.021e-02 6.032e-02 6.065e-02 8.548e-02 9.298e+00 2.640e+01 4.352e+01 6.184e+01 8.745e+01 1.131e+02 1.387e+02 1.643e+02 1.899e+02 2.155e+02 2.283e+02
I(typ) 2.667e+02 2.411e+02 2.155e+02 1.898e+02 1.642e+02 1.386e+02 1.130e+02 8.739e+01 6.178e+01 4.346e+01 2.635e+01 9.243e+00 5.536e-02 2.847e-02 2.025e-02 1.208e-02 3.994e-03 -3.88e-03 -1.11e-02 -1.76e-02 -2.35e-02 -2.86e-02 -3.30e-02 -3.65e-02 -3.92e-02 -4.12e-02
I(min) 1.885e+02 1.707e+02 1.528e+02 1.350e+02 1.172e+02 9.935e+01 8.152e+01 6.369e+01 4.999e+01 3.806e+01 2.613e+01 1.421e+01 2.435e+00 2.689e-02 1.265e-02 7.503e-03 2.474e-03 -2.38e-03 -6.76e-03 -1.06e-02 -1.40e-02 -1.69e-02 -1.93e-02 -2.10e-02 -2.22e-02 -2.29e-02
I(max) 2.667e+02 2.411e+02 2.155e+02 1.898e+02 1.642e+02 1.386e+02 1.130e+02 8.739e+01 6.178e+01 4.346e+01 2.635e+01 9.245e+00 6.260e-02 3.437e-02 2.451e-02 1.467e-02 4.868e-03 -4.76e-03 -1.37e-02 -2.20e-02 -2.95e-02 -3.63e-02 -4.23e-02 -4.75e-02 -5.17e-02 -5.51e-02
B-22
DSP56366 Advance Information
MOTOROLA
IBIS Model
1.900e+00 -4.26e-02 2.100e+00 -4.36e-02 2.300e+00 -4.43e-02 2.500e+00 -4.49e-02 2.700e+00 -4.54e-02 2.900e+00 -4.58e-02 3.100e+00 -4.61e-02 3.300e+00 -4.65e-02 3.500e+00 -4.68e-02 3.700e+00 -4.70e-02 3.900e+00 -4.73e-02 4.100e+00 -4.81e-02 4.300e+00 -4.00e-01 4.500e+00 -2.72e+01 4.700e+00 -6.12e+01 4.900e+00 -9.52e+01 5.100e+00 -1.37e+02 5.300e+00 -1.88e+02 5.500e+00 -2.39e+02 5.700e+00 -2.90e+02 5.900e+00 -3.41e+02 6.100e+00 -3.92e+02 6.300e+00 -4.43e+02 6.500e+00 -4.94e+02 6.600e+00 -5.20e+02 | [GND_clamp] |voltage I(typ) | -3.30e+00 -5.20e+02 -3.10e+00 -4.69e+02 -2.90e+00 -4.18e+02 -2.70e+00 -3.67e+02 -2.50e+00 -3.16e+02 -2.30e+00 -2.65e+02 -2.10e+00 -2.14e+02 -1.90e+00 -1.63e+02 -1.70e+00 -1.13e+02 -1.50e+00 -7.82e+01 -1.30e+00 -4.42e+01 -1.10e+00 -1.02e+01 -9.00e-01 -7.17e-03 -7.00e-01 -1.14e-04 -5.00e-01 -4.86e-07 -3.00e-01 -5.19e-10 -1.00e-01 -1.91e-11 0.000e+00 -1.68e-11 | [POWER_clamp] |voltage I(typ) | -3.30e+00 2.667e+02 -3.10e+00 2.411e+02
-2.35e-02 -2.38e-02 -2.42e-02 -2.44e-02 -2.47e-02 -2.49e-02 -2.50e-02 -2.52e-02 -2.54e-02 -2.99e-02 -1.19e+00 -2.15e+01 -4.51e+01 -6.87e+01 -9.24e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.58e+02 -2.94e+02 -3.29e+02 -3.65e+02 -4.00e+02 -4.18e+02
-5.77e-02 -5.97e-02 -6.11e-02 -6.22e-02 -6.31e-02 -6.38e-02 -6.44e-02 -6.49e-02 -6.54e-02 -6.58e-02 -6.62e-02 -6.66e-02 -6.72e-02 -7.21e-02 -7.70e+00 -4.17e+01 -7.57e+01 -1.10e+02 -1.60e+02 -2.11e+02 -2.62e+02 -3.13e+02 -3.64e+02 -4.15e+02 -4.41e+02
I(min) -3.65e+02 -3.29e+02 -2.94e+02 -2.58e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.24e+01 -6.87e+01 -4.51e+01 -2.15e+01 -1.16e+00 -4.39e-03 -2.55e-05 -1.91e-07 -2.47e-09 -1.17e-09
I(max) -5.17e+02 -4.66e+02 -4.15e+02 -3.64e+02 -3.13e+02 -2.62e+02 -2.11e+02 -1.60e+02 -1.10e+02 -7.57e+01 -4.16e+01 -7.64e+00 -4.87e-03 -3.03e-04 -2.73e-06 -2.57e-09 -2.19e-11 -1.84e-11
I(min) 1.885e+02 1.707e+02
I(max) 2.667e+02 2.411e+02
MOTOROLA
DSP56366 Advance Information
B-23
IBIS Model
-2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.634e+01 2.613e+01 2.634e+01 -1.10e+00 9.237e+00 1.421e+01 9.237e+00 -9.00e-01 2.454e-02 2.430e+00 2.488e-02 -7.00e-01 8.741e-05 1.104e-02 2.050e-04 -5.00e-01 6.316e-07 4.079e-05 2.961e-06 -3.00e-01 8.479e-10 2.484e-07 3.721e-09 -1.00e-01 4.420e-11 3.001e-09 4.943e-11 0.000e+00 4.215e-11 1.346e-09 4.543e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.140/0.494 0.699/0.978 1.400/0.354 | | dV/dt_f 1.150/0.505 0.642/0.956 1.350/0.350 | | [Model] iexlh_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.66e+02 -5.18e+02 -3.10e+00 -4.70e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.19e+02 -2.95e+02 -4.16e+02 -2.70e+00 -3.68e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.17e+02 -2.24e+02 -3.14e+02 -2.30e+00 -2.66e+02 -1.89e+02 -2.63e+02 -2.10e+00 -2.15e+02 -1.53e+02 -2.12e+02 -1.90e+00 -1.64e+02 -1.18e+02 -1.61e+02 -1.70e+00 -1.14e+02 -9.34e+01 -1.11e+02 -1.50e+00 -7.93e+01 -6.98e+01 -7.68e+01 -1.30e+00 -4.53e+01 -4.62e+01 -4.28e+01 -1.10e+00 -1.13e+01 -2.26e+01 -8.78e+00 -9.00e-01 -7.94e-03 -1.87e+00 -3.77e-03
B-24
DSP56366 Advance Information
MOTOROLA
IBIS Model
-7.00e-01 -1.62e-06 -5.00e-01 -3.45e-10 -3.00e-01 -1.29e-11 -1.00e-01 -1.10e-11 0.000e+00 -1.01e-11 | [POWER_clamp] |voltage I(typ) | -3.30e+00 2.653e+02 -3.10e+00 2.398e+02 -2.90e+00 2.143e+02 -2.70e+00 1.888e+02 -2.50e+00 1.633e+02 -2.30e+00 1.378e+02 -2.10e+00 1.123e+02 -1.90e+00 8.682e+01 -1.70e+00 6.133e+01 -1.50e+00 4.313e+01 -1.30e+00 2.614e+01 -1.10e+00 9.145e+00 -9.00e-01 1.797e-02 -7.00e-01 3.667e-06 -5.00e-01 7.730e-10 -3.00e-01 2.293e-11 -1.00e-01 2.096e-11 0.000e+00 2.004e-11 | [End]
-5.11e-03 -1.40e-05 -3.90e-08 -8.67e-10 -7.13e-10
-7.69e-07 -1.72e-10 -1.38e-11 -1.19e-11 -1.10e-11
I(min) 1.870e+02 1.693e+02 1.516e+02 1.339e+02 1.162e+02 9.847e+01 8.076e+01 6.305e+01 4.947e+01 3.766e+01 2.585e+01 1.404e+01 2.364e+00 7.589e-03 2.072e-05 5.767e-08 1.163e-09 9.618e-10
I(max) 2.653e+02 2.398e+02 2.143e+02 1.888e+02 1.633e+02 1.378e+02 1.123e+02 8.682e+01 6.133e+01 4.313e+01 2.614e+01 9.145e+00 1.797e-02 3.667e-06 7.748e-10 2.476e-11 2.278e-11 2.186e-11
MOTOROLA
DSP56366 Advance Information
B-25
IBIS Model
B-26
DSP56366 Advance Information
MOTOROLA
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USA/Europe/Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1 (800) 441-2447 1 (303) 675-2140 Asia/Pacific: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-26629298 Technical Resource Center: 1 (800) 521-6274 DSP Helpline dsphelp@dsp.sps.mot.com Japan: Nippon Motorola Ltd. SPD, Strategic Planning Office 4-32-1, Nishi- Gotanda Shinagawa-ku, Tokyo 141, Japan 81-3-5487-8488 Internet: http://dspaudio.motorola.com

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