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HYB39S256400/800/160T 256MBit Synchronous DRAM 256 MBit Synchronous DRAM
Preliminary Information
*
High Performance:
-8 fCK tCK3 tAC3 tCK2 tAC2 125 8 6 10 6 -8A 125 8 6 12 6 -8B 100 10 6 15 7 Units MHz ns ns ns ns
* * * * * * * * * * * *
Multiple Burst Read with Single Write Operation Automatic Command and Controlled Precharge
Data Mask for Read / Write control (x4, x8) Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode 8192 refresh cycles / 64 ms (7,8 s) Random Column Address every CLK ( 1-N Rule) Single 3.3V +/- 0.3V Power Supply LVTTL Interface versions Plastic Packages: P-TSOPII-54 400mil width (x4, x8, x16) -8 parts for PC100 2-2-2 operation -8A parts for PC100 3-2-2 operation -8B parts for PC100 3-2-3 operation
* * * * * *
Fully Synchronous to Positive Clock Edge 0 to 70 C operating temperature Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2, 3, 4 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8
The HYB39S256400/800/160T are four bank Synchronous DRAM's organized as 4 banks x 16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with INFINEON's advanced 256MBit DRAM process technology. The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a single 3.3V +/- 0.3V power supply and are available in TSOPII packages.
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4.99
HYB39S256400/800/160T 256MBit Synchronous DRAM
Ordering Information
Type Speed Grade Package Description
LVTTL-version:
HYB 39S256400T-8 HYB 39S256400T-8A HYB 39S256400T-8B HYB 39S256800T-8 HYB 39S256800T-8A HYB 39S256800T-8B HYB 39S256160T-8 HYB 39S256160T-8A HYB 39S256160T-8B PC100-222-620 PC100-322-620 PC100-323-620 PC100-222-620 PC100-322-620 PC100-323-620 PC100-222-620 PC100-322-620 PC100-323-620 P-TSOP-54-2 (400mil) P-TSOP-54-2 (400mil) P-TSOP-54-2 (400mil) P-TSOP-54-2 (400mil) P-TSOP-54-2 (400mil) P-TSOP-54-2 (400mil) P-TSOP-54-2 (400mil) P-TSOP-54-2 (400mil) P-TSOP-54-2 (400mil) 125MHz 4B x 16M x 4 SDRAM 125MHz 4B x 16M x 4 SDRAM 100MHz 4B x 16M x 4 SDRAM 125MHz 4B x 8M x 8 SDRAM 125MHz 4B x 8M x 8 SDRAM 100MHz 4B x 8M x 8 SDRAM 125MHz 4B x 4M x 16 SDRAM 125MHz 4B x 4M x 16 SDRAM 100MHz 4B x 4M x 16 SDRAM
Pin Description and Pinouts:
CLK CKE CS RAS CAS WE A0-A12 BA0, BA1 Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select DQ DQM, LDQM, UDQM Vdd Vss Vddq Vssq NC Data Input /Output Data Mask Power (+3.3V) Ground Power for DQ's (+ 3.3V) Ground for DQ's not connected
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HYB39S256400/800/160T 256MBit Synchronous DRAM
16M x 16 32M x 8 64M x 4
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD
VDD VDD DQ0 NC VDDQ VDDQ NC NC DQ1 DQ0 VSSQ VSSQ NC NC DQ2 NC VDDQ VDDQ NC NC DQ3 DQ1 VSSQ VSSQ NC NC VDD VDD NC NC WE WE CAS CAS RAS RAS CS CS BA0 BA0 BA1 BA1 A10/APA10/AP A0 A0 A1 A1 A2 A2 A3 A3 VDD VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
TSOPII-54 (400 mil x 875 mil, 0.8 mm pitch)
Pinout for x4, x8 & x16 organised 256M-DRAMs
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HYB39S256400/800/160T 256MBit Synchronous DRAM
Column Addresses A0 - A9,A11 AP, BA0, BA1
Row Addresses A0 - A12, BA0, BA1
Column address counter
Column address buffer
Row address buffer
Refresh Counter
Row decoder Column decoder Sense amplifier & I(O) bus Column decoder Sense amplifier & I(O) bus Memory array Bank 0
Row decoder Column decoder Sense amplifier & I(O) bus Memory array Bank 1
Row decoder Memory array Bank 2 Column decoder Sense amplifier & I(O) bus
Row decoder Memory array Bank 3
8196 x 2048 x 4 bit
8196 x 2048 x 4 bit
8196 x 2048 x 4 bit
8196 x 2048 x 4 bit
Input buffer
Output buffer
Control logic & timing generator
DQ0-DQ3 CAS CKE RAS WE DQM CLK CS
Block Diagram for 64M x 4 SDRAM ( 13 / 11 / 2 addressing)
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HYB39S256400/800/160T 256MBit Synchronous DRAM
Column Addresses A0 - A9, AP, BA0, BA1
Row Addresses A0 - A12, BA0, BA1
Column address counter
Column address buffer
Row address buffer
Refresh Counter
Row decoder Column decoder Sense amplifier & I(O) bus Column decoder Sense amplifier & I(O) bus Memory array Bank 0
Row decoder Column decoder Sense amplifier & I(O) bus Memory array Bank 1
Row decoder Memory array Bank 2 Column decoder Sense amplifier & I(O) bus
Row decoder Memory array Bank 3
8192 x 1024 x 8 bit
8192 x 1024 x 8 bit
8192 x 1024 x 8 bit
8192 x 1024 x 8 bit
Input buffer
Output buffer
Control logic & timing generator
DQ0-DQ7 CAS CKE RAS WE DQM CLK CS
Block Diagram for 32M x 8 SDRAM ( 13 / 10 / 2 addressing)
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HYB39S256400/800/160T 256MBit Synchronous DRAM
Column Addresses A0 - A8, AP, BA0, BA1
Row Addresses A0 - A12, BA0, BA1
Column address counter
Column address buffer
Row address buffer
Refresh Counter
Row decoder Column decoder Sense amplifier & I(O) bus Column decoder Sense amplifier & I(O) bus Memory array Bank 0
Row decoder Column decoder Sense amplifier & I(O) bus Memory array Bank 1
Row decoder Memory array Bank 2 Column decoder Sense amplifier & I(O) bus
Row decoder Memory array Bank 3
8192 x 512 x16 bit
8192 x 512 x16 bit
8192x512 x16 bit
8192x512 x16 bit
Input buffer
Output buffer
Control logic & timing generator
DQ0-DQ15 DQMU DQML CAS CKE RAS CLK WE CS
Block Diagram for 16M x16 SDRAM ( 13 / 9 / 2 addressing)
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HYB39S256400/800/160T 256MBit Synchronous DRAM
Signal Pin Description Pin
CLK
Type Signal Polarity
Input Pulse
Function
Positive The system clock input. All of the SDRAM inputs are sampled on the Edge rising edge of the clock. Active High Active Low Active Low Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode, Suspend mode, or the Self Refresh mode. CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled at the rising clock edge.CAn depends from the SDRAM organisation: 64M x 4 SDRAM CAn = CA9,CA11 (Page Length = 2048 bits) 32M x 8 SDRAM CAn = CA9 (Page Length = 1024 bits) 16M x 16 SDRAM CAn = CA8 (Page Length = 512 bits)
CKE
Input
Level
CS RAS, CAS, WE
Input
Pulse
Input
Pulse
A0 - A12
Input
Level
--
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 (=AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged regardless of the state of BA0 and BA1. If A10 is low, then BA0 and BA1 are used to define which bank to precharge.
BA0,BA1 DQx
Input Input Output
Level Level
-- --
Bank Select Inputs. Bank address inputs selects which of the four banks a command applies to. Data Input/Output pins operate in the same manner as on conventional DRAMs. The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. One DQM input it present in x4 and x8 SDRAMs, LDQM and UDQM controls the lower and upper bytes in x16 SDRAMs.
DQM LDQM UDQM
Input
Pulse
Active High
VDD,VSS Supply VDDQ VSSQ Supply -- --
Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity.
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HYB39S256400/800/160T 256MBit Synchronous DRAM
Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands.
Operation Bank Active Bank Precharge Precharge All Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Set No Operation Burst Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit
Device State Idle3 Any Any Active3 Active3 Active3 Active3 Idle Any Active4 Any Idle Idle Idle (Self Refr.) Active Idle Active5 Active Any (Power Down) Active Active
CKE n-1 H H H H H H H H H H H H H L H H L L H H
CKE n X X X X X X X X X X X H L H L L H H X X
DQM X X X X X X X X X X X X X X X X X X L H
BS0 BS1 V V X V V V V V X X X X X X X X X X X X
AP= A10 V L H L H L H V X X X X X X X X X X X X
Addr . V X X V V V V V X X X X X X X X X X X X
CS L L L L L L L L L L H L L H L X H L X H L X X
RAS L L L H H H H L H H X L L X H X X H X X H X X
CAS H H H L L L L L H H X L L X H X X H X X H X X
WE H L L L L H H L H L X H H X X X X X X X L X X
Clock Suspend Entry Power Down Entry (Precharge or active standby) Clock Suspend Exit Power Down Exit
Data Write/Output Enable Data Write/Output Disable
Note:
1. V = Valid, x = Don't Care, L = Low Level, H = High Level 2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3. This is the state of the banks designated by BA0, BA1 signals. 4. Device state is Full Page Burst operation, which is not supported on this device. 5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode cycle device is clock suspend mode.
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HYB39S256400/800/160T 256MBit Synchronous DRAM
Address Input for Mode Set (Mode Register Operation)
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus (Ax)
Operation Mode
CAS Latency
BT
Burst Length
Mode Register (Mx)
Operation Mode
M9 0 1 Mode burst read / burst write burst read / single write
Burst Type
M3 0 1 Type Sequential Interleave
Burst Length CAS Latency
M6 0 0 0 0 1 1 1 1 M5 0 0 1 1 0 0 1 1 M4 0 1 0 1 0 1 0 1 Reserved Latency Reserved Reserved 2 3 4 M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 Reserved Reserved Length Sequential 1 2 4 8 Interleave 1 2 4 8
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HYB39S256400/800/160T 256MBit Synchronous DRAM
Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner.During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 s is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Programming the Mode Register The Mode register designates the operation mode at the read or write cycle. This register is divided into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency Field to set the access time at clock cycle and a Operation mode field to differentiate between normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode. The mode set operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by re-executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table. Read and Write Operation When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 143 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4 and 8. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is `2', then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Similar to the page mode of conventional DRAM's, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
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HYB39S256400/800/160T 256MBit Synchronous DRAM
When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. Once two or more banks are activated, column to column interleave operation can be performed between different pages. Burst Length and Sequence:
Burst Starting Address Length (A2 A1 A0) 2 4 xx0 xx1 x00 x01 x10 x11 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 Sequential Burst Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 Interleave Burst Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
8
Refresh Mode SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS refresh of conventional DRAMs. All of banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. The chip has an on-chip timer and the Self Refresh mode is available. The mode restores the word lines after RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any access command. DQM Function
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HYB39S256400/800/160T 256MBit Synchronous DRAM
DQM has two functions for data I/O read and write operations. During reads, when it turns to high" at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks). Suspend Mode During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend Latency tCSL). Power Down In order to reduce standby power consumption, a power down mode is available. All banks must be precharged and the necessary Precharge delay (trp) must occur before the SDRAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can't remain in Power Down mode longer than the Refresh period (tref) of the device. Exit from this mode is performed by taking CKE high". One clock delay is required for mode entry and exit. Auto Precharge Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock before the last data out for CAS latencies 2, two clocks for CAS latencies 3 and three clocks for CAS latencies 4. If CAS10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation a time delay equal to tWR (Write recovery time) after the last data in. Precharge Command There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as shown in the following list. The precharge command can be imposed one clock before the last data out for CAS latency = 2, two clocks before the last data out for CAS latency = 3 and three clocks before the last data out for CAS latency= 4. Writes require a time delay twr from the last data out to apply the precharge command.
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HYB39S256400/800/160T 256MBit Synchronous DRAM
Bank Selection by Address Bits
A10 0 0 0 0 1 BA0 BA1 0 0 1 1 x 0 1 0 1 x Bank 0 Bank 1 Bank 2 Bank 3 all Banks
Burst Termination Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory.
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HYB39S256400/800/160T 256MBit Synchronous DRAM
Absolute Maximum Ratings Operating temperature range .........................................................................................0 to + 70 C Storage temperature range......................................................................................- 55 to + 150 C Input/output voltage ............................................................................................. - 0.3 to Vcc+0.3 V Power supply voltage VDD / VDDQ.......................................................................... - 0.3 to + 4.6 V Power Dissipation............................................. ..........................................................................1 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operation and Characteristics:
TA = 0 to 70 C; VSS = 0 V; VDD,VDDQ = 3.3 V 0.3 V
Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 4.0 mA) Output low voltage (IOUT = 4.0 mA) Input leakage current, any input (0 V < VIN < Vddq, all other inputs = 0 V) Output leakage current (DQ is disabled, 0 V < VOUT < VCC) Notes:
1. All voltages are referenced to VSS. 2. Vih may overshoot to Vcc + 2.0 V for pulse width of < 4ns with 3.3V. Vil may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
Symbol
Limit Values min. max. Vcc+0.3 0.8 - 0.4 5 5 2.0 - 0.3 2.4 - -5 -5
Unit Notes V V V V A A 1, 2 1, 2 3 3
VIH VIL VOH VOL II(L) IO(L)
Capacitance TA = 0 to 70 C; VDD = 3.3 V 0.3 V, f = 1 MHz Parameter Input capacitance (CLK) Input capacitance
(A0-A12, BA0,BA1,RAS, CAS, WE, CS, CKE, DQM)
Symbol
Values min. max. 4.0 5.0 6.5 2.5 2.5 4.0
Unit pF pF pF
CI1 CI2 CIO
Input / Output capacitance (DQ)
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HYB39S256400/800/160T 256MBit Synchronous DRAM
Operating Currents (TA = 0 to 70oC, Vdd = 3.3V 0.3V
(Recommended Operating Conditions unless otherwise noted)
Parameter & Test Condition
Symb.
-8/-8A max.
-8B
Note
OPERATING CURRENT trc=trcmin., tck=tckmin. Ouputs open, Burst Length = 4, CL=3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) PRECHARGE STANDBY CURRENT in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) NO OPERATING CURRENT tck = min., CS = VIH(min), active state ( max. 4 banks) BURST OPERATING CURRENT tck = min., Read command cycling CKE>=VIH(min.) CKE<=VIL(max.) tck = min. tck = min.
ICC1 x4 x8 x16
ICC2P
210 210 210 2
165 165 165 2
mA mA mA mA
3
3
ICC2N
19
16
mA
3
ICC3N ICC3P
45 10
40 10
mA mA
3 3
ICC4 x4 x8 x16
ICC5
210 210 210 240
165 165 165 195
mA mA mA mA
3,4
AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V standard version
3
ICC6
2.5
2.5
mA
3
Notes:
3. These parameters depend on the cycle rate. These values are measured at 125 MHz for -8 & -8A and at 100 MHz for -10 parts. Input signals are changed once during tck, excepts for ICC6 and for standby currents when tck=infinity. 4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the VDDQ current is excluded.
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HYB39S256400/800/160T 256MBit Synchronous DRAM
AC Characteristics 1)2) TA = 0 to 70 C; VSS = 0 V; Vdd = 3.3 V 0.3 V, tT = 1 ns Parameter
Symbol
Limit Values -8 PC100222
min. max.
Unit
-8A PC100322
min.
-8B PC100323
max.
max. min.
Clock and Clock Enable
Clock Cycle Time CAS Latency = 3 tCK CAS Latency = 2 Clock Frequency CAS Latency = 3 tCK CAS Latency = 2 Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Transition time - - - - 3 3 0.5 125 100 6 6 - - 10 - - - - 3 3 0.5 125 83 6 6 - - 10 - - - - 3 3 0.5 100 MHz 66 MHz 6 7 - - 10 ns ns ns ns ns
2, 3
8 10
- -
8 12
- -
10 15
- -
ns ns
tCH tCL tT
Setup and Hold Times
Input Setup Time Input Hold Time CKE Setup Time CKE Hold Time Mode Register Set-up time Power Down Mode Entry Time
tIS tIH tCKS tCKH tRSC tSB
2 1 2 1 16 0
- - - - - 8
2 1 2 1 16 0
- - - - - 10
2 1 2 1 20 0
- - - - - 10
ns ns ns ns ns ns
4 4 4 4
Common Parameters
Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time
tRCD tRP tRAS tRC
20 20 48 70
- -
100k
20 20 48 70
100k
20 30 60 80 -
- - -
ns ns ns
5 5 5 5
100k ns
-
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HYB39S256400/800/160T 256MBit Synchronous DRAM
Parameter
Symbol
Limit Values -8 PC100222
min. max.
Unit
-8A PC100322
min.
-8B PC100323
max.
max. min.
Activate(a) to Activate(b) Command period CAS(a) to CAS(b) Command period
tRRD tCCD
16 1
- -
16 1 -
20 1
- -
ns CLK
5
Refresh Cycle
Refresh Period (8192 cycles) Self Refresh Exit Time
tREF tSREX
- 10
64
- 10
64
- 10
64
ms ns
Read Cycle
Data Out Hold Time
Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency
tOH tLZ tHZ tDQZ
3 0 3 -
- - 8 2
3 0 3 -
- - 8 2
3 0 3 -
- - 10 2
ns ns ns CLK
2
Write Cycle
Data Input to Precharge (write recovery) DQM Write Mask Latency
tWR tDQW
2 0
- -
2 0
- -
2 0
- -
CLK CLK
INFINEON Technologies
17
HYB39S256400/800/160T 256MBit Synchronous DRAM
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet. 2. AC timing tests for LV-TTL versions have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is meas ured between Vih and Vil. All AC measurements assume tT=1ns with the AC output load circuit shown in fig.1.Specified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V.
tCH 2.4 V CLOCK tCL tSETUP tHOLD 0.4 V
+ 1.5 V 50 Ohm Z=50 Ohm I/O 50 pF
tT
INPUT
1.5V
tAC tLZ tOH
tAC
I/O 50 pF
OUTPUT
1.5V
Measurement conditions for tac and toh
tHZ
fig.1
3. If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter. 4. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered.
INFINEON Technologies
18
HYB39S256400/800/160T 256MBit Synchronous DRAM
Package Outlines
Plastic Package P-TSOPII-54 (400 mil, 0.8 mm lead pitch) Thin Small Outline Package, SMD
0.10.05
10.05
155
10.160.13 2)
0.8 155 0.35 +0.1 -0.05
3)
0.15 +0.06 -0.03
0.5 0.1 11.76 0.2
26x 0.8 = 20.8
0.1 54x 0.2 M 54x
54
28
6 max
1
2.5 max 22.220.13 1)
27
GPX09039
Index Marking
1) 2)
Does not include plastic or metal protrusion of 0.15 max per side Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side
INFINEON Technologies
19
HYB39S256400/800/160AT 256 MBit Synchronous DRAM Timing Diagrams
1. Bank Activate Command Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval 5. Burst Write Operation 6. Write and Read Interrupt 6.1 Write Interrupted by a Write 6.2 Write Interrupted by Read 7. Burst Write & Read with Auto-Precharge 7.1 Burst Write with Auto-Precharge 7.2 Burst Read with Auto-Precharge 8. AC- Parameters 8.1 AC Parameters for a Write Timing 8.2 AC Parameters for a Read Timing 9. Mode Register Set 10. Power on Sequence and Auto Refresh (CBR) 11. Clock Suspension (using CKE) 11. 1 Clock Suspension During Burst Read CAS Latency = 2 11. 2 Clock Suspension During Burst Read CAS Latency = 3 11. 3 Clock Suspension During Burst Write CAS Latency = 2 11. 4 Clock Suspension During Burst Write CAS Latency = 3 12. Power Down Mode and Clock Suspend 13. Self Refresh ( Entry and Exit ) 14. Auto Refresh ( CBR ) 15. Random Column Read ( Page within same Bank) 15.1 CAS Latency = 2 15.2 CAS Latency = 3 16. Random Column Write ( Page within same Bank) 16.1 CAS Latency = 2 16.2 CAS Latency = 3 17. Random Row Read ( Interleaving Banks) with Precharge 17.1 CAS Latency = 2 17.2 CAS Latency = 3 18. Random Row Write ( Interleaving Banks) with Precharge 18.1 CAS Latency = 2 18.2 CAS Latency = 3 19. Precharge Termination of a Burst
20
HYB39S256400/800/160AT 256 MBit Synchronous DRAM 1. Bank Activate Command Cycle
(CAS latency = 3)
T0 CLK
..........
T1
T
T
T
T
T
ADDRESS
Bank A Row Addr.
Bank A Col. Addr.
..........
Bank B Row Addr.
Bank A Row Addr.
tRCD
tRRD
NOP Write A with Auto Precharge .......... Bank B Activate NOP Bank A Activate
COMMAND
: "H" or "L"
Bank A Activate
NOP
tRC
2. Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
tCK2, DQ's
CAS latency = 3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
tCK3, DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
21
HYB39S256400/800/160AT 256 MBit Synchronous DRAM 3. Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
tCK2, DQ's
CAS latency = 3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
tCK3, DQ's
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
4.1 Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Minimum delay between the Read and Write Commands = 4+1 = 5 cycles
DQM
tDQZ
tDQW
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
DQ's
: "H" or "L"
DOUT A0 Must be Hi-Z before the Write Command
DIN B0
DIN B1
DIN B2
22
HYB39S256400/800/160AT 256 MBit Synchronous DRAM 4 2. Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2)
T0 CLK
tDQW
T1
T2
T3
T4
T5
T6
T7
T8
DQM
tDQZ
1 Clk Interval BANK A ACTIVATE
COMMAND
NOP
NOP
NOP
READ A
WRITE A
NOP
NOP
NOP
Must be Hi-Z before the Write Command CAS latency = 2
tCK2, DQ's
DIN A0
DIN A1
DIN A2
DIN A3
: "H" or "L"
4. 3. Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
tDQW
DQM
tDQZ
COMMAND
NOP
READ A
NOP
NOP
READ A
NOP
WRITE B
NOP
NOP
CAS latency = 2
Must be Hi-Z before the Write Command DOUT A0 DOUT A1 DIN B0 DIN B1 DIN B2
tCK2, DQ's
CAS latency = 3
tCK3, DQ's
DOUT A0
DIN B0
DIN B1
DIN B2
: "H" or "L"
23
HYB39S256400/800/160AT 256 MBit Synchronous DRAM 5. Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQ's
DIN A0
DIN A1
DIN A2
DIN A3
don't care
The first data element and the Write are registered on the same clock edge.
Extra data is ignored after termination of a Burst.
6.1 Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
1 Clk Interval
DQ's
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
24
HYB39S256400/800/160AT 256 MBit Synchronous DRAM 6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
tCK2, DQ's
CAS latency = 3
DIN A0
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
tCK3, DQ's
DIN A0
don't care
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Input data for the Write is ignored.
Input data must be removed from the DQ's at least one clock cycle before the Read data appears on the outputs to avoid data contention.
7.1 Burst Write with Auto-Precharge
Burst Length = 2, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
BANK A ACTIVE
NOP
NOP
WRITE A
Auto-Precharge
NOP
NOP
NOP
NOP
NOP
tWR
DIN A0 DIN A1
tRP
DQ's
*
Begin Autoprecharge Bank can be reactivated after trp
25
HYB39S256400/800/160AT 256 MBit Synchronous DRAM 7.2 Burst Read with Auto-Precharge
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ A with AP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
tCK2, DQ's
CAS latency = 3
DOUT A0
DOUT A1
* *
tRP
DOUT A3
DOUT A2
tRP
DOUT A2 DOUT A3
tCK3, DQ's
DOUT A0
DOUT A1
tRP
Bank can be reactivated after trp
*
Begin Autoprecharge
26
\
8.1 AC Parameters for Write Timing
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 4, CAS Latency = 2
T17 T18 T19 T20 T21 T22
CLK tCH CKE tCKS tCL tCS tCH tCK2
Begin Auto Precharge Bank A Begin Auto Precharge Bank B
tCKH
CS
RAS
CAS
27
WE
BS tAH AP tAS Addr
RAx CAx RBx CBx RAy RAy RAz RBy RAx RBx RAy RAz RBy
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
DQM tRCD tRC DQ
Hi-Z Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0
tDS tDH
Ay1 Ay2
tWR
Ay3
tRP
tRRD
Activate Write with Activate Write with Activate Command Auto Precharge Command Auto Precharge Command Bank A Command Bank B Command Bank A Bank A Bank B
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Activate Command Bank B
\
8.2 AC Parameters for Read Timing
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
Burst Length = 2, CAS Latency = 2
T10 T11 T12 T13
CLK tCH tCL CKE tCKS CS tCK2 tCS tCH
Begin Auto Precharge Bank A Begin Auto Precharge Bank B
tCKH
RAS
CAS
28
WE
BS tAH AP tAS Addr
RAx CAx RBx RBx RAy RAx RBx RAy
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
tRRD tRAS DQM tAC2 tRCD DQ
Hi-Z
tRC tAC2 tOH
Ax0
tLZ
tHZ
Ax1 Bx0
tRP tHZ
Bx1
Activate Command Bank A
Read with Auto Precharge Command Bank A
Activate Command Bank B
Read with Auto Precharge Command Bank B
Precharge Command Bank A
Activate Command Bank A
\
9. Mode Register Set
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
CAS Latency = 2
T20 T21 T22
CLK
CKE
tRSC
CS
RAS
CAS
29
WE
BS0,BS1
A10,A11
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Address Key
A0-A9
Precharge Command All Banks
Mode Register Set Command
Any Command
\
10. Power on Sequence and Auto Refresh (CBR)
T0 T T T T T T T T T T1 T T T T T T T T T T T T
CLK
CKE
High level is required
Minimum of 8 Refresh Cycles are required
2 Clock min.
CS
RAS
CAS
30
WE
BS
AP
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Address Key
Addr
DQM tRP DQ
Hi-Z
tRC
Precharge 1st Auto Refresh Command Command All Banks
8th Auto Refresh Command
Mode Register Set Command
Any Command
Inputs must be stable for 200s
\
11.1 Clock Suspension During Burst Read (Using CKE)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 4, CAS Latency = 2
T17 T18 T19 T20 T21 T22
CLK tCK2 CKE
CS
RAS
CAS
31
WE
BS
AP
RAx
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr
RAx
CAx
DQM
Hi-Z
tCSL
tCSL
tCSL tHZ
DQ
Ax0
Ax1
Ax2
Ax3
Activate Command Bank A
Read Command Bank A
Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
\
11.2 Clock Suspension During Burst Read (Using CKE)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 4, CAS Latency = 3
T17 T18 T19 T20 T21 T22
CLK tCK3 CKE
CS
RAS
CAS
32
WE
BS
AP
RAx
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr
RAx
CAx
DQM
Hi-Z
tCSL
tCSL
tCSL tHZ
DQ
Ax0
Ax1
Ax2
Ax3
Activate Command Bank A
Read Command Bank A
Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
\
11.3 Clock Suspension During Burst Write (Using CKE)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 4, CAS Latency = 2
T17 T18 T19 T20 T21 T22
CLK tCK2 CKE
CS
RAS
CAS
33
WE
BS
AP
RAx
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr
RAx
CAx
DQM
Hi-Z
DQ
DAx0
DAx1
DAx2
DAx3
Activate Command Bank A
Clock Suspend 1 Cycle Write Command Bank A
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
\
11.4 Clock Suspension During Burst Write (Using CKE)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 4, CAS Latency = 3
T17 T18 T19 T20 T21 T22
CLK tCK3 CKE
CS
RAS
CAS
34
WE
BS
AP
RAx
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr
RAx
CAx
DQM
Hi-Z
DQ
DAx0
DAx1
DAx2
DAx3
Activate Command Bank A
Clock Suspend 1 Cycle Write Command Bank A
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
\
12. Power Down Mode and Clock Suspend
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 4, CAS Latency = 2
T17 T18 T19 T20 T21 T22
CLK tCK2 CKE tCKS tCKS
CS
RAS
CAS
35
WE
BS
AP
RAx
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr
RAx
CAx
DQM tHZ DQ
Hi-Z Ax0 Ax1 Ax2 Ax3
PRECHARGE STANDBY
Activate Command Bank A
ACTIVE STANDBY
Read Command Bank A
Clock Mask Start
Clock Mask End
Precharge Command Bank A
Power Down Mode Entry
Power Down Mode Exit Any Command
Clock Suspend Mode Entry
Clock Suspend Mode Exit
\
13. Self Refresh (Entry and Exit)
T0 T1 T2 T3 T4 T5 T T T T T T T T T T T T T T T T T
CLK tCKS tCKS
CKE
CS
RAS
CAS
36
WE
BS
AP
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr tSREX DQM
Hi-Z
tRC
DQ
All Banks must be idle
Self Refresh Entry
Begin Self Refresh Exit Command Self Refresh Exit Command issued Self Refresh Exit
Any Command
\
14. Auto Refresh (CBR)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 4, CAS Latency = 2
T17 T18 T19 T20 T21 T22
CLK tCK2 CKE
CS
RAS
CAS
37
WE
BS
AP
RAx
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr tRP tRC
(Minimum Interval)
RAx
CAx
DQM
Hi-Z
tRC
DQ
Ax0
Ax1
Ax2
Ax3
Precharge Command All Banks
Auto Refresh Command
Auto Refresh Command
Activate Command Bank A
Read Command Bank A
\
15.1 Random Column Read (Page within same Bank)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 4, CAS Latency = 2
T17 T18 T19 T20 T21 T22
CLK tCK2 CKE
CS
RAS
CAS
38
WE
BS
AP
RAw
RAz
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr
RAw
CAw
CAx
CAy
RAz
CAz
DQM
Hi-Z
DQ
Aw0
Aw1
Aw2
Aw3
Ax0
Ax1
Ay0
Ay1
Ay2
Ay3
Az0
Az1
Az2
Az3
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
\
15.2 Random Column Read (Page within same Bank)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 4, CAS Latency = 3
T17 T18 T19 T20 T21 T22
CLK tCK3 CKE
CS
RAS
CAS
39
WE
BS
AP
RAw
RAz
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr
RAw
CAw
CAx
CAy
RAz
CAz
DQM
Hi-Z
DQ
Aw0
Aw1
Aw2
Aw3
Ax0
Ax1
Ay0
Ay1
Ay2
Ay3
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
\
16.1 Random Column Write (Page within same Bank)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 4, CAS Latency = 2
T17 T18 T19 T20 T21 T22
CLK tCK2 CKE
CS
RAS
CAS
40
WE
BS
AP
RBz
RBz RAw
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr
RBz
CBz
CBx
CBy
RBz RAw
CBz CAx
DQM
Hi-Z
DQ
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2 DBz3
Activate Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B
16.2 Random Column Write (Page within same Bank)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 4, CAS Latency = 3
T17 T18 T19 T20 T21 T22
CLK tCK3 CKE
CS
RAS
CAS
41
WE
BS
AP
RBz
RBz
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr
RBz
CBz
CBx
CBy
RBz
CBz
DQM
Hi-Z
DQ
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1
Activate Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B
17.1 Random Row Read (Interleaving Banks) with Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 8, CAS Latency = 2
T17 T18 T19 T20 T21 T22
CLK tCK2 CKE
High
CS
RAS
CAS
42
WE
BS
AP
RBx
RAx
RBy
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr
RBx
CBx
RAx
CAx
RBy
CBy
DQM
Hi-Z
tRCD
tAC2
tRP
DQ
Bx0
Bx1
Bx2
Bx3
Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
By0
By1
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Precharge Command Bank B Read Command Bank A
Activate Command Bank B
Read Command Bank B
17.2 Random Row Read (Interleaving Banks) with Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 8, CAS Latency = 3
T17 T18 T19 T20 T21 T22
CLK tCK3 CKE
High
CS
RAS
CAS
43
WE
BS
AP
RBx
RAx
RBy
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr
RBx
CBx
RAx
CAx
RBy
CBy
DQM
Hi-Z
tRCD
tAC3
tRP
DQ
Bx0
Bx1
Bx2
Bx3
Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
By0
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Read Command Bank A
Precharge Command Bank B
Activate Command Bank B
Read Command Bank B
Precharge Command Bank A
18.1 Random Row Write (Interleaving Banks) with Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 8, CAS Latency = 2
T17 T18 T19 T20 T21 T22
CLK tCK2 CKE
High
CS
RAS
CAS
44
WE
BS
AP
RAx
RBx
RAy
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr
RAx
CAX CAy
RBx
CBx
RAy
CAy
tRCD DQM
Hi-Z
tWR
tRP
tWR
DQ
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B Precharge Command Bank A
Activate Command Bank A
Write Command Bank A Precharge Command Bank B
18.2 Random Row Write (Interleaving Banks) with Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 8, CAS Latency = 3
T17 T18 T19 T20 T21 T22
CLK tCK3 CKE
High
CS
RAS
CAS
45
WE
BS
AP
RAx
RBx
RAy
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr
RAx
CAX
RBx
CBx
RAy
CAy
tRCD DQM
Hi-Z
tWR
tRP
tWR
DQ
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B
Precharge Command Bank A
Activate Command Bank A
Write Command Bank A
Precharge Command Bank B
\
19. Precharge Termination of a Burst
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 8 , CAS Latency = 2
T17 T18 T19 T20 T21 T22
CLK tCK2 CKE
High
CS
RAS
CAS
46
WE
BS
AP
RAx
RAy
RAz
HYB39S256400/800/160AT 256 MBit Synchronous DRAM
Addr
RAx
CAx
RAy
CAy
RAz
CAz
tRP DQM
Hi-Z
tRP
tRP
DQ
DAx0 DAx1 DAx2 DAx3
Ay0
Ay1
Ay2
Az0
Az1
Az2
Activate Command Bank A
Write Precharge Command Command Bank A Bank A Precharge Termination of a Write Burst. Write data is masked.
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Precharge Termination of a Read Burst.

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