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CS5345 105 dB, 24-Bit, 192 kHz Stereo Audio ADC
A/D Features
Multi-bit Delta Sigma modulator 105 dB dynamic range -95 dB THD+N Stereo 6:1 Input Multiplexer Programmable Gain Amplifier (PGA)
- +/- 12 dB gain, 0.5 dB step size - Zero crossing, click-free transitions
General Description
The CS5345 integrates an analog multiplexer, programmable gain amplifier, and stereo audio analog-to-digital converter. The CS5345 performs stereo analog-to-digital (A/D) conversion of up to 24-bit serial values at sample rates up to 192 kHz. A 6:1 stereo input multiplexer is included for selecting between line level or microphone level inputs. The microphone input path includes a +32 dB gain stage and a low noise bias voltage supply. The PGA is available for line or microphone inputs and provides gain/attenuation of 12 dB in 0.5 dB steps. The output of the PGA is followed by an advanced 5thorder, multi-bit delta sigma modulator and digital filtering/decimation. Sampled data is transmitted by the serial audio interface at rates from 4 kHz to 192 kHz in either slave or master mode. Integrated level translators allow easy interfacing between the CS5345 and other devices operating over a wide range of logic levels.
Stereo microphone inputs
- +32 dB gain stage - Low noise bias supply
Up to 192 kHz sampling rates Selectable serial audio interface formats
- Left justified up to 24-bit - IS up to 24-bit
High pass filter or DC offset calibration
System Features
Power down mode +3.3 V to +5 V analog power supply, nominal +3.3 V to +5 V digital power supply, nominal Direct interface with 1.8 V to 5 V logic levels ORDERING INFORMATION CS5345-CQZ -10 to 70 C Pin-compatible with CS4245 CDB5345
3.3 V to 5 V 3.3 V to 5 V
48-pin LQFP Evaluation Board
1.8 V to 5 V
Leve l T ranslator
IC /S P I C ontrol D ata Inte rrupt O ve rflow Re se t
Re gister C onfigura tion
Inte rna l V oltage Re fe rence
Left P G A O utput R ight P G A O utput S tere o Input 1 S tere o Input 2 S tere o Input 3 PGA MU X PG A
+32 d B
P C M S erial Inte rfa ce
H igh P a ss F ilte r
Line a r P hase A nti-A lias F ilte r
Multibit O versa mpling A DC Multibit O ve rsa mpling ADC
S e rial A udio O utput
Le ve l T ra nsla tor
S tere o Input 4 / Mic Input 1 & 2
H igh P a ss F ilte r
Line a r P hase A nti-A lias F ilte r
+32 d B
S tere o Input 5 S tere o Input 6
Advance Product Information
Cirrus Logic, Inc. www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2004 (All Rights Reserved)
(c)
JUNE `04 DS658A1 1
CS5345
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................... 3 2. CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 5 SPECIFIED OPERATING CONDITIONS ................................................................................. 5 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5 ADC ANALOG CHARACTERISTICS ....................................................................................... 6 ADC ANALOG CHARACTERISTICS ....................................................................................... 8 ADC DIGITAL FILTER CHARACTERISTICS ........................................................................... 9 PGAOUT ANALOG CHARACTERISTICS.............................................................................. 10 PGAOUT ANALOG CHARACTERISTICS (CONT'D)............................................................. 11 PGAOUT ANALOG CHARACTERISTICS (CONT'D)............................................................. 12 DC ELECTRICAL CHARACTERISTICS................................................................................. 13 DIGITAL INTERFACE CHARACTERISTICS.......................................................................... 14 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ................................................. 15 SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT ................................ 18 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................... 19 3. TYPICAL CONNECTION DIAGRAM ..................................................................................... 20 4. APPLICATIONS ..................................................................................................................... 21 4.1 Recommended Power-Up Sequence ............................................................................. 21 4.2 System Clocking ............................................................................................................. 21 4.2.1 Master Clock ...................................................................................................... 21 4.2.2 Master Mode ...................................................................................................... 22 4.2.3 Slave Mode ........................................................................................................ 22 4.3 High Pass Filter and DC Offset Calibration ..................................................................... 22 4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................. 23 4.5 Input Connections ........................................................................................................... 23 4.6 PGA Auxiliary Analog Output .......................................................................................... 23 4.7 Control Port Description and Timing ............................................................................... 24 4.7.1 SPI Mode ........................................................................................................... 24 4.7.2 IC Mode ............................................................................................................ 25 4.8 Interrupts and Overflow ................................................................................................... 27 4.9 Reset ............................................................................................................................. 27 4.10 Synchronization of Multiple Devices ............................................................................. 27 4.11 Grounding and Power Supply Decoupling .................................................................... 27 5. REGISTER QUICK REFERENCE ......................................................................................... 28 6. REGISTER DESCRIPTION ................................................................................................... 29 6.1 Chip ID - Register 01h .................................................................................................... 29 6.2 Power Control - Address 02h .......................................................................................... 29 6.3 ADC Control - Address 04h ............................................................................................ 29 6.4 MCLK Frequency - Address 05h ..................................................................................... 30 6.5 PGAOut Control - Address 06h ....................................................................................... 31 6.6 Channel A PGA Control - Address 07h ........................................................................... 31 6.7 Channel B PGA Control - Address 08h ........................................................................... 31 6.8 ADC Input Control - Address 09h ................................................................................... 32 6.9 Active Level Control - Address 0Ch ................................................................................ 33 6.10 Interrupt Status - Address 0Dh ..................................................................................... 33 6.11 Interrupt Mask - Address 0Eh ....................................................................................... 34 6.12 Interrupt Mode MSB - Address 0Fh .............................................................................. 34 6.13 Interrupt Mode LSB - Address 10h ............................................................................... 34 7. PARAMETER DEFINITIONS ................................................................................................. 35 8. PACKAGE DIMENSIONS ...................................................................................................... 36 9. THERMAL CHARACTERISTICS AND SPECIFICATIONS ................................................. 36 Appendix A: Filter Plots ....................................................................................................... 37
2
CS5345
1. PIN DESCRIPTIONS
SDOUT
DGND
MCLK
LRCK
OVFL
SCLK
48 47 46 45 44 43 42 41 40 39 38 37
SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN VLC RESET AIN3A AIN3B AIN2A AIN2B AIN1A AIN1B
TSTI
INT
NC
NC
NC
VD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
AIN4A/MICIN1 AIN4B/MICIN2 AFILTA AFILTB FILT+ AIN5A AGND AIN5B VA TSTO TSTO VQ
36 35 34 33 32
VLS TSTO NC NC AGND AGND VA PGAOUTB PGAOUTA AIN6B AIN6A MICBIAS
CS5345
31 30 29 28 27 26 25
Pin Name
SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN VLC RESET AIN3A AIN3B AIN2A AIN2B
# 1 2 3 4 5 6 7, 8 9, 10
Pin Description
Serial Control Data (Input/Output) - SDA is a data I/O in I2C mode. CDOUT is the output data line for the control port interface in SPI mode. Serial Control Port Clock (Input) - Serial clock for the serial control port. Address Bit 0 (I2C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I2C mode; CS is the chip select signal for SPI format. Address Bit 1 (I2C) / Serial Control Data Input (SPI) (Input) - AD1 is a chip address pin in I2C mode; CDIN is the input data line for the control port interface in SPI mode. Control Port Power (Input) - Determines the required signal level for the control port interface. Refer to the Recommended Operating Conditions for appropriate voltages. Reset (Input) - The device enters a low power mode when this pin is driven low. Stereo Analog Input 3 (Input) - The full scale level is specified in the ADC Analog Characteristics specification table. Stereo Analog Input 2 (Input) - The full scale level is specified in the ADC Analog Characteristics specification table.
3
CS5345
AIN1A AIN1B AGND VA AFILTA AFILTB VQ TSTO FILT+ TSTO AIN4A/MICIN1 AIN4B/MICIN2 AIN5A AIN5B MICBIAS AIN6A AIN6B PGAOUTA PGAOUTB VA AGND NC TSTO VLS TSTI NC SDOUT SCLK LRCK MCLK DGND VD INT OVFL
11, Stereo Analog Input 1 (Input) - The full scale level is specified in the ADC Analog Characteristics 12 specification table. 13 14 15 16 17 18 19 20
Analog Ground (Input) - Ground reference for the internal analog section. Analog Power (Input) - Positive power for the internal analog section. Antialias Filter Connection (Output) - Antialias filter connection for the channel A ADC input. Antialias Filter Connection (Output) - Antialias filter connection for the channel B ADC input. Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. Test Pin (Output) - This pin must be left unconnected. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Test Pin - This pin must be left unconnected.
21, Stereo Analog Input 4 / Microphone Input 1 & 2 (Input) - The full scale level is specified in the ADC 22 Analog Characteristics specification table. 23, Stereo Analog Input 5 (Input) - The full scale level is specified in the ADC Analog Characteristics 24 specification table. 25
Microphone Bias Supply (Output) - Low noise bias supply for external microphone. Electrical characteristics are specified in the DC Electrical Characteristics specification table.
26, Stereo Analog Input 6 (Input) - The full scale level is specified in the ADC Analog Characteristics 27 specification table. 28, PGA Analog Audio Output (Output) - Either an analog output from the PGA block or high impedance. 29 See "PGAOut Source Select (Bit 6)" on page 31. 30
Analog Power (Input) - Positive power for the internal analog section.
31, Analog Ground (Input) - Ground reference for the internal analog section. 32 33, No Connect - These pins are not connected internally and should be tied to ground to minimize any 34 potential coupling effects. 35 36 37
Test Pin (Output) - This pin must be left unconnected. Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages. Test Pin (Input) - This pin must be connected to ground.
38, No Connect - These pins are not connected internally and should be tied to ground to minimize any 39, potential coupling effects. 40 41 42 43 44 45 46 47 48
Serial Audio Data Output (Output) - Output for two's complement serial audio data. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input/Output) -Clock source for the ADC's delta-sigma modulators. Digital Ground (Input) - Ground reference for the internal digital section. Digital Power (Input) - Positive power for the internal digital section. Interrupt (Output) - Indicates an interrupt condition has occurred. Overflow (Output) - Indicates an ADC overflow condition is present.
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CS5345
2. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25C.)
SPECIFIED OPERATING CONDITIONS (AGND = DGND = 0 V; All voltages with respect to
ground.) Parameters Analog Digital Logic - Serial Port Logic - Control Port Ambient Operating Temperature (Power Applied) DC Power Supplies: Symbol VA VD VLS VLC TA Min 3.1 3.1 1.71 1.71 -10 Nom 5.0 3.3 3.3 3.3 Max 5.25 5.25 5.25 5.25 +70 Units V V V V C
ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V All voltages with respect to ground.) (Note
1) Parameter DC Power Supplies: Analog Digital Logic - Serial Port Logic - Control Port (Note 2) Symbol VA VD VLS VLC Iin VINA Logic - Serial Port VIND-S Logic - Control Port VIND-C TA Tstg Min -0.3 -0.3 -0.3 -0.3 AGND-0.3 -0.3 -0.3 -20 -65 Typ Max +6.0 +6.0 +6.0 +6.0 10 VA+0.3 VLS+0.3 VLC+0.3 +85 +150 Units V V V V mA V V V C C
Input Current Analog Input Voltage Digital Input Voltage
Ambient Operating Temperature (Power Applied) Storage Temperature
Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up.
5
CS5345
ADC ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Fs = 48/96/192 kHz. Line Level Inputs Parameter Dynamic Performance for VA = 5 V Dynamic Range PGA Setting: -12 dB to +6 dB A-weighted unweighted (Note 4) 40 kHz bandwidth unweighted PGA Setting: +12 dB Gain A-weighted unweighted (Note 4) 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 3) PGA Setting: -12 dB to +6 dB -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Symbol Min Typ Max Unit
99 96 -
105 102 99
-
dB dB dB
93 90 THD+N
99 96 93
-
dB dB dB
(Note 4)
-
-95 -82 -42 -92
-89 -
dB dB dB dB
PGA Setting: +12 dB Gain -1 dB -20 dB -60 dB (Note 4) 40 kHz bandwidth -1 dB Dynamic Performance for VA = 3.3 V Dynamic Range PGA Setting: -12 dB to +6 dB A-weighted unweighted (Note 4) 40 kHz bandwidth unweighted PGA Setting: +12 dB Gain A-weighted unweighted 40 kHz bandwidth unweighted
-
-92 -76 -36 -89
-86 -
dB dB dB dB
94 91 -
102 99 96
-
dB dB dB
(Note 4)
90 87 -
96 93 90
-
dB dB dB
6
CS5345
Total Harmonic Distortion + Noise (Note 3) THD+N
(Note 4)
PGA Setting: -12 dB to +6 dB -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB PGA Setting: +12 dB Gain -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Line Level Inputs Symbol
-
-92 -79 -39 -84
-86 -
dB dB dB dB
(Note 4)
Min 0.53*VA 6.12 -
-89 -73 -33 -81 Typ 90 0.56*VA 6.8 5
-83 Max 0.59*VA 7.48 -
dB dB dB dB Unit dB Vpp k %
Parameter Interchannel Isolation Line Level Input Characteristics Full-scale Input Voltage Input Impedance Maximum Interchannel Input Impedance Mismatch
Line Level and Microphone Level Inputs Parameter DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Programmable Gain Characteristics Gain Step Size Absolute Gain Step Error Symbol Min Typ 0.1 Max Unit dB % ppm/C dB dB
100
0.5 -
5
0.4
7
CS5345
ADC ANALOG CHARACTERISTICS
Parameter Dynamic Performance for VA = 5 V Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 3) PGA Setting: -12 dB to 0 dB -1 dB -20 dB -60 dB PGA Setting: +12 dB -1 dB Dynamic Performance for VA = 3.3 V Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 3) PGA Setting: -12 dB to 0 dB -1 dB -20 dB -60 dB PGA Setting: +12 dB -1 dB Interchannel Isolation Microphone Level Input Characteristics Full-scale Input Voltage Input Impedance 3. Referred to the typical line level full-scale input voltage 4. Valid for Double and Quad Speed Modes only. (cont)
Microphone Level Inputs Symbol Min Typ Max Unit
77 74
83 80
-
dB dB
65 62 THD+N
71 68
-
dB dB
-
-80 -60 -20
-74 -
dB dB dB
-
-68
-
dB
77 74
83 80
-
dB dB
65 62 THD+N
71 68
-
dB dB
-
-80 -60 -20
-74 -
dB dB dB
0.013*VA -
-68 30 0.014*VA 100
0.015*VA -
dB dB Vpp k
8
CS5345
ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Note 5, 7) Single Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Double Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Quad Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) High Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time Note: 5. Filter response is guaranteed by design. 6. Response shown is for Fs equal to 48 kHz. 7. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 13 to 24) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. -3.0 dB -0.13 dB @ 20Hz (Note 6) (Note 6) 1 20 10 10 /Fs
5
Symbol
Min 0 0.5688 70
Typ 12/Fs 9/Fs 5/Fs
Max 0.4896 0.035 0.4896 0.025 0.2604 0.025 0
Unit Fs dB Fs dB s Fs dB Fs dB s Fs dB Fs dB s Hz Hz Deg dB s
(-0.1 dB)
tgd
0 0.5604 69
(-0.1 dB)
tgd
0 0.5000 60
(-0.1 dB)
tgd
-
9
CS5345
PGAOUT ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): Synchronous mode, Fs = 48/96/192 kHz. Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. VA = 5 V Parameter Symbol Dynamic Performance with PGA Line Level Input Selected Dynamic Range (Note 8) PGA Setting: -12 dB to +6 dB A-weighted unweighted PGA Setting: +12 dB Gain A-weighted unweighted Total Harmonic Distortion + Noise (Note 8) THD+N PGA Setting: -12 dB to +12 dB -1 dB -20 dB -60 dB Dynamic Performance with PGA Mic Level Input Selected Dynamic Range (Note 8) PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 8) PGA Setting: -12 dB to 0 dB -1 dB -20 dB -60 dB PGA Setting: +12 dB -1 dB Min Typ Max Unit
99 96
105 102
-
dB dB
93 90
99 96
-
dB dB
-
-80 -82 -42
-74 -
dB dB dB
77 74
83 80
-
dB dB
65 62 THD+N -
71 68
-
dB dB
-74 -60 -20
-68 -
dB dB dB
-
-68
-
dB
Notes: 8. Referred to the typical PGAOUT Full-Scale Output Voltage.
10
CS5345
PGAOUT ANALOG CHARACTERISTICS (CONT'D)
VA = 3.3 V Parameter Symbol Dynamic Performance with PGA Line Level Input Selected Dynamic Range PGA Setting: -12 dB to +6 dB A-weighted unweighted PGA Setting: +12 dB Gain A-weighted unweighted Total Harmonic Distortion + Noise (Note 8) THD+N PGA Setting: -12 dB to +12 dB -1 dB -20 dB -60 dB Dynamic Performance with PGA Mic Level Input Selected Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 8) PGA Setting: -12 dB to 0 dB -1 dB -20 dB -60 dB PGA Setting: +12 dB -1 dB Min Typ Max Unit
94 91
102 99
-
dB dB
90 87
96 93
-
dB dB
-
-80 -82 -42
-74 -
dB dB dB
77 74
83 80
-
dB dB
65 62 THD+N -
71 68
-
dB dB
-74 -60 -20
-68 -
dB dB dB
-
-68
-
dB
11
CS5345
PGAOUT ANALOG CHARACTERISTICS (CONT'D)
VA = 5 V or 3.3 V Parameter DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Analog Output Full-Scale Output Voltage Frequency Response 10 Hz to 20 kHz Analog In to Analog Out Phase Shift DC Current draw from a PGAOUT pin AC-Load Resistance Load Capacitance Output Impedance Symbol Min -0.1dB 100 Typ 0.1 Max VA +0.1dB 1 20 Unit dB % ppm/C Vpp dB deg A k pF k
5 100
0.56*VA 180 1
IOUT RL CL ZOUT
12
CS5345
DC ELECTRICAL CHARACTERISTICS (AGND = DGND = 0 V, all voltages with respect to
ground. MCLK=12.288 MHz; Fs=48 kHz, Master Mode) Parameter Power Supply Current (Normal Operation) VA = 5 VA = 3.3 VD, VLS, VLC = 5 VD, VLS, VLC = 3.3 V V V V Symbol IA IA ID ID IA ID PSRR VQ (Note 11) IQ ZQ FILT+ MICBIAS IMB Min Typ 41 37 39 23 0.30 0.54 400 198 4.2 60 0.5 x VA 23 VA 0.8 x VA Max 50 45 47 28 485 241 1 2 Unit mA mA mA mA mA mA mW mW mW dB VDC A k VDC VDC mA
Power Supply Current. (Power-Down Mode) (Note 9). Power Consumption (Normal Operation). (Power-Down Mode). VQ Characteristics Quiescent Voltage DC Current from VQ VQ Output Impedance FILT+ Nominal Voltage Microphone Bias Voltage Current from MICBIAS
VA = 5 V VLS, VLC, VD=5 V
VA, VD, VLS, VLC = 5 V VA, VD, VLS, VLC = 3.3 V VA, VD, VLS, VLC = 5 V (1 kHz) (Note 10)
Power Supply Rejection Ratio
Notes: 9. Power Down Mode is defines as RESET = Low with all clock and data lines held static and no analog input. 10. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram. 11. Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage through the electrolytic de-coupling capacitors.
13
CS5345
DIGITAL INTERFACE CHARACTERISTICS
Parameters (Note 12) High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at Io=2 mA Symbol VIH Serial Port VIH Control Port VIL Serial Port VIL Control Port Serial Port VOH Control Port VOH Serial Port Control Port VOL VOL Iin (Note 13) Min 0.7xVLS 0.7xVLC VLS-1.0 VLC-1.0 10 ---------------LRCK
6
Typ -
Max 0.2xVLS 0.2xVLC 0.4 0.4 10 1 -
Units V V V V V V V V A pF s
Low-Level Output Voltage at Io=2 mA
Input Leakage Current Input Capacitance Minimum OVFL Active Time
Notes: 12. Serial Port signals include: MCLK, SCLK, LRCK, SDOUT Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, RESET, INT, OVFL. 13. Guaranteed by design.
14
CS5345
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic `0' = DGND = 0 V;
Logic `1' = VL, CL = 20 pF) (Note 14) Parameter Sample Rate Single Speed Mode Double Speed Mode Quad Speed Mode Symbol Fs Fs Fs fmclk tclkhl Min 4 50 100 1.024 8 tslr tsdo -10 0 40 Single Speed Mode Double Speed Mode Quad Speed Mode SCLK Pulse Width High SCLK Pulse Width Low SCLK falling to LRCK edge SCLK falling to SDOUT valid Notes: 14. See Figures 1 and 2 on page 16. tsclkw tsclkw tsclkw tsclkh tsclkl tslr tsdo
10 -------------------( 128 )Fs 10 ----------------( 64 )Fs 10 ----------------( 64 )Fs
9 9 9
Typ 50 50 50 -
Max 50 100 200 51.200 10 32 60 10 32
Unit kHz kHz kHz MHz ns % % ns ns % ns ns ns ns ns ns ns
MCLK Specifications MCLK Frequency MCLK Input Pulse Width High/Low Master Mode LRCK Duty Cycle SCLK Duty Cycle SCLK falling to LRCK edge SCLK falling to SDOUT valid Slave Mode LRCK Duty Cycle SCLK Period
30 48 -10 0
15
CS5345
LRCK Output
t SCLK Output t SDOUT
slr
sdo
Figure 1. Master Mode Serial Audio Port Timing
LRCK Input t sclkh t
t SCLK Input t SDOUT
slr
sclkl
sdo
t sclkw
Figure 2. Slave Mode Serial Audio Port Timing
16
CS5345
LRC K SCLK
L eft C A - Left Channel h a n ne l
Channel a - Right R ig h t C hB n n el
SDATA
M SB -1 -2 -3 -4 -5
+5 +4 +3 + 2 +1 LS B
M SB -1 -2 -3 -4
+5 +4 + 3 +2 +1 LSB
Figure 3. Format 0, Left Justified up to 24-Bit Data
LR C K SCLK
Channel h a n n el Le ft C A - Left
RChannelha n n el ig h t C B - Right
SDATA
MSB -1 -2 -3 -4 -5
+5 + 4 +3 +2 + 1 LSB
MSB -1 -2 -3 -4
+ 5 +4 + 3 +2 +1 LS B
Figure 4. Format 1, IS up to 24-Bit Data
17
CS5345
SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT
(Inputs: Logic 0 = DGND, Logic 1 = VLC, CL = 30 pF) Parameter SCL Clock Frequency RESET Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 16) (Note 16) (Note 15) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 Max 100 1 300 1000 Unit kHz ns s s s s s s ns s ns s ns
Notes: 15. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 16. Guaranteed by design.
RST t S to p irs S t a rt R e p e a te d S t a rt t rd t fd S top
SDA t bu f t h ds t t h igh t h ds t t fc t su sp
SCL t t t t t s u st t rc
lo w
hd d
sud
a ck
Figure 5. Control Port Timing - IC Format
18
CS5345
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = DGND, Logic 1 = VLC, CL = 30 pF) Parameter CCLK Clock Frequency RESET Rising Edge to CS Falling. CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 18) (Note 18) (Note 17) Symbol fsck tsrs tcsh tcss tscl tsch tdsu tdh tpd tr1 tf1 tr2 tf2 Min 0 500 1.0 20 66 66 40 15 Typ Max 6.0 ns 50 25 25 100 100 s ns ns ns ns ns ns ns ns ns ns Units MHz
Notes: 17. Data must be held for sufficient time to bridge the transition time of CCLK. 18. For fsck <1 MHz.
RST
t srs
CS t css CCLK t r2 CDIN t dsu t dh t f2 t scl t sch t csh
t pd
CDOUT
Figure 6. Control Port Timing - SPI Format
19
CS5345
3. TYPICAL CONNECTION DIAGRAM
+3.3V to +5V 10 F 0.1 F 0.1 F 0.1 F 10 F
+3.3V to +5V
VD +1.8V to +5V 0.1 F VLS
VA
VA
3.3 F
PGAOUTA
3.3 F
MCLK Digital Audio Capture SCLK LRCK SDOUT
PGAOUTB AIN1A
1800 pF *
10 F 100
Left Analog Input 1
100 k 100 k
AIN1B INT OVFL RESET MicroController SCL/CCLK SDA/CDOUT AD1/CDIN AD0/CS 2 k +1.8V to +5V
See Note 1
1800 pF
*
10 F
100
Right Analog Input 1 Left Analog Input 2
100 k 100 k
AIN2A
1800 pF *
10 F 100
AIN2B AIN3A
1800 pF
*
10 F
100
Right Analog Input 2 Left Analog Input 3
100 k 100 k
1800 pF *
10 F 100
2 k VLC 0.1 F
AIN3B AIN4A/MICIN1
1800 pF
*
10 F
100
Right Analog Input 3 Left Analog Input 4
100 k 100 k
1800 pF *
10 F 100
AIN4B/MICIN2 NC NC NC NC NC TSTI TSTO TSTO TSTO AIN5A
1800 pF
*
10 F
100
Right Analog Input 4 Left Analog Input 5
100 k 100 k
Note 1: Resistors are required for IC control port operation
1800 pF *
10 F 100
AIN5B AIN6A
1800 pF
*
10 F
100
Right Analog Input 5 Left Analog Input 6
100 k 100 k
Note 2 The value of RL is dictated by the microphone carteridge.
1800 pF *
10 F 100
AIN6B MICBIAS
1800 pF
*
10 F
100
Right Analog Input 6
See Note 2
VQ FILT+ 10 F 0.1 F 47 F 0.1 F AGND DGND
AGND AGND AFILTA AFILTB
47 F *
RL
* 2.2nF 2.2nF
* Capacitors must be C0G or equivalent
Figure 7. Typical Connection Diagram
RL
20
CS5345
4. APPLICATIONS 4.1 Recommended Power-Up Sequence
1) Hold RESET low until the power supply, MCLK, and LRCK are stable. In this state, the Control Port is reset to its default settings. 2) Bring RESET high. The device will remain in a low power state with the PDN bit set by default. The control port will be accessible. 3) The desired register settings can be loaded while the PDN bit remains set. 4) Clear the PDN bit to initiate the power-up sequence.
4.2
System Clocking
The CS5345 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed modes as shown in Table 1 below. Mode Single Speed Double Speed Quad Speed Sampling Frequency 4-50 kHz 50-100 kHz 100-200 kHz
Table 1. Speed Modes
4.2.1
Master Clock
MCLK/LRCK must maintain an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked out of the device. The FM bits (see page 30) and the MCLK Freq bits (see page 30) configure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and LRCK frequencies.
21
CS5345
LRCK (kHz) 32 44.1 48 64 88.2 96 128 176.4 192 Mode
MCLK (MHz) 64x 8.1920 11.2896 12.2880 96x 12.2880 16.9344 18.4320 128x 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 QSM Table 2. Common Clock Frequencies 192x 12.2880 16.9344 18.4320 24.5760 33.8680 36.8640 256x 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 32.7680 45.1584 49.1520 384x 12.2880 16.9344 18.4320 24.5760 33.8680 36.8640 DSM 512x 16.3840 22.5792 24.5760 32.7680 45.1584 49.1520 768x 24.5760 33.8680 36.8640 SSM 1024x 32.7680 45.1584 49.1520 -
4.2.2
Master Mode
As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 8.
MC LK F req Bits /256 /1 /1.5 MC LK /2 /3 /4 000 001 010 011 100 /1 10 /4 /2 /128 /64 F M Bits 00 01 SC LK 00 01 10 LR C K
Figure 8. Master Mode Clocking
4.2.3
Slave Mode
In Slave mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sample rate, Fs, and must be synchronously derived from the supplied master clock, MCLK. The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to 128x, 64x, 48x or 32x Fs depending on the desired speed mode. Refer to Table 3 for required clock ratios. Single Speed SCLK/LRCK Ratio 32x, 48x, 64x, 128x Double Speed 32x, 48x, 64x Quad Speed 32x, 48x, 64x
Table 3. Slave Mode Serial Bit Clock Ratios
4.3
High Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS5345, a small DC offset may be driven into the A/D converter. The CS5345 includes a high pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding clicks when switching between devices in a multichannel system.
22
CS5345
The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the HPFFreeze bit (see page 30) is set during normal operation, the current value of the DC offset for the each channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1) Running the CS5345 with the high pass filter enabled until the filter settles. See the Digital Filter Characteristics section for filter settling time. 2) Disabling the high pass filter and freezing the stored DC offset. A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS5345.
4.4
Analog Input Multiplexer, PGA, and Mic Gain
The CS5345 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier (PGA). The input multiplexer can select one of 6 possible stereo analog input sources and route it to the PGA. Analog inputs 4A and 4B are able to insert a +32 dB gain stage before the input multiplexer, allowing them to be used for microphone level signals without the need for any external gain. The PGA stage provides 12 dB of gain or attenuation in 0.5 dB steps. Figure 9 shows the architecture of the input multiplexer, PGA, and mic gain stages.
AIN1A AIN2A AIN3A AIN4A/MICIN1 MUX
+32 dB
PGA
Out to ADC Channel A
AIN5A AIN6A Analog Input Selection Bits AIN1B AIN2B AIN3B AIN4B/MICIN2 MUX
+32 dB
Channel A PGA Gain Bits
Channel B PGA Gain Bits
PGA
Out to ADC Channel B
AIN5B AIN6B
Figure 9. Analog Input Architecture
The "Analog Input Selection (Bits 2:0)" section on page 33 outlines the bit settings necessary to control the input multiplexer and mic gain. "Channel A PGA Control - Address 07h" on page 31 and "Channel B PGA Control - Address 08h" on page 31 outlines the register settings necessary to control the PGA. By default, line level input 1 is selected, and the PGA is set to 0 dB.
4.5
Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n x 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
4.6
PGA Auxiliary Analog Output
23
CS5345
The CS5345 includes an auxiliary analog output through the PGAOUT pins. These pins can be configured to output the analog input to the ADC as selected by the input MUX and gained or attenuated with the PGA, or alternatively, they may be set to high-impedance. See the "PGAOut Source Select (Bit 6)" section on page 31 for information on configuring the PGA auxiliary analog output. The PGA auxiliary analog output can source very little current. As current from the PGAOUT pins increases, distortion will increase. For this reason, a high input impedance buffer must be used on the PGAOUT pins to achieve full performance. Refer to the PGAOUT Analog Characteristics table on page 12 for acceptable loading conditions.
4.7
Control Port Description and Timing
The control port is used to access the registers, allowing the CS5345 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI and IC, with the CS5345 acting as a slave device. SPI mode is selected if there is a high to low transition on the AD0/CS pin, after the RESET pin has been brought high. IC mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently selecting the desired AD0 bit address state.
4.7.1
SPI Mode
In SPI mode, CS is the CS5345 chip select signal, CCLK is the control port bit clock (input into the CS5345 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge. Figure 10 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 k resistor, if desired. There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers. To read a register, the MAP has to be set to the correct address by executing a partial write cycle which finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not, as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. The next falling edge of CCLK
24
CS5345
will clock out the MSB of the addressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will appear consecutively.
CS
CCLK C H IP ADDRESS C D IN C H IP AD D R ESS LSB b y te n MSB LSB MSB LSB
M AP R/W MSB
DATA
1001111
1001111
R/W
b y te 1
High Impedance
CD OUT
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 10. Control Port Timing in SPI Mode
4.7.2
IC Mode
In IC mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the CS5345 is being reset. The signal timings for a read and write cycle are shown in Figure 11 and Figure 12. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS5345 after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS5345, the chip address field, which is the first byte sent to the CS5345, should match 10011 followed by the settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS5345 after each input byte is read, and is input to the CS5345 from the microcontroller after each transmitted byte.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
DATA
2 1 0 7 6 1 0 7
DATA +1
6 1 0 7
DATA +n
6 1 0
SDA
START
1
0
0
1
1 AD1 AD0 0
6
5
4
3
ACK
ACK
ACK
ACK STOP
Figure 11. Control Port Timing, IC Write
25
CS5345
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
STOP
1 0 1
CHIP ADDRESS (READ)
0 0 1 1 AD1 AD0 1
DATA
7 0
DATA +1
7 0
DATA + n
7 0
SDA
1
0
0
1
1 AD1 AD0 0
6
5
4
3
2
ACK START
ACK START
ACK
ACK
NO ACK
STOP
Figure 12. Control Port Timing, IC Read
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown in Figure 12, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition. Send 10011xx0 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 10011xx1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
26
CS5345
4.8 Interrupts and Overflow
The CS5345 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt input pin on the host microcontroller. The INT pin may function as either an active high CMOS driver or an active low opendrain driver (see "Active High/Low (Bit 0)" on page 33). When configured as active low open-drain, the INT pin has no active pull-up transistor, allowing it to be used for wired-OR hook-ups with multiple peripherals connected to the microcontroller interrupt input pin. In this configuration, an external pull-up resistor must be placed on the INT pin for proper operation. Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See "Interrupt Status - Address 0Dh" on page 33. Each source may be masked off through mask register bits. In addition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the equipment designer. The CS5345 also has a dedicated overflow output. The OVFL pin functions as active low open drain and has no active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs an OR of the ADCOverflow and ADCUnderflow conditions available in the Interrupt Status register, however, these conditions do not need to be unmasked for proper operation of the OVFL pin.
4.9
Reset
When RESET is low, the CS5345 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are muted. When RESET is high, the control port becomes operational and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control register will then cause the part to leave the low power state and begin operation. The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by setting the RESET pin high. However, the voltage reference will take much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. During this voltage reference ramp delay, SDOUT will be automatically muted. It is recommended that RESET be activated if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues.
4.10 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the master clocks and left/right clocks must be the same for all of the CS5345's in the system. If only one master clock source is needed, one solution is to place one CS5345 in Master Mode, and slave all of the other CS5345's to the one master. If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS5345 reset with the inactive edge of master clock. This will ensure that all converters begin sampling on the same clock edge.
4.11 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS5345 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 7 shows the recommended power arrangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the system logic supply (VLS or VLC) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices should be powered from VD. Power supply decoupling capacitors should be as near to the CS5345 as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and AGND. The CS5345 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the CS5345 digital outputs only to CMOS inputs.
27
CS5345
5. REGISTER QUICK REFERENCE
This table shows the register names and their associated default values. Addr Function 7
PART3 1 02h Power Control 03h Reserved 04h ADC Control 05h MCLK Frequency 06h PGAOut Control Freeze 0 0 FM1 0 Reserved 0 Reserved 0
6
PART2 1 0 0 FM0 0 MCLK Freq2 0 PGAOut 1
5
PART1 1 0 0 Reserved 0 MCLK Freq1 0 Reserved 0 Gain5 0 Gain5 0
4
PART0 0 Reserved 0 Reserved 0 DIF 0 MCLK Freq0 0 Reserved 0 Gain4 0 Gain4 0 PGASoft 1 Reserved 0 Reserved 0 EFTC 0 EFTCM 0 EFTC1 0 EFTC1 0
3
REV3 0 PDN_MIC 0 Reserved 1 Reserved 0 Reserved 0 Reserved 0 Gain3 0 Gain3 0 PGAZero 1 Reserved 0 Reserved 0 ClkErr 0 ClkErrM 0 ClkErr1 0 ClkErr1 0
2
REV2 0 PDN_ADC 0 Reserved 0 Mute 0 Reserved 0 Reserved 0 Gain2 0 Gain2 0 Sel2 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0
1
REV1 0 Reserved 0 Reserved 0 HPFFreeze 0 Reserved 0 Reserved 0 Gain1 0 Gain1 0 Sel1 0 Reserved 0 Reserved 0 ADCOvfl 0 OvflM 0 ADCOvfl1 0 ADCOvfl1 0
0
REV0 1 PDN 1 Reserved 0 M/S 0 Reserved 0 Reserved 0 Gain0 0 Gain0 0 Sel0 1 Reserved 0 Active_H/L 0 ADCUndrfl 0 UndrflM 0 ADCUndrfl1 0 ADCUndrfl1 0
01h Chip ID
Reserved Reserved
Reserved Reserved Reserved
07h PGA Ch B Gain Reserved Reserved Control 0 0 08h PGA Ch A Gain Reserved Reserved Control 0 09h Analog Input Control 0Ah - Reserved 0Bh 0Ch Active Level Control 0
Reserved Reserved Reserved 0 0 0
Reserved Reserved Reserved 0 0 0
Reserved Reserved Reserved 1 0 1 0 0 0 0 0
0Dh Interrupt Status Reserved Reserved Reserved 0Eh Interrupt Mask 0Fh Interrupt Mode MSB 10h Interrupt Mode LSB Reserved Reserved Reserved 0
Reserved Reserved Reserved 0 0 0
Reserved Reserved Reserved 0 0 0
28
CS5345
6. 6.1 REGISTER DESCRIPTION Chip ID - Register 01h
B6 PART2 B5 PART1 B4 PART0 B3 REV3 B2 REV2 B1 REV1 B0 REV0 B7 PART3
Function:
This register is Read-Only. Bits 7 through 4 are the part number ID which is 1110b (0Eh) and the remaining bits (3 through 0) are for the chip revision.
6.2
Power Control - Address 02h
6 Reserved 5 Reserved 4 Reserved 3 PDN_MIC 2 PDN_ADC 1 Reserved 0 PDN
7 Freeze
6.2.1
Freeze (Bit 7)
Function:
This function allows modifications to be made to certain control port bits without the changes taking effect until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed in Table 4 below. Table 4. Freeze-able Bits Name Mute Gain[5:0] Gain[5:0] Register 04h 07h 08h Bit(s) 2 5:0 5:0
6.2.2
Power Down MIC (Bit 3)
Function:
The microphone preamplifier block will enter a low-power state whenever this bit is set.
6.2.3
Power Down ADC (Bit 2)
Function:
The ADC pair will remain in a reset state whenever this bit is set.
6.2.4
Power Down Device (Bit 0)
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and must be cleared before normal operation can occur. The contents of the control registers are retained when the device is in power-down.
6.3
7
ADC Control - Address 04h
6 FM0 5 Reserved 4 DIF 3 Reserved 2 Mute 1 HPFFreeze 0 M/S FM1
29
CS5345
6.3.1 Functional Mode (Bits 7:6)
Function:
Selects the required range of sample rates. Table 5. Functional Mode Selection FM1 0 0 1 1 FM0 0 1 0 1 Mode Single-Speed Mode: 4 to 50 kHz sample rates Double-Speed Mode: 50 to 100 kHz sample rates Quad-Speed Mode: 100 to 200 kHz sample rates Reserved
6.3.2
Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK, SCLK and SDOUT is defined by the Digital Interface Format bit. The options are detailed in Table 6 and may be seen in Figure 3 and 4. Table 6. Digital Interface Formats DIF 0 1
2
Description Left Justified, up to 24-bit data (default) I S, up to 24-bit data
Format 0 1
Figure 3 4
6.3.3
Mute (Bit 2)
Function:
When this bit is set, the serial audio output of the both channels will be muted.
6.3.4
High Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter will be disabled.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See "High Pass Filter and DC Offset Calibration" on page 22.
6.3.5
Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for the serial audio port. Setting this bit will select master mode, while clearing this bit will select slave mode.
6.4
7
MCLK Frequency - Address 05h
6 MCLK Freq2 5 MCLK Freq1 4 MCLK Freq0 3 Reserved 2 Reserved 1 Reserved 0 Reserved
Reserved
30
CS5345
6.4.1 Master Clock Dividers (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK signal. See Table 7 below for the appropriate settings. Table 7. MCLK Frequency MCLK Divider /1 / 1.5 /2 /3 /4 Reserved Reserved MCLK Freq2 0 0 0 0 1 1 1 MCLK Freq1 0 0 1 1 0 0 1 MCLK Freq0 0 1 0 1 0 1 x
6.5
7
PGAOut Control - Address 06h
6 PGAOut 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 Reserved
Reserved
6.5.1
PGAOut Source Select (Bit 6)
Function:
This bit is used to configure the PGAOut pins to be either high impedance or PGA outputs. Refer to Table 8 below. Table 8. PGAOut Source Selection PGAOut 0 1 PGAOutA & PGAOutB High Impedance PGA Output
6.6
Channel A PGA Control - Address 07h
6 Reserved 5 Gain5 4 Gain4 3 Gain3 2 Gain2 1 Gain1 0 Gain0
7 Reserved
6.6.1
Channel A PGA Gain (Bits 5:0)
Function:
See "Channel B PGA Gain (Bits 5:0)" on page 31.
6.7
Channel B PGA Control - Address 08h
6 Reserved 5 Gain5 4 Gain4 3 Gain3 2 Gain2 1 Gain1 0 Gain0
7 Reserved
6.7.1
Channel B PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to +12 dB in 0.5 dB steps. The gain bits are in two's complement with the Gain0 bit set for a 0.5 dB step. Register settings outside of the 12 dB range are reserved and must not be used. See Table 9 for
31
CS5345
example settings. Table 9. Example Gain and Attenuation Settings Gain[5:0] 101000 000000 011000 Setting -12 dB 0 dB +12 dB
6.8
ADC Input Control - Address 09h
6 Reserved 5 Reserved 4 PGASoft 3 PGAZero 2 Sel2 1 Sel1 0 Sel0
7 Reserved
6.8.1
PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function:
Soft Ramp Enable Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. See Table 10 on page 33. Zero Cross Enable Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 10 on page 33. Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 10 on page 33.
32
CS5345
Table 10. PGA Soft Cross or Zero Cross Mode Selection PGASoft 0 0 1 1 PGAZeroCross 0 1 0 1 Mode Changes to affect immediately Zero Cross enabled Soft Ramp enabled Soft Ramp and Zero Cross enabled (default)
6.8.2
Analog Input Selection (Bits 2:0)
Function:
These bits are used to select the input source for the PGA and ADC. Please see Table 11 below. Table 11. Analog Input Multiplexer Selection Sel2 0 0 0 0 1 1 1 1 Sel1 0 0 1 1 0 0 1 1 Sel0 0 1 0 1 0 1 0 1 PGA/ADC Input Microphone Level Inputs (+32 dB Gain Enabled) Line Level Input Pair 1 Line Level Input Pair 2 Line Level Input Pair 3 Line Level Input Pair 4 Line Level Input Pair 5 Line Level Input Pair 6 Reserved
6.9
7
Active Level Control - Address 0Ch
6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 Active_H/L
Reserved
6.9.1
Active High/Low (Bit 0)
Function:
When this bit is set, the INT pin will function as an active high CMOS driver. When this bit is cleared, the INT pin will function as an active low open drain driver and will require an external pull-up resistor for proper operation.
6.10 Interrupt Status - Address 0Dh
7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 ClkErr 2 Reserved 1 Ovfl 0 Undrfl
For all bits in this register, a `1' means the associated interrupt condition has occurred at least once since the register was last read. A `0' means the associated interrupt condition has NOT occurred since the last reading of the register. Status bits that are masked off in the associated mask register will always be `0' in this register. This register defaults to 00h.
6.10.1 Clock Error (Bit 3)
Function:
Indicates the occurrence of a clock error condition.
33
CS5345
6.10.2 Overflow (Bit 1)
Function:
Indicates the occurrence of an ADC overflow condition.
6.10.3 Underflow (Bit 0)
Function:
Indicates the occurrence of an ADC underflow condition.
6.11 Interrupt Mask - Address 0Eh
7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 ClkErrM 2 Reserved 1 OvflM 0 UndrflM
Function:
The bits of this register serve as a mask for the Status sources found in the register "Interrupt Status - Address 0Dh" on page 33. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corresponding bits in the Status register.
6.12 Interrupt Mode MSB - Address 0Fh 6.13 Interrupt Mode LSB - Address 10h
7 Reserved Reserved 6 Reserved Reserved 5 Reserved Reserved 4 Reserved Reserved 3 ClkErr1 ClkErr0 2 Reserved Reserved 1 Ovfl1 Ovfl0 0 Undrfl1 Undrfl0
Function:
The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT pin remains active during the interrupt condition. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved
34
CS5345
7. PARAMETER DEFINITIONS
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
Dynamic Range
35
CS5345
8. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
MIN --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000 * Nominal pin pitch is 0.50 mm DIM A A1 B D D1 E E1 e* L INCHES NOM MAX MIN 0.055 0.063 --0.004 0.006 0.05 0.009 0.011 0.17 0.354 0.366 8.70 0.28 0.280 6.90 0.354 0.366 8.70 0.28 0.280 6.90 0.020 0.024 0.40 0.24 0.030 0.45 4 7.000 0.00 *Controlling dimension is mm. MILLIMETERS NOM MAX 1.40 1.60 0.10 0.15 0.22 0.27 9.0 BSC 9.30 7.0 BSC 7.10 9.0 BSC 9.30 7.0 BSC 7.10 0.50 BSC 0.60 0.60 0.75 4 7.00 *JEDEC Designation: MS022
9. THERMAL CHARACTERISTICS AND SPECIFICATIONS
Parameters Package Thermal Resistance (Note 19) Allowable Junction Temperature 48-LQFP Symbol JA JC Min Typ 48 15 Max 125 Units C/Watt C/Watt C
Notes: 19. JA is specified according to JEDEC specifications for multi-layer PCBs. 36
CS5345
APPENDIX A: FILTER PLOTS
0 -10 -20 -30 0 -10 -20 -30
Amplitude (dB)
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Amplitude (dB)
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 13. Single Speed Stopband Rejection
Figure 14. Single Speed Stopband Rejection
0 -1 -2
0.10 0.08 0.06
Amplitude (dB)
Amplitude (dB)
-3 -4 -5 -6 -7 -8 -9 -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 15. Single Speed Transition Band (Detail)
Figure 16. Single Speed Passband Ripple
0 -10 -20 -30
0 -10 -20 -30
Amplitude (dB)
-80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Amplitude (dB)
-40 -50 -60 -70
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 17. Double Speed Stopband Rejection
Figure 18. Double Speed Stopband Rejection
37
CS5345
0 -1 -2
0.10 0.08 0.06
Amplitude (dB)
-3 -4 -5 -6 -7 -8 -9 -10 0.46 0.47 0.48 0.49 0.50 0.51 0.52
Amplitude (dB)
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 19. Double Speed Transition Band (Detail)
Figure 20. Double Speed Passband Ripple
0 -10 -20 -30
0 -10 -20 -30
Amplitude (dB)
-80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Amplitude (dB) Frequency (norm alized to Fs)
-40 -50 -60 -70
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Frequency (norm alized to Fs)
Figure 21. Quad Speed Stopband Rejection
Figure 22. Quad Speed Stopband Rejection
0 -1 -2 0.10 0.08 0.06
Amplitude (dB)
-3
Amplitude (dB)
0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
-4 -5 -6 -7 -8 -9 -10 0.10
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08
Frequency (norm alized to Fs)
-0.10 0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Frequency (norm alized to Fs)
Figure 23. Quad Speed Transition Band (Detail)
Figure 24. Quad Speed Passband Ripple
38
CS5345
Release A1
Date June 2004
Changes Initial Release Table 12. Revision History
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I2C is a registered trademark of Philips Semiconductor. Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system.
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