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| * 8 AVR(R) * RISC - 118 - - 32 8 - - 16 MHz 16 MIPS - 2K Flash : 10,000 - 128 EEPROM : 10,000 - 128 SRAM - EEPROM - 8 / - 8 2 PWM PWM - - 10 ADC 11 8 ADC 7 1x, 20x - - - 11 - - - - / - SPI - RC I/O - 20 PDIP/SOIC: 16 I/O - 32 MLF: 16 I/O - ATtiny26L2.7V - 5.5V - ATtiny264.5V - 5.5V - ATtiny26L0 - 8 MHz - ATtiny260 - 16 MHz ATtiny26L - 16 MHz, 5V, 25C:15 mA - 1 MHz, 3V, 25C: 0.70 mA - 1 MHz, 3V, 25C, : 0.18 mA - : < 1 A * * 2KB Flash 8 ATtiny26 ATtiny26L * * * * * Rev. 1477E-AVR-12/03 1 PDIP/SOIC (MOSI/DI/SDA/OC1A) PB0 (MISO/DO/OC1A) PB1 (SCK/SCL/OC1B) PB2 (OC1B) PB3 VCC GND (ADC7/XTAL1) PB4 (ADC8/XTAL2) PB5 (ADC9/INT0/T0) PB6 (ADC10/RESET) PB7 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (AREF) GND AVCC PA4 (ADC3) PA5 (ADC4) PA6 (ADC5/AIN0) PA7 (ADC6/AIN1) MLF Top View PB2 (SCK/SCL/OC1B) PB1 (MISO/DO/OC1A) PB0 (MOSI/DI/SDA/OC1A) NC NC NC PA0 (ADC0) PA1 (ADC1) 32 31 30 29 28 27 26 25 NC (OC1B) PB3 NC VCC GND NC (ADC7/XTAL1) PB4 (ADC8/XTAL2) PB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 NC PA2 (ADC2) PA3 (AREF) GND NC NC AVCC PA4 (ADC3) 2 ATtiny26(L) 1477E-AVR-12/03 NC (ADC9/INT0/T0) PB6 (ADC10/RESET) PB7 NC (ADC6/AIN1) PA7 (ADC5/AIN0) PA6 (ADC4) PA5 NC ATtiny26(L) ATtiny26(L) AVR RISC 8 CMOS ATtiny26(L) 1 MIPS/MHz AVR 32 (ALU) CISC 10 ATtiny26(L) 118ADC 20x ATtiny26(L) 8 PWM PWM ATtiny26(L)TWISM ATtiny26(L) 2K Flash 128 EEPROM 128 SRAM I/O 16 32 8 / PWM / / 11 10 CPU T/C ATtiny26(L)ADCADC ADC ADC I/O Standby ATtiny26(L) Atmel 8 RISC CPU Flash ATtiny26(L) ATtiny26(L) / 3 1477E-AVR-12/03 Figure 1. ATtiny26(L) VCC 8-BIT DATA BUS INTERNAL OSCILLATOR GND PROGRAM COUNTER STACK POINTER INTERNAL CALIBRATED OSCILLATOR WATCHDOG TIMER MCU CONTROL REGISTER TIMING AND CONTROL PROGRAM FLASH SRAM AVCC INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z MCU STATUS REGISTER TIMER/ COUNTER0 TIMER/ COUNTER1 INSTRUCTION DECODER CONTROL LINES ALU UNIVERSAL SERIAL INTERFACE STATUS REGISTER INTERRUPT UNIT PROGRAMMING LOGIC ISP INTERFACE EEPROM OSCILLATORS ANALOG COMPARATOR DATA REGISTER PORT A DATA DIR. REG.PORT A ADC DATA REGISTER PORT B DATA DIR. REG.PORT B + - PORT A DRIVERS PORT B DRIVERS PA0-PA7 PB0-PB7 4 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) VCC GND AVCC A(PA7..PA0) B(PB7..PB0) ADC AVCC A A/D ADC VCC VCC P75 A 8 I/O A ADC P92" " B 8 I/O PB6..0 PB7 I/O RSTDISBL ("0") PB7 I/O RESET B ADC T/C USI SPI P92" " PB7/RESET 50 ns XTAL1 XTAL2 5 1477E-AVR-12/03 32 8 ALU ALU 6 3 16 16 X Y Z Figure 2. ATtiny26(L) AVR RISC 8-bit Data Bus Control Registers 1024 x 16 Program FLASH Program Counter Status and Test Interrupt Unit Universal Serial Interface ISP Unit Indirect Addressing Direct Addressing Instruction Decoder Instruction Register 32 x 8 General Purpose Registers 2 x 8-bit Timer/Counter ALU Watchdog Timer 128 x 8 SRAM 128 byte EEPROM Control Lines ADC Analog Comparator I/O Lines ALU ALU Figure 2 ATtiny26(L) AVR RISC 32 ($00 - $1F) I/O64 CPU T/C ADC I/O $20 - $5F AVR Harvard CPU ( ) Flash 16 16 (PC) SRAM SRAM 6 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) SP I/O C C 128 SRAM 5 AVR I/O 64 CPU T/C I/O AVR AVR I/O Figure3 CPU 32 Figure 3. AVR CPU 7 R0 R1 R2 ... R13 R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 $1A $1B $1C $1D $1E $1F X X Y Y Z Z $0D $0E $0F $10 $11 0 Addr. $00 $01 $02 SBCI SUBI CPI ANDI ORI LDI - R16..R31 SBC SUB CP AND OR Figure3 32 SRAM X Y Z XYZ R26..R31 Figure 4. X Y Z 15 X 7 R27 ($1B) 0 7 R26 ($1A) 0 0 7 1477E-AVR-12/03 15 Y 7 R29 ($1D) 0 7 R28 ($1C) 0 0 15 Z 7 R31 ($1F) 0 7 R30 ($1E) 0 0 ALU AVR ALU 32 ALU ALU 3 8 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Flash ATtiny26(L)2KFlash AVR 16 32 Flash 1K x 16 Flash 10,000 ATtiny26(L) (PC) 10 1024 P103" " Flash P9" " Figure 5. SRAM R0 R1 R2 ... R29 R30 R31 I/O $00 $01 $02 ... $3D $3E $3F $0020 $0021 $0022 ... $005D $005E $005F SRAM $0060 $0061 ... $00DE $00DF $0000 $0001 $0002 ... $001D $001E $001F SRAM Figure5 ATtiny26(L) SRAM 224 I/O SRAM 96 I/O 128 SRAM 5 R26 R31 Y Z 63 X Y Z ATtiny26(L)32 64I/O128SRAM ATtiny26(L) AVR RISC Flash SRAM I/O AVR OP 9 1477E-AVR-12/03 Rd Figure 6. d (Rd) Rd Rr Figure 7. r (Rr) d (Rd) d (Rd) I/O Figure 8. I/O 6 n 10 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 9. Data Space 31 OP 16 LSBs 15 0 20 19 Rr/Rd 16 $0000 $00DF 16 16 LSB Rd/Rr Figure 10. Data Space $0000 15 Y OR Z - REGISTER 0 15 OP 10 n 65 a 0 $00DF Y Z 6 Figure 11. Data Space $0000 15 X-, Y-, OR Z-REGISTER 0 $00DF X Y Z 11 1477E-AVR-12/03 Figure 12. Data Space $0000 15 X-, Y-, OR Z-REGISTER 0 -1 $00DF X Y Z X Y Z Figure 13. Data Space $0000 15 X-, Y-, OR Z-REGISTER 0 1 $00DF X Y Z X Y Z LPM Figure 14. PROGRAM MEMORY $000 $3FF Z 15 MSB (0 - 1K) LSB = 0 LSB = 1 12 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) IJMP ICALL Figure 15. PROGRAM MEMORY $000 $3FF Z ( PC Z ) RJMP RCALL Figure 16. PROGRAM MEMORY $000 +1 $3FF PC + k + 1 k -2048 2047 EEPROM ATtiny26(L) 128 EEPROM EEPROM 100,000 EEPROM P58"EEPROM / " EEPROM P103" " 13 1477E-AVR-12/03 AVR CPU Figure17 Harvard 1 MIPS/MHz / / Figure 17. T1 T2 T3 T4 System Clock O 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure18 ALU Figure 18. ALU T1 T2 T3 T4 System Clock O Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back Figure19 SRAM Figure 19. SRAM T1 T2 T3 T4 System Clock O Address Data WR Data RD Prev. Address Address 14 ATtiny26(L) 1477E-AVR-12/03 Read Write ATtiny26(L) I/O ATtiny26(L) I/O Table 1 Table 1. ATtiny26(L) I/O (1) $3F ($5F) $3D ($5D) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $29 ($29) $21 ($41) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $0F ($2F) $0E ($2E) $0D ($2D) $08 ($28) $07 ($27) SREG SP GIMSK GIFR TIMSK TIFR MCUCR MCUSR TCCR0 TCNT0 OSCCAL TCCR1A TCCR1B TCNT1 OCR1A OCR1B OCR1C PLLCSR WDTCR EEAR EEDR EECR PORTA DDRA PINA PORTB DDRB PINB USIDR USISR USICR ACSR ADMUX T/C T/C MCU MCU T/C0 T/C0 (8 ) T/C1 A T/C1 B T/C1 (8 ) T/C1 A T/C1 B T/C1 C PLL EEPROM EEPROM EEPROM A A A B B B ADC 15 1477E-AVR-12/03 Table 1. ATtiny26(L) I/O (1) (Continued) $06($26) $05($25) $04($24) Note: ADCSR ADCH ADCL ADC ADC ADC 1. ATtiny26(L) I/OI/O I/OIN OUT 32 I/O $00 - $1F I/O SBI CBI SBIS SBIC "0" I/O I/O SREG AVR - SREG - I/O $3F Bit $3F ($5F) / 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG * Bit 7 - I: I I I RETI I I SEI CLI * Bit 6 - T: BLD BST T BST T BLD T * Bit 5 - H: H BCD * Bit 4 - S: , S = N V S N 2 V * Bit 3 - V: 2 2 * Bit 2 - N: * Bit 1 - Z: * Bit 0 - C: 16 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) SP ATtiny26(L) I/O8ATtiny26(L) 224 8 Bit $3D ($5D) / 7 SP7 R/W 0 6 SP6 R/W 0 5 SP5 R/W 0 4 SP4 R/W 0 3 SP3 R/W 0 2 SP2 R/W 0 1 SP1 R/W 0 0 SP0 R/W 0 SP SRAM $60 PUSH POP RET RETI 17 1477E-AVR-12/03 ATtiny26(L) I Table 2 RESET INT0 - 0 Table 2. 1 2 3 4 5 6 7 8 9 A B C $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B RESET INT0 I/O Pins TIMER1, CMPA TIMER1, CMPB TIMER1, OVF1 TIMER0, OVF0 USI_STRT USI_OVF EE_RDY ANA_COMP ADC 0 T/C1 1A T/C1 1B T/C1 T/C0 USI USI EEPROM ADC $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B ; $009 $00A $00B ... ... RESET: ldi out sei ... ... r16, RAMEND SP, r16 ; rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp RESET EXT_INT0 PIN_CHANGE TIM1_CMP1A TIM1_CMP1B TIM1_OVF TIM0_OVF USI_STRT USI_OVF EE_RDY ANA_COMP ADC ; ; IRQ0 ; ; 1 1A ; 1 1B ; 1 ; 0 ; USI ; USI ; EEPROM ; ; ADC 18 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) ATtiny26(L) * * * * VPOT MCU PB7/RESET I/O RSTDISBL ("1") RESET 50 ns MCU MCU VCC VBOT MCU I/O $000 $000 RJMP Figure20 ATtiny26(L) Table 3 ATtiny26(L) Figure 20. ATtiny26(L) DATA BUS MCU Status Register (MCUSR) PORF BORF EXTRF WDRF BODEN BODLEVEL Brown-Out Reset Circuit Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] 0 Table 3. VPOT VRST tRST ( ) ( ) RESET RESET (1) 1.4 1.3 2.3 2.3 0.9 V V VCC ns 0.2 750 19 1477E-AVR-12/03 Table 3. VBOT tBOD VHYST Notes: (2) BODLEVEL = 1 BODLEVEL = 0 2.5 3.7 2.7 4.0 2 2 130 3.2 4.2 V s s mV BODLEVEL = 1 BODLEVEL = 0 1. VPOT ( ) 2. VBOT VCC = VBOT VCC ATtiny26L BODLEVEL=1 ATtiny26 BODLEVEL=0 BODLEVEL=1 ATtiny26 P24" " CPU (POR) Table 3 VCC POR POR (POR) VCC RESET CKSEL P24"" VCC RESET Figure 21. VCC MCU RESET VCC VPOT RESET VRST TIME-OUT tTOUT INTERNAL RESET Figure 22. MCU RESET VCC VPOT RESET VRST TIME-OUT tTOUT INTERNAL RESET 20 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) RESET 500 ns VRST tTOUT MCU Figure 23. VCC RESET VRST t TOUT TIME-OUT INTERNAL RESET ATtiny26(L) BOD VCC BOD BODEN BOD VCC VCC Table 2 POR BOD BODLEVEL 2.7V (BODLEVEL ) 4.0V (BODLEVEL ) 50 mV BOD Table 3 tBOD BOD VCC Figure 24. BOD VCC VBOTVBOT+ RESET TIME-OUT tTOUT INTERNAL RESET MCU P56 21 1477E-AVR-12/03 Figure 25. 1 CK Cycle 22 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure26 AVR P38" " Figure 26. Timer/Counter1 General I/O modules ADC CPU Core RAM Flash and EEPROM clkADC clkI/O clkCPU clkFLASH AVR Clock Control Unit Reset Logic Watchdog Timer Source clock Clock Multiplexer Watchdog clock Watchdog Oscillator clkPCK clkPLL PLL External RC Oscillator External clock Crystal Oscillator Low-Frequency Crystal Oscillator Calibrated RC Oscillator CPU clkCPU I/O clkI/O CPUAVR CPU I/OI/O /USI I/O I/O Flash Flash CPU ADC ADCCPUI/O ADC Flash clkFLASH ADC clkADC 23 1477E-AVR-12/03 PLL clkPCK ATtiny26(L) PLL()1 MHz64 MHz 1 RC P24Figure27 PLL 1 MHz 64 MHz T/C1 PLLRC OSCCALRC RC 1 MHz 70 MHz PLL RC OSCCAL RC 1 MHz PLL PLLCSR PLLE PLLCK ("0") PLL PLL PLLCSR PLOCK Standby 1 MHz RC PLL Figure 27. PCK PLLE PLLCK & CKSEL FUSES OSCCAL Lock Detector PLOCK 1 RC OSCILLATOR 2 4 8 MHz DIVIDE TO 1 MHz PLL 64x PCK DIVIDE BY 4 CK XTAL1 XTAL2 OSCILLATORS 24 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Flash Table 4 AVR PB5 (XTAL2) PB4 (XTAL1) I/O Table 5 Table 4. / RC RC PLL PLLCK 1 1 1 1 1 0 CKSEL3..0 1111 - 1010 1001 1000 - 0101 0100 - 0001 0000 0001 Table 5. PB5 PB4 (1) RC RC RC RC RC RC RC RC / / / / / / PLL Note: PLLCK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 CKSEL [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0001 PB4 XTAL1 I/O I/O I/O I/O XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 I/O PB5 I/O I/O I/O I/O I/O I/O I/O I/O I/O XTAL2 XTAL2 XTAL2 XTAL2 XTAL2 XTAL2 XTAL2 I/O 1. "1" "0" CPU CPU MCU 25 1477E-AVR-12/03 WDT Table 6 Table 6. (VCC = 5.0V) 4.1 ms 65 ms (VCC = 3.0V) 4.3 ms 69 ms 4K (4,096) 64K (65,536) CKSEL = "0001" SUT = "10" PLLCK 1 MHzRC ISP .XTAL1 XTAL2 Figure28 12 MHz CKOPT C1 C2 Table 7 Figure 28. C2 C1 XTAL2 XTAL1 GND CKSEL3..1 Table 7 Table 7. CKSEL3..1 101 (1) (MHz) 0.4 - 0.9 0.9 - 3.0 3.0 - 16 16 - C1 C2 (pF) - 12 - 22 12 - 22 12 - 15 110 111 Note: 1. 26 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Table 8 CKSEL0 SUT1..0 Table 8. CKSEL0 0 0 0 0 1 1 1 1 Notes: SUT1..0 00 01 10 11 00 01 10 11 258 CK (1) (VCC = 5.0V) 4.1 ms 65 ms - 4.1 ms 65 ms - 4.1 ms 65 ms BOD BOD 258 CK(1) 1K CK(2) 1K CK(2) 1K CK(2) 16K CK 16K CK 16K CK 1. 2. 32.768 kHz PLLCK "1" CKSEL"1001" Figure28 CKOPT XTAL1 XTAL2 36 pF SUT Table 9 Table 9. SUT1..0 00 01 10 11 Note: 1K CK 1K CK (1) (1) (VCC = 5.0V) 4.1 ms 65 ms 65 ms BOD 32K CK 1. RC Figure29 RC f = 1/(3RC) C 22 pF CKOPT XTAL1 GND 36 pF 27 1477E-AVR-12/03 Figure 29. RC VCC R PB5 (XTAL2) XTAL1 C GND CKSEL3..0 Table 10 Table 10. RC CKSEL3..0 0101 0110 0111 1000 (MHz) - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0 SUT Table 11 Table 11. RC SUT1..0 00 01 10 11 Notes: 18 CK 18 CK 18 CK 6 CK (1) (VCC = 5.0V) - 4.1 ms 65 ms 4.1 ms BOD BOD 1. 28 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) RC RC 1.0 2.0 4.0 8.0 MHz 5V 25C Table 12 CKSEL (CKOPT) OSCCAL RC 5V 25C 1.0 MHz 1% P105" " Table 12. RC CKSEL3..0 0001 (1) (MHz) 1.0 2.0 4.0 8.0 0010 0011 0100 Note: 1. SUT Table 13 XTAL1 XTAL2 I/O Table 13. RC SUT1..0 00 01 10(1) 11 Note: 1. 6 CK 6 CK 6 CK (VCC = 5.0V) - 4.1 ms 65 ms BOD OSCCAL Bit $31 ($51) / 7 CAL7 R/W 6 CAL6 R/W 5 CAL5 R/W 4 CAL4 R/W 3 CAL3 R/W 2 CAL2 R/W 1 CAL1 R/W 0 CAL0 R/W OSCCAL * Bits 7..0 - CAL7..0: 1 MHz ( 0x00) OSCCAL RC Flash EEPROM OSCCAL OSCCAL $FF EEPROM Flash EEPROM Flash 29 1477E-AVR-12/03 10% 1.0 2.0 8.0 MHz 4.0 Table 14 Table 14. RC OSCCAL $00 $7F $FF (%) 50% 75% 100% (%) 100% 150% 200% XTAL1 Figure30 CKSEL"0000" PLLCK"1" CKOPT XTAL1 GND 36 pF Figure 30. PB5 (XTAL2) EXTERNAL CLOCK SIGNAL XTAL1 GND SUT Table 15 Table 15. SUT1..0 00 01 10 11 6 CK 6 CK 6 CK (VCC = 5.0V) - 4.1 ms 65 ms BOD MCU 2% MCU 30 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) PLL PLLCLK RC PLL 64 MHz T/C1 PLLCK("0") CKSEL3..0 "0001" 4.5 - 5.5V 16 MHz (64 MHz/4) Table 16 SUT P24"PCK " Table 16. PLLCK SUT1..0 00 01 10 11 1K CK 1K CK 1K CK 16K CK (VCC = 5.0V) - 4.1 ms 65 ms - BOD MCU MCUSR Bit $34 ($54) / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUSR * Bit 7..4 - Res: ATtiny26(L) "0" * Bit 3 - WDRF: "0" * Bit 2 - BORF: "0" * Bit 1 - EXTRF: "0" * Bit 0 - PORF: "0" 31 1477E-AVR-12/03 ATtiny26(L) 8 GIMSK - TIMSK - T/C I I RETI I "1" "0" I AVR 4 4 4 PC 2 MCU 4 PC(10 ) AVR GIMSK Bit $3B ($5B) / 7 - R 0 6 INT0 R/W 0 5 PCIE1 R/W 0 4 PCIE0 R/W 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIMSK * Bit 7 - Res: ATtiny26(L) "0" * Bit 6 - INT0: 0 INT0 '1' SREG I MCU- MCUCR0 1/0 (ISC01ISC00) INT0 INT0 0 $001 P37" " * Bit 5 - PCIE1: 1 PCIE1 I "1" PB[7:4] PA[7:6] PA[3] $002 P37" " 32 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) * Bit 4- PCIE0: 0 PCIE0I"1" PB[3:0] $002 P37" " * Bits 3..0 - Res: ATtiny26(L) "0" GIFR Bit $3A ($5A) / 7 - R 0 6 INTF0 R/W 0 5 PCIF R/W 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIFR * Bit 7 - Res: ATtiny26(L) "0" * Bit 6 - INTF0: 0 INT0 INTF0 SREG I GICR INT0 "1" MCU "1" * Bit 5 - PCIF: PB[7:0] PA[7:6] PA[3] PCIF "1" PCIE1 PB[7:4] PA[7:6] PA[3] PCIE0 PB[3:0] PCIE1 PCIE0 PCIE0 PB[3:0] PCIF PCIF SREG I GIMSK PCIE "1" MCU $002 "1" P37" " * Bits 4..0 - Res: ATtiny26(L) "0" T/C TIMSK Bit $39 ($59) / 7 - R 0 6 OCIE1A R/W 0 5 OCIE1B R/W 0 4 - R 0 3 - R 0 2 TOIE1 R/W 0 1 TOIE0 R/W 0 0 - R 0 TIMSK * Bit 7 - Res: ATtiny26(L) "0" * Bit 6 - OCIE1A:T/C1 OCIE1A I "1" T/C1 A T/C1 A $003 T/C T/C1 "1" 33 1477E-AVR-12/03 * Bit 5 - OCIE1B: T/C1 OCIE1B I "1" T/C1 B T/C1 B $004 T/C T/C1 "1" * Bit 4..3 - Res: ATtiny26(L) "0" * Bit 2 - TOIE1: T/C1 TOIE1 I "1" T/C1 T/C1 TIFR $005 * Bit 1 - TOIE0: T/C0 TOIE0I"1" T/C0 T/C0 TIFR $006 * Bit 0 - Res: ATtiny26(L) "0" T/C TIFR Bit $38 ($58) / 7 - R 0 6 OCF1A R/W 0 5 OCF1B R/W 0 4 - R 0 3 - R 0 2 TOV1 R/W 0 1 TOV0 R/W 0 0 - R 0 TIFR * Bit 7 - Res: ATtiny26(L) "0" * Bit 6 - OCF1A: 1A T/C1 OCR1A( 1A) OCF1A 1 SREG I OCIE1A OCF1A * Bit 5 - OCF1B: 1B T/C1 OCR1B( 1B) OCF1B 1 SREG I OCIE1B OCF1B * Bits 4..3 - Res: ATtiny26(L) "0" * Bit 2 - TOV1:T/C1 T/C1 TOV1 TOV1 1 SREG I TOIE1(T/C1 ) TOV1 34 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) * Bit 1 - TOV0: T/C0 T/C0 TOV0 TOV0 1 SREG I TOIE0(T/C0 ) TOV0 * Bit 0 - Res: ATtiny26(L) "0" 35 1477E-AVR-12/03 INT0 INT0 MCU MCUCR B PA3PA6 PA7 I/O GIMSK PCIE1 PB[7:4] PA[7:6] PA[3] PCIE0 PB[3:0] PCIE1 PCIE0 AREF AIN0 AIN1 OC1A OC1A OC1B OC1B XTAL1 XTAL2 Timer0 RESET Table 17 USI USI T/C1 PB0 "0" "1" " " Table 17. Pin PA3 PA6 PA7 PB0 AREF USI USI TC1 /PWM USI TC1 /PWM USI USI TC1 /PWM TC1 /PWM XTAL1 XTAL2 TC0 RESET [ ] (1) ADMUX[REFS0] ACSR[ACD] ACSR[ACD] USICR[USIWM1] USICR[USIWM1,USIWM0] TCCR1A[COM1A1,COM1A0,PWM1A] USICR[USIWM1,USIWM0] TCCR1A[COM1A1] TCCR1A[COM1A0] USICR[USIWM1] USICR[USIWM1,USIWM0] TCCR1A[COM1B1,COM1B0,PWM1B] TCCR1A[COM1B1] TCCR1A[COM1B0] FUSE[PLLCK,CKSEL] FUSE[PLLCK,CKSEL] FUSE[PLLCK,CKSEL] GIMSK[INT0],MCUCR[ISC01,ISC01] TCCR0[CS02,CS01] RSTDISBL FUSE (2) 1 0 0 1 01 011 01 1 1 1 01 011 1 1 10000 10101-11111 11001-11111 100 11 1 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Notes: 1. 2. "0" "1" 36 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) MCU MCUCR MCU MCU Bit $35 ($55) / 7 - R 0 6 PUD R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 - R 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR * Bits 7 - Res: ATtiny26(L) "0" * Bit 6 - PUD: DDxn PORTxn ({DDxn, PORTxn} = 0b01) I/O P88" " * Bit 5 - SE: SLEEP SE MCU SLEEP SE * Bits 4,3 - SM1/SM0: 1 0 Table 18. SM1 0 0 1 1 SM0 0 1 0 1 ADC Standby " " * Bit 2 - Res: ATtiny26(L) "0" * Bits 1, 0 - ISC01, ISC00: 0 Bit 1 and Bit 0 0 INT0 SREG I Table 19. 0 (1) ISC01 0 0 1 1 Note: ISC00 0 1 0 1 INT0 . INT0 INT0 INT0 1. ISC10/ISC00 GIMSK INT0 37 1477E-AVR-12/03 MCU AVR MCUCR SE SLEEP ( ADC Standby Standby ) MCUCR SM1 SM0 Table 18 MCU 4 MCU SLEEP SRAM MCU P39Table 20 ATtiny26 SM1..0 "00" SLEEP MCU CPU ADC USI T/C clkCPU clkFLASH USI MCU MCU ACSR ACD ADC ADC SM1..0 "01" SLEEP MCU ADC CPU ADC USI clkI/O clkCPU clkFLASH ADC ADC AD ADC BOD USI EEPROM INT0 MCU ADC SM1..0 "10" SLEEP MCU USI BOD USI INT0 MCU CKSEL P26" " MCU MCU MCU 3.0V 25C 1.0 s ( ) MCU INT0 38 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Standby SM1..0 "11" SLEEP MCU Standby 6 Table 20. ADC Standby Notes: (1) X X INT0 USI EEPROM ADC I/O clkCPU clkFLASH clkIO clkADC X X X X X(2) X (2) (2) X X X X X X X X X X X 1. 2. INT0 39 1477E-AVR-12/03 AVR ADC ADC P75" " ADC P72" " BOD BODEN BOD P23" " BOD BOD ADC P56" " I/O clkI/O ADC clkADC P91" " VCC/2 BOD 40 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) / T/C0 ATtiny26(L) 8T/C T/CT/C0(CK) T/C1 CK (PCK) Figure31 T/C Figure 31. T/C0 CK CLEAR CK/8 10-BIT T/C PRESCALER CK/64 CK/256 CK/1024 PSR0 T0(PB6) 0 CS00 CS01 CS02 TIMER/COUNTER0 CLOCK SOURCE CK/8 CK/64 CK/256 CK/1024 CK CK T/C1 Figure32 T/C1 T/C1 PCKPCK/16384 CK CK/16384 T/C1 TCCR1B P47Table 24 TCCR1B PSR1 PLLCSR PCKE Figure 32. T/C1 PCKE CK PCK (64 MHz) S A PSR1 T1CK 14-BIT T/C PRESCALER T1CK/1024 T1CK/2048 T1CK/4096 0 CS10 CS11 CS12 CS13 TIMER/COUNTER1 COUNT ENABLE T1CK/8192 T1CK/128 T1CK/256 T1CK/512 T1CK/16 T1CK/32 T1CK/64 T1CK/8 T1CK/16384 T1CK/2 T1CK/4 T1CK 41 1477E-AVR-12/03 8 T/C0 Figure33 T/C0 8 T/C0 CK CK T/C0 TCCR0 T/C TIFR T/C0TCCR0 T/C0/T/CTIMSK T/C0 CPU CPU CPU 8 T/C0 T/C0 Figure 33. T/C0 T/C0 TCCR0 Bit $33 ($53) / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 PSR0 R/W 0 2 CS02 R/W 0 1 CS01 R/W 0 0 CS00 R/W 0 TCCR0 * Bits 7..4 - Res: ATtiny26(L) "0" * Bit 3 - PSR0: T/C0 T/C0 0 42 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) * Bits 2, 1, 0 - CS02, CS01, CS00: 0, Bit 2, 1 0 T0 Table 21. 0 CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 Stop, T/C0 CK CK/8 CK/64 CK/256 CK/1024 T0 T0 Stop / ( ) T/C0 TCNT0 Bit $32 ($52) / 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 TCNT0 T/C0 T/C0 T/C0 8 T/C1 T/C1 (CK) (PCK) PLLCSR PCKE "1" T/C1 Figure34 T/C1 T/C1 TCCR1A TCCR1B OCR1A OCR1B OCR1C T/C1 (TCNT1) (OCF1A OCF1B TOV1) T/C1 8 64 MHz T/C1 / PWM P52 T/C1 43 1477E-AVR-12/03 Figure 34. T/C1 8-BIT DATABUS IO-registers OCR1A OCR1B OCR1C TCCR1A TCCR1B TCNT1 OCF1A OCF1B TOV1 Input syncronization Timer/Counter1 registers OCR1A_SI OCR1B_SI OCR1C_SI TCCR1A_SI TCCR1B_SI TCNT1 TCNT1_SI OCF1A_SI OCF1B_SI TOV1_SI TOV1_SO OCF1B_SO S A S A OCF1B OCF1A_SO S A OCF1A Output syncronization registers TCNT_SO Output multiplexers S A TCNT1 TOV1 PCKE CK S A S A 1CK delay 1/2PCK -1CK delay 1PCK delay no delay 1/2PCK -1CK delay no delay PCK SYNC MODE ASYNC MODE 64 MHz PCK T/C1 PCK PCK PCK 2 T/C1 PCK Figure35 T/C1 44 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 35. T/C1 T/C1 OVER- T/C1 COMPARE T/C1 COMPARE FLOW IRQ MATCH A IRQ MATCH B IRQ OC1A (PB0) OC1A (PB1) OC1B (PB2) OC1B (PB3) OCIE1A OCIE1B TOIE0 OCF1A TOIE1 OCF1B TOV1 TIMER INT. MASK REGISTER (TIMSK) TIMER INT. FLAG REGISTER (TIFR) COM1A1 OCF1A OCF1B TOV1 TOV0 T/C CONTROL REGISTER 1 (TCCR1A) PWM1A PWM1B COM1A0 COM1B1 COM1B0 FOC1A FOC1B CTC1 T/C CONTROL REGISTER 1 (TCCR1B) PSR1 CS13 CS12 CS11 CS10 TIMER/COUNTER1 TIMER/COUNTER1 (TCNT1) T/C CLEAR T/C1 CONTROL LOGIC CK PCK 8-BIT COMPARATOR 8-BIT COMPARATOR 8-BIT COMPARATOR T/C1 OUTPUT COMPARE REGISTER (OCR1A) T/C1 OUTPUT COMPARE REGISTER (OCR1B) T/C1 OUTPUT COMPARE REGISTER (OCR1C) 8-BIT DATA BUS T/CTIFR ()T/CTCCR1A TCCR1B T/C TIMSK / T/C1OCR1A OCR1BOCR1C T/C1 OCR1A OC1A (PB1) PWM 1 OC1A OCR1B OC1B (PB3) PWM 1 OC1B PWM OCR1C T/C T/C1 $FF $00 OCR1C $00 (TOV1) PWM OC1A OC1B PWM OCR1A OCR1B T/C PWM (OC1A OC1AOC1BOC1B) PWM T/C OCR1C $00 " " $FF PWM Table 27 20 kHz 250 kHz 10 kHz 250 kHz 500 kHz 50 kHzPWM OCR1C PWM T/C1 A TCCR1A Bit $30 ($50) / 7 COM1A1 6 COM1A0 5 COM1B1 4 COM1B0 3 FOC1A 2 FOC1B 1 PWM1A 0 PWM1B TCCR1A R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 45 1477E-AVR-12/03 * Bits 7, 6 - COM1A1, COM1A0: A , Bits 1 0 COM1A1 COM1A0 OC1A 1 OC1A Table 22. A COM1A1 0 0 1 1 COM1A0 0 1 0 1 T/C A OC1A OC1A OC1A OC1A PWM P50Table 25 * Bits 5, 4 - COM1B1, COM1B0: B , Bits 1 0 COM1B1 COM1B0 OC1B 1 OC1B Table 23. B COM1B1 0 0 1 1 COM1B0 0 1 0 1 T/C B OC1B OC1B OC1B OC1B PWM P50Table 25 * Bit 3 - FOC1A: 1A 1 OC1A COM1A1:0 COM1A1 COM1A0 FOC1A COM1A1 COM1A0 FOC1A PWM1A FOC1A * Bit 2 - FOC1B: 1B 1 OC1B COM1B1:0 COM1B1 COM1B0 FOC1B COM1B1 COM1B0 FOC1B PWM1B FOC1B * Bit 1 - PWM1A: A PWM T/C1 OCR1A OCR1C $00 * Bit 0 - PWM1B: B PWM T/C1 OCR1B OCR1C $00 46 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) T/C1 B TCCR1B Bit $2F ($4F) / 7 CTC1 R/W 0 6 PSR1 R/W 0 5 - R 0 4 - R 0 3 CS13 R/W 0 2 CS12 R/W 0 1 CS11 R/W 0 0 CS10 R/W 0 TCCR1B * Bit 7 - CTC1: T/C CTC1 OCR1C T/C1 $00 T/C1 * Bit 6 - PSR1: T/C1 T/C 0 * Bit 5..4 - Res: ATtiny26(L) "0" * Bits 3..0 - CS13, CS12, CS11, CS10: 3, 2, 1 0 3 2 1 0 T/C1 Table 24. T/C1 CS13 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CS12 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CS11 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CS10 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 T/C1 PCK PCK/2 PCK/4 PCK/8 PCK/16 PCK/32 PCK/64 PCK/128 PCK/256 PCK/512 PCK/1024 PCK/2048 PCK/4096 PCK/8192 PCK/16384 T/C1 CK CK/2 CK/4 CK/8 CK/16 CK/32 CK/64 CK/128 CK/256 CK/512 CK/1024 CK/2048 CK/4096 CK/8192 CK/16384 / T/C1 TCNT1 Bit $2E ($4E) / 7 MSB R/W R/W R/W R/W R/W R/W R/W 6 5 4 3 2 1 0 LSB R/W TCNT1 47 1477E-AVR-12/03 0 0 0 0 0 0 0 0 8 T/C1 T/C1 CPUT/C1T/C1 CPU CPU T/C1 OCR1A Bit $2D ($4D) / 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 OCR1A A 8 / T/C A T/C1 TCCR1A T/C1 OCR1A TCNT1 OCR1A OCF1A T/C1 B OCR1B Bit $2C ($4C) / 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 OCR1B B 8 / T/C B T/C1 TCCR1A T/C1 OCR1B TCNT1 OCR1B OCF1B T/C1 C OCR1C Bit $2B ($4B) / 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 OCR1C C 8 / T/CCT/C1 T/C1OCR1C TCNT1 OCR1C TCCR1B CTC1 TCNT1 (TOV1) PWM PLL PLLCSR Bit $29 ($29) / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 PCKE R/W 0 1 PLLE R/W 0/1 0 PLOCK R 0 PLLCSR * Bit 7..3 - Res: ATtiny26(L) "0" 48 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) * Bit 2 - PCKE: PCK PCKET/C1 64 MHz PCK T/C1 CK T/C1 PLLE PLL PLOCK 1 * Bit 1 - PLLE: PLL PLLE PLL RC PLL PLL 1 * Bit 0 - PLOCK: PLL PLOCKPLL T/C1 PCK PLL PLL 64 s/100 s ( / ) T/C1 PWM T/C1 T/C1 PLLPLOCK PCKE PWM T/C1 C - OCR1C 8 PWM PB1(OC1A) PB3(OC1B) PB0(OC1A)PB2(OC1B) (OC1A - OC1AOC1B - OC1B) PCK PCK CKCK Figure 36. OC1x OC1x t non-overlap x = A or B OCR1A OCR1B T/C1 A - TCCR1A COM1A1/COM1A0 COM1B1/COM1B0 OC1A OC1B Table 25 T/C1 $00 OCR1C $00 OC1C TOV1 49 1477E-AVR-12/03 Table 25. PWM COM1x1 0 0 1 1 COM1x0 0 1 0 1 OC1x OC1x OC1x TCNT1 = $01 OC1x TCNT1 = $00 OC1x TCNT1 = $01 OC1x OC1x TCNT = $00 OC1x PWM OCR1A OCR1B T/C OCR1C OCR1A OCR1B OCR1A OCR1B PWM ( ) Figure 37 Figure 37. OCR Compare Value Changes Counter Value Compare Value PWM Output OC1x Synchronized OC1x Latch Compare Value changes Counter Value Compare Value PWM Output OC1x Unsynchronized OC1x Latch Glitch OCR1A OCR1B OCR1A OCR1B OCR1A OCR1B $00 OCR1C COM1A1/COM1A0 PB1(OC1A) PB3(OC1B) Table 26 50 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Table 26. PWM OCR1x = $00 OCR1C, x = A B COM1x1 0 0 1 1 1 1 COM1x0 1 1 0 0 1 1 OCR1x $00 OCR1C $00 OCR1C $00 OCR1C OC1x L H L H H L OC1x H L PWM - TOV1 T/C T/C PWM 1 (OCR1C + 1) f TCK1 f PWM = ----------------------------------( OCR1C + 1 ) OCR1C ResolutionPWM = log2(OCR1C + 1) 51 1477E-AVR-12/03 Table 27. T/C1 PWM (kHz) 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 250 300 350 400 450 500 PCK/16 PCK/16 PCK/8 PCK/8 PCK/8 PCK/4 PCK/4 PCK/4 PCK/4 PCK/4 PCK/4 PCK/2 PCK/2 PCK/2 PCK/2 PCK/2 PCK/2 PCK/2 PCK/2 PCK PCK PCK PCK PCK PCK CS13..CS10 0101 0101 0100 0100 0100 0011 0011 0011 0011 0011 0011 0010 0010 0010 0010 0010 0010 0010 0010 0001 0001 0001 0001 0001 0001 OCR1C 199 132 199 159 132 228 199 177 159 144 132 245 228 212 199 187 177 167 159 255 212 182 159 141 127 ( ) 7.6 7.1 7.6 7.3 7.1 7.8 7.6 7.5 7.3 7.2 7.1 7.9 7.8 7.7 7.6 7.6 7.5 7.4 7.3 8.0 7.7 7.5 7.3 7.1 7.0 52 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) 1 Mhz VCC = 5V VCC 16 2048 ms WDR 8 ATtiny26(L) P23 Figure 38. Normally 1 MHz WATCHDOG PRESCLALER WATCHDOG RESET WDP0 WDP1 WDP2 WDE MCU RESET WDTCR Bit $21 ($41) / 7 - R 0 6 - R 0 5 - R 0 4 WDCE R/W 0 3 WDE R/W 0 2 WDP2 R/W 0 1 WDP1 R/W 0 0 WDP0 R/W 0 WDTCR * Bits 7..5 - Res: ATtiny26(L) "0" * Bit 4 - WDCE: WDE WDCE 4 WDE 1 2 WDCE * Bit 3 - WDE: WDE"1" WDCE"1"WDE 1. WDCE WDE "1" WDE "1" 2. 4 WDE "0" 53 1477E-AVR-12/03 * Bits 2..0 - WDP2, WDP1, WDP0: 2, 1 0 WDP2 WDP1 WDP0 Table 28 Table 28. (1) WDP2 0 0 0 0 1 1 1 1 Note: WDP1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 16K (16,384) 32K (32,768) 64K (65,536) 128K (131,072) 256K (262,144) 512K (524,288) 1,024K (1,048,576) 2,048K (2,097,152) VCC = 3.0V 17.1 ms 34.3 ms 68.5 ms 0.14 s 0.27 s 0.55 s 1.1 s 2.2 s VCC = 5.0V 16.3 ms 32.5 ms 65 ms 0.13 s 0.26 s 0.52 s 1.0 s 2.1 s 1. WDR - - 0 54 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) EEPROM / EEPROM I/O EEPROM 8.3 ms EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM CPU 2 EEPROM CPU 4 EEPROM EEAR Bit $1E ($3E) / 7 - R 0 6 EEAR6 R/W X 5 EEAR5 R/W X 4 EEAR4 R/W X 3 EEAR3 R/W X 2 EEAR2 R/W X 1 EEAR1 R/W X 0 EEAR0 R/W X EEAR * Bit 7 - RES: ATtiny26(L) "0" * Bit 6..0 - EEAR6..0: EEPROM EEAR 128 EEPROM EEPROM 0 127 EEAR EEPROM EEPROM EEDR Bit $1D ($3D) / 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 EEDR * Bit 7..0 - EEDR7..0: EEPROM EEPROM EEDR EEAR EEDR EEAR EEPROM EECR Bit $1C ($3C) / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 EERIE R/W 0 2 EEMWE R/W 0 1 EEWE R/W 0 0 EERE R/W 0 EECR * Bit 7..4 - RES: ATtiny26(L) "0" * Bit 3 - EERIE: EEPROM SREG I "1" EERIE EEPROM EERIE EEWE EEPROM * Bit 2 - EEMWE: EEPROM EEMWEEEWE"1"EEPROM EEMWE"1" 4 EEWEEEPROMEEMWE"0" EEWE 55 1477E-AVR-12/03 EEMWE 4 EEPROM EEWE * Bit 1 - EEWE: EEPROM EEWE EEPROM EEPROM EEWE EEPROM EEMWE EEPROM ( 2 3 ) 1. EEWE "0" 2. EEPROM EEAR ( ) 3. EEPROM EEDR ( ) 4. EECR EEMPE "1" 5. EEMWE 4 EEWE : 4 5 EEPROM EEPROM EEPROM EEAR EEDR EEPROM I ( 8.3 ms) EEPE EEWE CPU * Bit 0 - EERE: EEPROM EERE EEPROM EEPROM EERE EEAR EEPROM EEPROM CPU 4 EEPROM EEWE EEPROM EEAR 56 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Table 29. EEPROM CPU EEPROM Note: RC (1) 8448 8.5 ms 1. 1 MHz CKSEL EEPROM EEPROM EEPROM CPU EEPROM EEPROM ( ) EEPROM EEPROM EEPROM CPU EEPROM 1. AVR RESET BOD BOD 2. AVR CPU EEPROM 3. Flash CPU Flash EEPROM 57 1477E-AVR-12/03 USI USI USI USI * ( , fSCLmax = fCK/16) * ( , fSCKmax = fCK/2, Slave fSCKmax = fCK/4) * * * * Figure 39. USI Figure 39. DQ LE PB1 DO (Output only) PB0 DI/SDA (Input/Open Drain) Bit7 Bit0 USIDR 3 2 1 0 TIM0 OVF USIOIF USISIF USIDC USIPF 4-bit Counter 3 2 1 0 [1] 0 1 CLOCK HOLD PB2 SCK/SCL (Input/Open Drain) DATA BUS USISR Two-wire Clock Control Unit 2 USIWM1 USIWM0 USICS1 USICS0 USICLK USIOIE USISIE USICR 8 (DI) 4 SCK 0 USI USIDR Bit $0F ($2F) / 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 USIDR 58 ATtiny26(L) 1477E-AVR-12/03 USITC ATtiny26(L) USI USIDR USICS1..0 / 0 USICLK (USIWM1..0 = 0) (DI/SDA) (SCK/SCL) (DO SDA ) ( 7) (USICS1 = 1) ( ) (USICS1 = 0) MSB USI USISR Bit $0E ($2E) / 7 USISIF 6 USIOIF 5 USIPF 4 USIDC 3 USICNT3 2 USICNT2 1 USICNT1 0 USICNT0 USISR R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 USISR - - SBI CBI OUT * Bit 7 - USISIF: USISIF (USICSx = 0b11 & USICLK = 0) (USICS = 0b10 & USICLK = 0) SCK USISIF USICR USISIE USISIF 1 SCL * Bit 6 - USIOIF: 4(150) USICRUSIOIE USIOIF 1 SCL * Bit 5 - USIPF: USIPF USIOIF 1 * Bit 4 - USIDC: 7 USIDC * Bits 3..0 - USICNT3..0: 4 CPU 59 1477E-AVR-12/03 / 0 USICLK USITC USICS1..0 USITC (USICS1 = 1) USICLK 1 (USIWM1..0 = 0) (SCK/SCL) USI USICR Bit $0D ($2D) / 7 USISIE R/W 0 6 USIOIE R/W 0 5 USIWM1 R/W 0 4 USIWM0 R/W 0 3 USICS1 R/W 0 2 USICS0 R/W 0 1 USICLK W 0 0 USITC W 0 USICR * Bit 7 - USISIE: 1 USISIE P59"Bit 7 - USISIF: " * Bit 6 - USIOIE: 1 USIOIE P59"Bit 6 - USIOIF: " 60 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) * Bit 5..4 - USIWM1..0: USIWM1..0 USIWM1..0 USI Table 30 Table 30. USIWM1..0 USI USIWM1 0 0 USIWM0 0 1 DO DI SCK (DO) IO DDR PORT (DI) (SCK) PORT USICR USITC SDA (DI) SCL (SCK) (1) (SDA) (SCL) DDR SDA PORT 0 SDA SDA ( ) SCL PORT 0 SCL SCL SCL (USISIF) SDA SCL SDA SCL SDA SCL SCL (USIOIF) 1 0 1 1 Note: 1. DI SCK (SDA) (SCL ) 61 1477E-AVR-12/03 * Bit 3..2 - USICS1..0: (SCK/SCL) (DI/SDA) 0 USICS1..0 0 USICLK 1 (USICS1 = 1) USICLK USITC Table 31 USICS1..0 USICLK 4 Table 31. USICS1..0 USICLK USICS1 0 0 0 1 1 1 1 USICS0 0 0 1 0 1 0 1 USICLK 0 1 X 0 0 1 1 (USICLK) / 0 4 (USICLK) / 0 (USITC) (USITC) * Bit 1 - USICLK: USICS1..0 0 USICLK 0 (USICS1 = 1) USICLK USICLK USITC 4 ( Table 31) * Bit 0 - USITC: USITC SCK/SCL 0 1 DDRB2 0 (USICS1 = 1) USICLK 1 USITC 4 62 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) USI(SPI)01 (SS) DI DO SCK Figure 40. PBx DO Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PBy DI PBz SLAVE SCK PBx DO Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PBy DI PBz PORTBz MASTER SCK Figure40 USI 8 SCK USI 4 ( ) USIOIF PORTB PB2 USICR USITC Figure 41. CYCLE SCK SCK DO DI MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB ( Reference ) 1 2 3 4 5 6 7 8 A B C D E Figure 41. SCK USI (USIDR) SCK 0(USICS0 = 0) DI DO ( ) 1(USICS0 = 1) 0 USI SPI 0 1 Figure 41. 63 1477E-AVR-12/03 1. (DDRB2) A B C USCK 4 0 2. SCK (C D) (DI) USI (C) (D) 4 3. ( ) 2 8 4. 8 (16 ) SPI USI SPI SPITransfer: out ldi out ldi out sbis rjmp in ret USIDR,r16 r16,(1< 8 (+ ret) DO SCK DDRB r16 r16 USI USI USITC SCK 16 64 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) (fsck = fck/2) USI SPI SPITransfer_Fast: out ldi ldi out out out out out out out out out out out out out out out out in ret USIDR,r16 r16,(1< USI SPI init: ldi out ... SlaveSPITransfer: out ldi out sbis rjmp in ret USIDR,r16 r16,(1< 8 (+ ret) DO SCK DDRB r16 r16 USI USI IC (TWI) SCL SDA 65 1477E-AVR-12/03 Figure 42. VCC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PBy SDA PBz SCL HOLD SCL Two-wire Clock Control Unit SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PBy SDA PBz PORTBz MASTER SCL Figure42 USI SCL SCL PORTB PB2 TWI Figure 43. SDA SCL S 1-7 ADDRESS 8 R/W 9 ACK 1-8 DATA 9 ACK 1-8 DATA 9 ACK P A B C D E F (Figure 43.) 1. SCL (A) SDA SDA 7 0 PORTB0 0 66 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) (Figure 44.) USISIF 2. SCL (B) SCL 3. SCL (C) SCL 4. ()8 SCL (D) SCL 5. SCL ( SCL(D) 14) SDA R/W R/W 1 ( SDA ) (E) SCL 6. (F) Figure 44. USISIF DQ SDA CLR CLR DQ CLOCK HOLD SCL Write( USISIF) Figure 44. SDA (50 300 ns) SCL SCL CKSEL ( P24" " ) P59"Bit 7 - USISIF: " USI 4 12 / USI UART 4 USI 4 / 0 12 (F) USICS1 67 1477E-AVR-12/03 AIN0 AIN1 AIN0 AIN1 ACO / 1 Figure45 Figure 45. ACBG PA6 (AIN0) MUX PA7 (AIN1) MUX ACME ADC MULTIPLEXER OUTPUT ACSR Bit $08 ($28) / 7 ACD R/W 0 6 ACBG R/W 0 5 ACO R X 4 ACI R/W 0 3 ACIE R/W 0 2 ACME R/W 0 1 ACIS1 R/W 0 0 ACIS0 R/W 0 ACSR * Bit 7 - ACD: ACD ACD ACSR ACIE ACD * Bit 6 - ACBG: ACBG * Bit 5 - ACO: ACO * Bit 4 - ACI: ACI1 ACI0 ACI ACIE SREG I ACI ACI 1 * Bit 3 - ACIE: ACIE 1 I 68 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) * Bit 2 - ACME: ACME ADC (ADCSR ADEN 0)ADMUX MUX3...0 P70Table 33 ACME ADEN PA7(AIN1) * Bits 1, 0 - ACIS1, ACIS0: Table 32 Table 32. ACIS1/ACIS0 (1) ACIS1 0 0 1 1 Note: ACIS0 0 1 0 1 1. ACIS1/ACIS0 ACSR 69 1477E-AVR-12/03 Table 33. (1) ACME 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Notes: ADEN X 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUX3...0(3) XXXX XXXX 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AIN1 AIN1 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6(2) ADC7(2) ADC8 ADC9 ADC10 1. MUX4 2. PA6 PA7 AIN1 AIN0 3. MUX3...0 70 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) * * * * * * * * * * * * * * 10 2 LSB 0.5 LSB 65 - 260 s 11 8 20x 7 ADC 0 - AVCC ADC ADC ADC ATtiny26(L)10ADC ADC11 8 A B 11 A/D dB (1x) 26 dB (20x) ADC 0V (GND) ADC ADC ADC Figure46 ADC AVCC AVCC VCC 0.3V P86"ADC " 2.56V AREF 71 1477E-AVR-12/03 Figure 46. ADC CONVERSION COMPLETE IRQ 8-BIT DATA BUS ADIF ADIE 15 ADC DATA REGISTER (ADCH/ADCL) ADPS0 0 ADC MULTIPLEXER SELECT (ADMUX) ADLAR REFS1 REFS0 MUX4 MUX2 MUX3 MUX1 MUX0 ADC CTRL. & STATUS REGISTER (ADCSR) ADPS2 ADPS1 ADFR ADEN ADSC ADIF PRESCALER MUX DECODER CHANNEL SELECTION GAIN SELECTION CONVERSION LOGIC VCC AREF INTERNAL 2.56 V REFERENCE SAMPLE & HOLD COMPARATOR 10-BIT DAC + GND INTERNAL 1.18 V REFERENCE ADC10 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 + ADC2 ADC1 ADC0 POS. INPUT MUX SINGLE ENDED / DIFFERENTIAL SELECTION ADC[9:0] ADC MULTIPLEXER OUTPUT GAIN AMPLIFIER NEG. INPUT MUX ADC 10 GND AREF1 LSB ADMUXREFS AVCC 2.56V AREF AREF ADMUX MUX ADC GND ADC ADC 0V (GND) ADC ADC - ADC ADC ADCSR ADFR 72 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) ADC ADCSR ADEN ADEN ADEN ADC ADC ADSC 1 1 0 ADC ADC10 ADCADCHADCL ADMUX ADLAR 8 ADCH ADCL ADCH ADCL ADC ADCL ADCH ADC ADCH ADC ADCH ADCL ADC ADCHADCLADC Figure 47. ADC ADEN CK Reset 7-BIT ADC PRESCALER ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE 50 kHz 200 kHz ADC ADC ADCSR ADPS 100 kHz ADC ADCSR ADEN ADC ADEN ADEN ADCSR ADSC ADEN 13 ADC ADC ADC (ADCSRA ADEN ) 25 ADC 125 s 125 s ADC ( ADMUX REFS1:0 ) 125 s ADC 1.5 ADC ADC 13.5 ADC ADC ADC ADIF ADSC ( ) CK/128 CK/16 CK/32 CK/64 CK/2 CK/4 CK/8 73 1477E-AVR-12/03 ADSC ADC ADSC 1 ADC 200 kHz 65 s 15 kSPS Table 34 Figure 48. ADC ( ) Extended Conversion Next Conversion Cycle Number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 ADC Clock ADEN ADSC ADIF ADCH ADCL MSB of Result LSB of Result MUX and REFS Update Sample & Hold Conversion Complete MUX and REFS Update Figure 49. ADC One Conversion Next Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete MUX and REFS Update Figure 50. ADC One Conversion 11 12 13 Next Conversion 1 2 3 4 Cycle Number ADC Clock ADSC ADIF ADCH ADCL MSB of Result LSB of Result Conversion Complete Sample & Hold MUX and REFS Update 74 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Table 34. ADC & ( ) 13.5 1.5 ( ) 25 13 (s) 125 - 500 65 - 260 75 1477E-AVR-12/03 ADC ADC CPUI/O ADC 1. ADC ADC ADEN = 1 ADSC = 0 ADFR = 0 ADIE = 1 2. ADC ( ) CPU ADC 3. ADC ADC CPU ADC ADC (ADIF ) ADC (ADCL, ADCH) V IN 1024 ADC = -------------------------V REF VIN VREF ( P78Table 36 P79Table 37) 0x000 0x3FF 1LSB ( V POS - V NEG ) GAIN 1024 ADC = -----------------------------------------------------------------------------V REF VPOS VNEG GAIN VREF VPOS VNEG ADC 0x000 Figure51 Table 35 (ADCn - ADCm)GAIN VREF Figure 51. Output Code 0x3FF 0x000 0 VREF/GAIN Differential Input Voltage (Volts) 76 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Table 35. VADCn VADCm + VREF /GAIN VADCm + (1023/1024) VREF /GAIN VADCm + (1022/1024) VREF /GAIN ... VADCm + (1/1024) VREF /GAIN VADCm 0x3FF 0x3FF 0x3FE ... 0x001 0x000 1023 1023 1022 ... 1 0 ADMUX = 0xEB (ADC0 - ADC1, 20x 2.56V ) .ADC0 400 mV ADC1 300 mV ADCR = 1024 * 20 * (400 - 300) / 2560 = 800 = 0x320 ADCL 0x00 ADCH 0xC8 ADLAR 0 ADCL = 0x20 ADCH = 0x03 77 1477E-AVR-12/03 ADC ADMUX Bit $07 ($27) / 7 REFS1 R/W 0 6 REFS0 R/W 0 5 ADLAR R/W 0 4 MUX4 R/W 0 3 MUX3 R/W 0 2 MUX2 R/W 0 1 MUX1 R/W 0 0 MUX0 R/W 0 ADMUX * Bit 7, 6 - REFS1, REFS0: Table 36 (ADCSR ADIF ) AVCC AREF(AVCC - 0.2V) ADC AREF Table 36. ADC REFS1 0 0 1 1 REFS0 0 1 0 1 AVCC AREF (PA3) Vref 2.56 V AREF (PA3) 2.56 V AREF * Bit 5 - ADLAR: ADC ADLARADCADC ADLAR ADLAR ADC P85"ADC - ADCL ADCH" * Bits 4..0 - MUX4..MUX0: ADC Table 37 (ADCSR ADIF ) 78 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Table 37. MUX4..0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101(1) 01110 01111 10000 10001(1) 10010 10011 (1) ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 N/A ADC0 ADC0 N/A ADC1 ADC2 ADC2 ADC2 N/A ADC3 ADC4 ADC4 ADC4 ADC4 N/A ADC5 ADC6 ADC6 ADC8 ADC8 N/A ADC9 ADC10 ADC10 1.18V (VBG) 0V (GND) 1. P86" " N/A ADC1 ADC1 ADC1 ADC1 ADC1 ADC3 ADC3 ADC3 ADC3 ADC5 ADC5 ADC5 ADC5 ADC5 ADC9 ADC9 ADC9 ADC9 ADC9 20x 1x 20x 20x 1x 1x 20x 20x 1x 20x 1x 20x 20x 1x 20x 1x 20x 20x 1x 10100 10101 10110 10111 11000 11001 11010 11011 (1) (1) 11100 11101 11110 11111 Note: 79 1477E-AVR-12/03 ADC ADCSR Bit $06 ($26) 7 ADEN R/W 0 6 ADSC R/W 0 5 ADFR R/W 0 4 ADIF R/W 0 3 ADIE R/W 0 2 ADPS2 R/W 0 1 ADPS1 R/W 0 0 ADPS0 R/W 0 ADCSR * Bit 7 - ADEN: ADC ADENADC ADC ADC * Bit 6 - ADSC: ADC ADSC ADC ADSC ADC ADSC ADC ADSC ADC ADSC 1 ADSC ADSC * Bit 5 - ADFR: ADC ADC ADC * Bit 4 - ADIF: ADC ADC ADIF ADIE SREG I ADC ADIF 1 ADIF ADCSR SBI CBI * Bit 3 - ADIE: ADC ADIE SREG I ADC * Bits 2..0 - ADPS2..0: ADC CK ADC Table 38. ADC ADPS2 0 0 0 0 1 1 1 1 ADPS1 0 0 1 1 0 0 1 1 ADPS0 0 1 0 1 0 1 0 1 2 2 4 8 16 32 64 128 80 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) ADC ADCL ADCH ADLAR = 0 Bit $05 ($25) $04 ($24) 15 - ADC7 7 R R 0 0 14 - ADC6 6 R R 0 0 13 - ADC5 5 R R 0 0 12 - ADC4 4 R R 0 0 11 - ADC3 3 R R 0 0 10 - ADC2 2 R R 0 0 9 ADC9 ADC1 1 R R 0 0 8 ADC8 ADC0 0 R R 0 0 ADCH ADCL ADLAR = 1 Bit $05 ($25) $04 ($24) 15 ADC9 ADC1 7 R R 0 0 14 ADC8 ADC0 6 R R 0 0 13 ADC7 - 5 R R 0 0 12 ADC6 - 4 R R 0 0 11 ADC5 - 3 R R 0 0 10 ADC4 - 2 R R 0 0 9 ADC3 - 1 R R 0 0 8 ADC2 - 0 R R 0 0 ADCH ADCL ADC ADMUX ADLAR ADLAR ( ) 8 ADCH ADCL ADCH * ADC9..0: ADC ADC P79Table 37 $000 $3FF 1LSB ADC ADMUX ADC ATtiny26(L) (EMI) 1. ATtiny26(L) PCB 2. 3. Figure52 AVCC LC VCC 4. ADC CPU 5. ADC ADC 5 mV ( 3 mV) 2LSBs 81 1477E-AVR-12/03 20x ADC 10 mV (2.56V) 10 ADC 1LSB 2.56 mV 4LSBs 5 mV 2LSBs 1LSB Figure 52. ADC Analog Ground Plane 100nF 1477E-AVR-12/03 (MOSI/DI/SDA/OC1A) PB0 1 2 3 4 5 ATtiny26/L 20 19 18 17 16 15 14 13 12 11 PA0 (ADC0) (MISO/DO/OC1A) PB1 (SCK/SCL/OC1B) PB2 (OC1B) PB3 VCC PA1 (ADC1) PA2 (ADC2) PA3 (AREF) GND AVCC GND (ADC7/XTAL1) PB4 6 7 8 9 10 PA4 (ADC3) PA5 (ADC4) PA6 (ADC5/AIN0) PA7 (ADC6/AIN1) (ADC8/XTAL2) PB5 (ADC9/INT0/T0) PB6 (ADC10/RESET) PB7 82 ATtiny26(L) 10 ATtiny26(L) I/O I/O AVR I/O - - SBI CBI ( / ) ( / ) LED VCC Figure53 Figure 53. I/O Rpu Pxn Logic Cpin See Figure "General Digital I/O" for Details "x" "n" PORTB3 B 3 PORTxn I/O P102"I/O " I/O : - PORTx - DDRx - PINx / PINx "1" "0" "1" MCUCR PUD I/O P87" I/O " P92" " I/O I/O I/O Figure54 I/O 83 1477E-AVR-12/03 Figure 54. I/O(1) PUD Q D DDxn Q CLR RESET WDx RDx Pxn Q D PORTxn Q CLR WPx RESET SLEEP RRx SYNCHRONIZER D Q D Q RPx PINxn L Q Q clk I/O PUD: SLEEP: clkI/O: PULLUP DISABLE SLEEP CONTROL I/O CLOCK WDx: RDx: WPx: RRx: RPx: WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN Note: 1. WRx, WPx, WDx, RRx, RPx RDx clkI/O, SLEEP PUD : DDxn PORTxn PINxn P102"I/O " DDxn DDRx PORTxn PORTx PINxn PINx DDxn DDxn "1" Pxn PORTxn "1" PORTxn PORTxn "1" ("1") ("0") ( )({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b11) ({DDxn, PORTxn} = 0b01) ({DDxn, PORTxn} = 0b10) SFIOR PUD ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b11) 84 ATtiny26(L) 1477E-AVR-12/03 DATA BUS ATtiny26(L) Table 39 Table 39. DDxn 0 0 0 1 1 PORTxn 0 1 1 0 1 PUD( MCUCR) X 0 1 X X I/O No Yes No No No (Hi-Z) (Hi-Z) ( ) ( ) DDxn PINxn Figure54 PINxn Figure55 tpd,max tpd,min Figure 55. SYSTEM CLK INSTRUCTIONS SYNC LATCH PINxn r17 0x00 t pd, max t pd, min 0xFF XXX XXX in r17, PINx SYNC LATCH PINxn pd,max tpd,min t 1/2 11/2 Figure56. out in nop out SYNC LATCH tpd 85 1477E-AVR-12/03 Figure 56. SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17 0x00 t pd 0xFF out PORTx, r16 nop 0xFF in r17, PINx 86 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) B 0 1 2 3 4 7 6 7 nop (1) ... ; ; ldi ldi out out nop ; in ... r16,PINB r16,(1< C unsigned char i; ... /* */ /* */ PORTB = (1< 1. Figure54 ( ) SLEEP MCU Standby VCC/2 SLEEP SLEEP SLEEP P92" " ("1") " " "1" "0" "0" "1" ( ) VCC GND 87 1477E-AVR-12/03 I/O Figure57 Figure54 AVR Figure 57. (1) PUOExn PUOVxn 1 0 PUD DDOExn DDOVxn 1 0 QD DDxn Q CLR PVOExn PVOVxn WDx RESET RDx 1 Pxn 0 Q D PORTxn DIEOExn DIEOVxn 1 0 Q CLR WPx RESET RRx SLEEP SYNCHRONIZER D SET RPx Q D Q PINxn L CLR Q CLR Q clk I/O DIxn AIOxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL PUD: WDx: RDx: RRx: WPx: RPx: clkI/O: DIxn: AIOxn: PULLUP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx Note: 1. WPx, WDx, RLx, RPxRDx I/O, SLEEP clk PUD 88 ATtiny26(L) 1477E-AVR-12/03 DATA BUS ATtiny26(L) Table 40 Figure57 Table 40. PUOE PUOV {DDxn, PORTxn, PUD} = 0b010 PUOE DDxnPORTxn PUD PUOV / / DDOV DDxn DDOE DDOV / / DDxn PVOV PVOE PORTxn PVOE PVOV PORTxn PTOE DIEOV DIEOE MCU ( ) / PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO / 89 1477E-AVR-12/03 MCU MCUCR MCU Bit $35 ($55) / 7 - R 0 6 PUD R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 - R 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR * Bit 6 - PUD: DDxn PORTxn ({DDxn, PORTxn} = 0b01) I/O P88" " A A ADC Table 41 A ADC P75" " P72" " PA7 PA6 PA3 P37" " Table 41. A PA7 ADC6 (ADC 6) AIN1 ( ) PCINT1 ( 1) ADC5 (ADC 5) AIN0 ( ) PCINT1 ( 1) ADC4 (ADC 4) ADC3 (ADC 3) AREF (ADC ) PCINT1 ( 1) ADC2 (ADC 2) ADC1 (ADC 1) ADC0 (ADC 0) PA6 PA5 PA4 PA3 PA2 PA1 PA0 Table 42Table 43 AP88Figure57 PA7 PA6 PA3 PA3 * ADC6/AIN1 - A, Bit 7 AIN1 ADC6 ADC 6 PCINT1 1 SLEEP PA7 * ADC5/AIN0 - A, Bit 6 AIN0 ADC5ADC 5 PCINT1 1 SLEEP PA7 90 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) * ADC4, ADC3 - A, Bit 5, 4 ADC4/ADC3ADC 4 3 * AREF/PCINT1 - A, Bit 3 AREF ADC PA3 AREF ( ADMUX REFS0 1) (2.56V) PCINT1 1 ADC SLEEP PA3 Table 42. PA7..PA4 PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PA7/ADC6/ AIN1/PCINT1 0 0 0 0 0 0 PCINT1_ENABLE ACSR[ACD] 1 PCINT1 ADC6 AIN1 (1) PA6/ADC5/ AIN0/PCINT1 0 0 0 0 0 0 * PCINT1_ENABLE * ACSR[ACD] 1 PCINT1 ADC5 AIN0 (1) PA5/ADC4 0 0 0 0 0 0 0 0 - ADC4 PA4/ADC3 0 0 0 0 0 0 0 0 - ADC3 91 1477E-AVR-12/03 Table 43. PA3..PA0 PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Notes: PA3/AREF/PCINT1 ADMUX[REFS0] 0 ADMUX[REFS0] 0 0 0 PCINT1_ENABLE(1) * ~(2)ADMUX[REFS0] 1 PCINT1 PA2/ADC2 0 0 0 0 0 0 0 0 - ADC2 PA1/ADC1 0 0 0 0 0 0 0 0 - ADC1 PA0/ADC0 0 0 0 0 0 0 0 0 - ADC0 1. PCINT1 GIMSKPCIE1 P37" " 2. "~" 92 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) B B ADC T/CUSI SPI ADC P75" " P6" " P42" / " USI P61" - USI" PB7 - PB0 P37" " P103" " B Table 44 Table 44. B PB7 ADC10 (ADC 10) RESET ( ) PCINT1 ( 1) ADC9 (ADC 9) INT0 ( 0 ) T0 (T/C0 ) PCINT1 ( 1) ADC8 (ADC l 8) XTAL2 ( ) PCINT1 ( 1) ADC7 (ADC 7) XTAL1 ( ) PCINT1 ( 1) OC1B (T/C1 PWM B T/C1 B ) PCINT0 ( 0) SCK (USI / ) SCL (USI ) OC1B ( T/C1 PWM B) PCINT0 ( 0) DO (USI ) OC1A (T/C1 PWM A, T/C1 A ) PCINT0 ( 0) DI (USI ) SDA (USI ) OC1A ( T/C1 PWM A) PCINT0 ( 0) PB6 PB5 PB4 PB3 PB2 PB1 PB0 * ADC10/RESET/PCINT1 - B, Bit 7 ADC10ADC 10 RESET RSTDISBL "1" RESET PCINT1 1 RESET SLEEP PB7 93 1477E-AVR-12/03 * ADC9/INT0/T0/PCINT1 - B, Bit 6 ADC9ADC 9 INT0 0 PB6 GIMSK INT0 1 T0 T/C0 T/C0 TCCR0 CS02 CS01 1 PCINT1 1 INT0 T0 SLEEP PB6 * ADC8/XTAL2/PCINT1 - B, Bit 5 ADC8ADC 8 XTAL2 2 RC PLL I/O RC PLL PB5 I/O PCINT1 1 XTAL2 SLEEP PB5 * ADC7/XTAL1/PCINT1 - B, Bit 4 ADC7ADC 7 XTAL1 1 RC PLL I/O RC PLL PB4 I/O PCINT1 1 XTAL1 SLEEP PB4 * OC1B/PCINT0 - B, Bit 3 OC1B PB3 T/C1 B (DDB3 "1") OC1B PWM PCINT0 0 OC1B SLEEP PB3 * SCK/SCL/OC1B/PCINT0 - B, Bit 2 SCK USI / SPI USI DDRB2 SCL USI PORTB2 USI SCL DDRB2 1 USI OC1B T/C1 PWM B USI PB2 T/C1 PWM DDB2 1 94 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) PCINT1 0 OC1B USI SCK/SCL SLEEP PB2 * DO/OC1A/PCINT0 - B, Bit 1 DO USI DDB1 1 PORTB1 DO PORTB1 PORTB1 1 OC1A PB1 T/C1 A (DDB1 "1") OC1B PWM PCINT0 0 OC1A USI DO SLEEP PB1 * DI/SDA/OC1A/PCINT0 - B, Bit 0 DIUSI USI SDA USI SDA PORTB0 USI 0(DDB0 1) USI OC1A T/C1 PWM A USI PB0 T/C1 PWM DDB0 1 PCINT0 0 OC1A USI DI SDA SLEEPPB0 95 1477E-AVR-12/03 Table 45 Table 46 B P92" " Table 45. PB7..PB4 PUOE PUOV DDOE DDOV PVOE PVOV DIEOE PB7/ADC10/RESET/ PCINT1 RSTDSBL 1 RSTDSBL(1) 0 0 0 PCINT1_ENABLE(2) | RSTDSBL(1) (1) PB6/ADC9/INT0/TO/ PCINT1 0 0 0 0 0 0 ~T0_EXT_CLOCK (6) * PCINT1_ENABLE(2) | INT0_ENABLE(4) 1 PB5/ADC8/XTAL2/ PCINT1 ~ PB5IOENABLE 0 ~PB5IOENABLE(3) 0 0 0 PCINT1_ENABLE(2) | ~PB5IOENABLE(3) PCINT1_ENABLE(2) * PB5IOENABLE(3) PCINT1 ADC8, XTAL2 (5) (3) PB4/ADC7/XTAL1 ~PB4IOENABLE(3) 0 ~PB4IOENABLE(3) 0 0 0 PCINT_ ENABLE (2) | ~PB4IOENABLE(3) | EXT_CLOCK_ENABLE(7) PCINT1_ENABLE(2)* PB4IOENABLE(3) | EXT_CLOCK_ENABLE , PCINT1 XTAL1 DIEOV PCINT1_ENABLE(2) * ~(5)RSTDSBL(1) PCINT1 ADC10 DI AIO Notes: INT0, T0, PCINT1 ADC9 1. RSTDISBL ( ) P20" " 2. GIMSKPCIE1P37"" PCINT1 3. PB5IOENABLE PB4IOENABLE PLLCK CKSEL P26" " 4. GIMSK INT0 P37" " 5. "~" 6. T/C0 P43"8 T/C0" 7. PLLCK CKSEL P26" " 96 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Table 46. PB3..PB0 PUOE PUOV DDOE DDOV PVOE PB3/OC1B/PCINT0 0 0 0 0 OC1B_ENABLE(1) PB2/SCK/SCL/OC1B/PCI NT0 USI_TWO-WIRE(3) 0 USI_TWO-WIRE (3) PB1/DO/OC1A/PCINT0 0 0 0 0 USI_THREE-WIRE(3) | OC1A_ENABLE(1) USI_THREE-WIRE(3) * DO(6) | ~USI_THREEWIRE * OC1A_ENABLE(1) * OC1A ~(USI_THREE-WIRE | OC1A_ENABLE) * PCINT0_ENABLE(2) PB0/DI/SDA/OC1A USI_TWO-WIRE(3) 0 USI_TWO-WIRE(3) (~SDA | ~PORTB0) * DDB0 USI_TWO-WIRE(3)* DDB0 | OC1A_ENABLE(1) ~(USI_TWO-WIRE* DDB0) * OC1A_ENABLE(1) * OC1A ~(USI_TWO-WIRE(3) | USI_THREE-WIRE(3) | OC1A_ENABLE(1)) * PCINT0_ENABLE(2) | USI_START_I.ENABLE(5) 1 PCINT0, SDA - (USI_SCL_HOLD(4) | ~(8)PORTB2) * DDB2 USI_TWO-WIRE(3) * DDB2 | OC1B_ENABLE(1) ~(USI_TWO-WIRE * DDB2) * OC1B PVOV OC1B DIEOE PCINT0_ENABLE(2) * ~OC1B_ENABLE(1) ~(USI_TWO-WIRE | USI_THREE-WIRE | OC1B_ENABLE) * PCINT0_ENABLE(2) | USI_START_I.ENABLE(5) 1 PCINT0, SCL, SCK - DIEOV DI AIO Notes: 1 PCINT0 - 1 PCINT0 - 1. T/C1 T/C1 PWM OC1A/OC1B OC1A/OC1B P45"8 T/C1" 2. GIMSKPCIE0P37"" PCINT0 3. P61" - USI" 4. SCL P61" - USI" 5. USICR USISIE P61" - USI" USI 6. USI DO P61" - USI" 7. USI SDA DI P61" - USI" 8. "~" 97 1477E-AVR-12/03 I/O A PORTA Bit $1B ($3B) / 7 PORTA7 6 PORTA6 5 PORTA5 4 PORTA4 3 PORTA3 2 PORTA2 1 PORTA1 0 PORTA0 PORTA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 A DDRA Bit $1A ($3A) / 7 DDA7 R/W 0 6 DDA6 R/W 0 5 DDA5 R/W 0 4 DDA4 R/W 0 3 DDA3 R/W 0 2 DDA2 R/W 0 1 DDA1 R/W 0 0 DDA0 R/W 0 DDRA A PINA Bit $19 ($39) / 7 PINA7 R N/A 6 PINA6 R N/A 5 PINA5 R N/A 4 PINA4 R N/A 3 PINA3 R N/A 2 PINA2 R N/A 1 PINA1 R N/A 0 PINA0 R N/A PINA B PORTB Bit $18 ($38) / 7 PORTB7 R/W 0 6 PORTB6 R/W 0 5 PORTB5 R/W 0 4 PORTB4 R/W 0 3 PORTB3 R/W 0 2 PORTB2 R/W 0 1 PORTB1 R/W 0 0 PORTB0 R/W 0 PORTB B DDRB Bit $17 ($37) / 7 DDB7 R/W 0 6 DDB6 R/W 0 5 DDB5 R/W 0 4 DDB4 R/W 0 3 DDB3 R/W 0 2 DDB2 R/W 0 1 DDB1 R/W 0 0 DDB0 R/W 0 DDRB B PINB Bit $16 ($36) / 7 PINB7 R N/A 6 PINB6 R N/A 5 PINB5 R N/A 4 PINB4 R N/A 3 PINB3 R N/A 2 PINB2 R N/A 1 PINB1 R N/A 0 PINB0 R N/A PINB 98 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) ATtiny26 2 ("0") ("1") Table 48 "1" Table 47. (1) 7 6 5 4 3 2 LB2 LB1 Note: 1 0 - - - - - - 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1. "1" "0" Table 48. LB 1 2 3 Notes: LB2(2) 1 1 0 LB1(2) 1 0 0 Flash EEPROM (1) Flash EEPROM (1) 1. 2. "1" , "0" 99 1477E-AVR-12/03 ATtiny26 Table 49Table 50 0 Table 49. 7 6 5 RSTDISBL(2) SPIEN(1) EESAVE BODLEVEL BODEN Notes: 4 3 2 1 0 - - 1 ( ) 1 ( ) 1 ( ) 1 ( PB7 RESET ) 0 ( SPI ) 1 ( EEPROM ) 1 ( ) 1 ( BOD ) - PB7 I/O RESET EEPROM 1. SPIEN 2. RSTDISBL Table 50. PLLCK CKOPT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Notes: (3) 7 6 5 4 3 2 1 0 PLL 1 ( ) 1 ( ) 1 ( )(1) 0 ( )(1) 0 ( )(2) 0 ( )(2) 0 ( )(2) 1 ( )(2) 1. SUT1..0 P29Table 13 2. CKSEL3..0 RC 1MHz P25Table 4 3. CKOPT CKSEL P24" " 1(LB1) 100 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) EESAVE Atmel ATtiny26 1. $000: $1E ( Atmel ) 2. $001: $91 ( 2KB Flash) 3. $002: $09 ( $001 $91 ATtiny26 ) ATtiny26RC 0x000 0x00010x0002 0x0003 12 4 8 MHz1 MHz OSCCAL P30" - OSCCAL" ATtiny26 Flash EEPROM 250 ns ATtiny26 Figure58 Table 51 XA1/XA0 XTAL1 Table 53 WR OE Table 54 Figure 58. +5V WR XA0 XA1/BS2 PAGEL/BS1 OE RDY/BSY +12 V PB0 PB1 PB2 AVCC PB3 PB5 PB6 RESET XTAL1/PB4 GND PA7: PA0 VCC +5V DATA 101 1477E-AVR-12/03 Table 51. WR XA0 XA1/BS2(1) PAGEL/BS1(1) OE RDY/BSY DATA Note: PB0 PB1 PB2 PB3 PB5 PB6 PA7:0 I/O I I I I I O I/O ( ) XTAL 0 XTAL1 2 ("0" , "1" ) EEPROM 1 ("0" , "1" ) ( ) 0: , 1: (OE ) 1. " BS1 " " PAGEL/BS1 " . Table 52. Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] 0 0 0 0 PAGEL/BS1 XA1/BS2 XA0 WR 102 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Table 53. XA1 XA0 (1) XA1 0 0 1 1 Note: XA0 0 1 0 1 XTAL1 Flash EEPROM ( BS1 ) ( BS1 Flash ) 1. [XA1, XA0] = 0b11 " "XTAL1 BS2 XA1 BS2 (OE ) XTAL1 BS2 Table 54. Command Byte 1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011 Command Executed Flash EEPROM Flash EEPROM Table 55. Flash Flash 1K (2K ) 16 PCWORD PC[3:0] 64 PCPAGE PC[9:4] PCMSB 9 Table 56. EEPROM EEPROM 128 4 PCWORD EEA[1:0] 32 PCPAGE EEA[7:0] EEAMSB 7 103 1477E-AVR-12/03 1. VCC GND 4.5 - 5.5V 100 s 2. RESET XTAL1 6 3. P102Table 52 Prog_enable "0000" 100 ns 4. RESET 11.5 - 12.5V RESET +12V 100 ns Prog_enable RESET RSTDISBL RC XTAL1 1. P102Table 52 Prog_enable "0000" 2. VCC GND 4.5 - 5.5V RESET 11.5 - 12.5V 3. 100 ns 4. (CKSEL3:0 = 0b0000) RESET (RSTDISBL ) 5. RESET 0b0 6. * * * $FF Flash EEPROM( EESAVE ) Flash EEPROM 256 104 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Flash EEPROM(1) Flash / EEPROM Note: 1. EESAVE EEPRPOM " " 1. XA1 XA0 10 2. BS1 0 3. DATA "1000 0000" 4. XTAL1 5. WR RDY/BSY 6. RDY/BSY Flash Flash P103Table 55 Flash Flash A " Flash" 1. XA1 XA0 "10" 2. BS1 0 3. DATA "0001 0000" Flash 4. XTAL1 B 1. XA1 XA0 "00" 2. BS1 0 3. DATA ($00 - $FF) 4. XTAL1 C 1. XA1 XA0 "01" 2. DATA ($00 - $FF) 3. XTAL1 D 1. BS1 "1" 2. XA1 XA0 "01" 3. DATA ($00 - $FF) 4. XTAL1 E. B D FLASH P106Figure59 8 ( < 256) 105 1477E-AVR-12/03 F 1. XA1 XA0 "00" 2. BS1 "1" 3. DATA ($00 - $FF) 4. XTAL1 G. 1. BS1 "0" 2. WR RDY/BSY 3. RDY/BSY ( Figure60 ) H B G Flash I 1. XA1 XA0 "10" 2. DATA "0000 0000" 3. XTAL1 Figure 59. Flash (1) PCMSB PROGRAM COUNTER PCPAGE PAGEMSB PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 1. PCPAGE PCWORD P103Table 55 106 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 60. Flash (1) E A DATA $10 B ADDR. LOW C D B C D F G XX DATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH ADDR. HIGH XA1/BS2 XA0 PAGEL/BS1 XTAL1 WR RDY/BSY RESET +12V OE Note: 1. " XX" Flash EEPROM P103Table 56 EEPROM EEPROM EEPROM ( P109" Flash " ) 1. A "0001 0001" 2. B ($00 - $FF) 3. C ($00 - $FF) J 2 3 K EEPROM 1. BS "0" 2. WR EEPROM RDY/BSY 3. RDY/BSY ( Figure61) 107 1477E-AVR-12/03 Figure 61. EEPROM J A DATA $11 B ADDR. LOW C DATA B ADDR. LOW C DATA XX K XA1/BS2 XA0 PAGEL/BS1 XTAL1 WR RDY/BSY RESET +12V OE Flash Flash ( P109" Flash " ) 1. A "0000 0010" 2. F ($00 - $03) 3. B ($00 - $FF) 4. OE "0" BS1 "0" DATA Flash 5. BS "1" DATA Flash 6. OE "1" EEPROM EEPROM ( P109" Flash " ) 1. A "0000 0011" 2. B ($00 - $FF) 3. OE "0" BS1 "0" DATA EEPROM 4. OE "1" ( P109" Flash " ) 1. A "0100 0000" 2. C 0 3. Set BS1 and BS2 to "0". 4. WR RDY/BSY 108 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) ( P109" Flash " ) 1. A "0100 0000" 2. C 0 3. BS1 "1" BS2 "0" 4. WR RDY/BSY 5. BS1 "0" Figure 62. Write Fuse Low Byte A DATA $40 Write Fuse High Byte A C DATA XX C DATA XX $40 XA1/BS2 XA0 PAGEL/BS1 XTAL1 WR RDY/BSY RESET +12V OE ( P109" Flash " ) 1. A "0010 0000" 2. C. n 0 3. WR RDY/BSY ( P109" Flash " ) 1. A "0000 0100" 2. OE BS2 BS1 "0" DATA ("0" ) 3. OE"0" BS2BS1"1" DATA("0") 4. OE BS2 "0" BS1 "1" DATA ("0" ) 5. OE "1" 109 1477E-AVR-12/03 Figure 63. BS1 BS2 Fuse Low Byte 0 DATA 0 1 Lock Bits BS1 Fuse High Byte BS2 1 ( P109" Flash " ) 1. A "0000 1000" 2. B $00 - $02 3. OE BS1 "0" DATA 4. OE "1" ( P109" Flash " ) 1. A "0000 1000" 2. B 3. OE "0" BS1 "1" DATA 4. OE "1" Figure 64. tXLWL XTAL1 tDVXH Data & Contol (DATA, XA0, XA1/BS2 PAGEL/BS1) WR WLRL tXHXL tXLDX t BVWL tWLWH tWLBX RDY/BSY tWLRH 110 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 65. (1) LOAD ADDRESS (LOW BYTE) t XLXH LOAD DATA (LOW BYTE) t XLXH LOAD DATA (HIGH BYTE) t XLXH LOAD ADDRESS (LOW BYTE) XTAL1 PAGEL/BS1 DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1/BS2 Note: 1. Figure64 (tDVXH tXHXL tXLDX) Figure 66. ( )(1) LOAD ADDRESS (LOW BYTE) tXLOL READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) XTAL1 tBHDV PAGEL/BS1 tOLDV OE tOHDZ DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1/BS2 Note: 1. Figure64 ( tDVXH tXHXL tXLDX) 111 1477E-AVR-12/03 Table 57. VCC = 5V 10% VPP IPP tDVXH tXLXH tXHXL tXLDX tXLWL tWLBX tBVWL tWLWH tWLRL tWLRH tWLRH_CE tXLOL tBVDV tOLDV tOHDZ Notes: 1. 2. XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 WR WR BS2/1 WR BS1 WR WR RDY/BSY WR RDY/BSY (1) WR RDY/BSY XTAL1 OE BS1 DATA OE DATA OE DATA Flash EEPROM tWLRH tWLRH_CE (2) 11.5 12.5 250 V A ns ns ns ns ns ns ns ns 67 200 150 67 0 67 67 150 0 3.7 7.5 0 0 250 250 250 1 4.5 9 s ms ms ns ns ns ns 112 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) RESET SPI Flash EEPROM SCK MOSI( ) MISO( ) RESET P113Table 58 SPI SPI SPI MOSI MISO Table 58. MOSI MISO SCK PB0 PB1 PB2 I/O I O I Figure 67. (1) 2.7 - 5.5V VCC 2.7 - 5.5V (2) MOSI MISO SCK PB0 PB1 PB2 AVCC XTAL1 RESET GND Notes: 1. XTAL1 2. VCC -0.3V < AVCC < VCC +0.3V AVCC 2.7 - 5.5V EEPROM MCU EEPROM $FF CKSEL (SCK) fck < 12 MHz 2 CPU fck >= 12 MHz 3 CPU > fck < 12 MHz 2 CPU fck >= 12 MHz 3 CPU > SPI ATtiny26 SCK ATtiny26 SCK Figure68 Figure69 Table 69 113 1477E-AVR-12/03 ATtiny26 ( Table 60 4 ) 1. RESET SCK "0" VCC GND SCK SCK RESET 2 CPU 2. 20 ms MOSI 3. ($53) 4 $53 RESET 4. Flash P103Table 55 4 LSB 8 tWD_FLASH ( Table 59) Flash 5. EEPROM EEPROM tWD_EEPROM ( Table 59) $FF 6. MISO 7. RESET 8. ( ) RESET "1" VCC 114 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Flash Flash $FF Flash $FF $FF tWD_FLASH $FF 0xFF tWD_FLASH Table 59 EEPROM $FF $FF $FF $FF EEPROM $FF tWD_EEPROM tWD_EEPROM Table 59 Table 59. Flash EEPROM tWD_FLASH tWD_EEPROM tWD_ERASE tWD_FUSE 4.5 ms 9.0 ms 9.0 ms 4.5 ms EEPROM Figure 68. SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK) SAMPLE MSB LSB MSB LSB 115 1477E-AVR-12/03 Table 60. 1 1010 1100 1010 1100 0010 H000 0100 H000 2 0101 0011 100x xxxx xxxx xxaa xxxx xxxx 3 xxxx xxxx xxxx xxxx bbbb bbbb xxxx bbbb 4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii RESET EEPROM Flash a:b H( ) o b H( ) i a:b EEPROM b o EEPROM b i "0" "1" P99Table 47 "0" P99Table 47 b o "0" "1" EEPROM EEPROM Note: 0100 1100 1010 0000 1100 0000 0101 1000 1010 1100 0011 0000 1010 1100 1010 1100 0101 0000 0101 1000 0011 1000 xxxx xxaa xxxx xxxx xxxx xxxx 0000 0000 111x xxxx xxxx xxxx 1010 0000 1010 1000 0000 0000 0000 1000 xxxx xxxx bbbb xxxx xbbb bbbb xbbb bbbb xxxx xxxx xxxx xxxx xxxx xxbb xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 00bb xxxx xxxx oooo oooo iiii iiii xxxx xxoo 1111 11ii oooo oooo iiii iiii xxxi iiii oooo oooo xxxo oooo oooo oooo P100Table 50 P100Table 49 "0" "1" "0" "1" P100Table 50 "0" "1" P100Table 49 o. a = b = H = 0 - 1 - o = i = x = Figure 69. MOSI t OVSH SCK t SHSL MISO t SLIV t SHOX tSLSH 116 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Table 61. TA = -40C 85C VCC = 2.7V - 5.5V ( )(1) 1/tCLCL tCLCL 1/tCLCL tCLCL tSHSL tSLSH tOVSH tSHOX tSLIV Note: (VCC = 2.7 - 5.5 V) (VCC = 2.7 - 5.5 V) (VCC = 4.5 - 5.5 V) (VCC = 4.5 - 5.5 V) SCK SCK SCK MOSI SCK MOSI MISO SCK 1. fck < 12 MHz 2 tCLCLfck >= 12 MHz 3 tCLCL 0 125 0 62.5 2 tCLCL 2 tCLCL (1) (1) 8 MHz ns 16 MHz ns ns ns ns ns tCLCL 2 tCLCL 20 ns 117 1477E-AVR-12/03 * ........................................................ -55C +125C ........................................................ -65C +150C RESET.......... -1.0V VCC + 0.5V RESET .................................. -0.5V +13.0V .................................................................... 6.0V I/O ......................................... 40.0 mA *NOTICE: " " VCC GND ................................ 200.0 mA TA = -40C - 85C VCC = 2.7V-5.5V ( ) VIL VIL1 VIH VIH1 VIH2 VOL VOH IIL IIH RRST Rpu ( A B) (4) XTAL1 XTAL1 XTAL1 RESET XTAL1 RESET IOL = 20 mAVCC = 5V IOL = 10 mAVCC = 3V IOH = -20 mAVCC = 5V IOH = -10 mA VCC = 3V Vcc = 5.5V ( ) Vcc = 5.5V ( ) -0.5 -0.5 0.6VCC(3) 0.8VCC(3) 0.9VCC(3) 0.2VCC 0.1VCC VCC +0.5 VCC +0.5 VCC +0.5 0.7 0.5 V V V V V V V V V (5) ( A B) I/O I/O Reset I/O 4.2 2.3 1 1 20 20 100 100 A A k k 118 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) TA = -40C - 85C VCC = 2.7V-5.5V ( ) (Continued) 1 MHz,VCC = 3V (ATtiny26L) 4 MHz, VCC = 3V (ATtiny26L) 8 MHz, VCC = 5V (ATtiny26) 1 MHz, VCC = 3V (ATtiny26L) 4 MHz, VCC = 3V (ATtiny26L) 8 MHz, VCC = 5V (ATtiny26) (6) VACIO IACLK tACID Notes: 1. 2. 3. 4. WDT VCC = 3V WDT VCC = 3V VCC = 5V Vin = VCC/2 VCC = 5V Vin = VCC/2 VCC = 2.7V VCC = 4.0V -50 750 500 0.70(1) 2.5(1) 8(1) 0.18(1) 0.75(1) 3.5(1) 7.5(1) 0.3 (1) mA 6 15 mA mA mA ICC 2 7 15 3 40 50 mA mA A A mV nA ns <10 25C " " " " ()I/O(20 mA CC = 5V10 mAVCC = 3V) V 1] IOL 400 mA 2] A0 - A7 IOL 300 mA 3] B0 - B7 IOL 300 mA IOL VOL 5. ( ) I/O (20 mA CC = 5V 10 mAVCC = 3V) V 1] IOH 400 mA 2] A0 - A7 IOH 300 mA 3] B0 - B7 IOH 300 mA IOH VOH 6. VCC 2.5V 119 1477E-AVR-12/03 Figure 70. V IH1 V IL1 Table 62. VCC = 2.7 - 5.5V 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL 0 125 50 50 1.6 1.6 2 8 VCC = 4.5 - 5.5V 0 62.5 25 25 0.5 0.5 2 16 MHz ns ns ns s s tCLCL 120 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) ADC Table 63. ADC TA = -40C 85C VREF = 4VVCC = 4V ADC = 200 kHz VREF = 4VVCC = 4V ADC = 1 MHz ( INL DNL ) VREF = 4VVCC = 4V ADC = 200 kHz VREF = 4VVCC = 4V ADC = 1 MHz (INL) VREF = 4VVCC = 4V ADC = 200 kHz VREF = 4VVCC = 4V ADC = 200 kHz VREF = 4VVCC = 4V ADC = 200 kHz VREF = 4VVCC = 4V ADC = 200 kHz 50 13 VCC - 0.3 2.0 GND 0 38.5 2.3 2.56 32 100 2.7 (1) 10 1 Bits LSB 2 LSB 1 LSB 2 LSB 0.5 LSB (DNL) 0.5 LSB 0.75 LSB AVCC VREF VIN ADC VINT RREF RAIN Note: 1. AVCC 2.7V 2. AVCC 5.5V 0.5 1000 260 VCC + 0.3 AVCC VREF 1023 (2) LSB kHz s V V V LSB kHz V k M 121 1477E-AVR-12/03 Table 64. ADC TA = -40C 85C Gain = 1x Gain = 20x Gain = 1x VREF = 4V VCC = 5V ADC = 50 - 200 kHz Gain = 20x VREF = 4V VCC = 5V ADC = 50 - 200 kHz Gain = 1x VREF = 4V VCC = 5V ADC = 50 - 200 kHz Gain = 20x VREF = 4V VCC = 5V ADC = 50 - 200 kHz Gain = 1x Gain = 20x Gain = 1x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz Gain = 20x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz 50 26 VCC - 0.3(1) 2.0 GND 0 0 4 2.3 2.56 32 100 2.7 24 10 10 Bits Bits LSB 27 LSB 1.5 LSB (INL) ( ) 2 2 2.5 4 LSB % % LSB 6 200 65 VCC + 0.3(2) AVCC - 0.5 VCC VREF/Gain 1023 LSB kHz s V V V V LSB kHz V k M AVCC VREF VIN VDIFF ADC VINT RREF RAIN Notes: 1. AVCC 2.7V 2. AVCC 5.5V 122 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) ATtiny26 I/O I/O I/O I/O CL*VCC*f CL = VCC = f = I/O Figure 71. (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 1.6 1.4 1.2 1 ICC (mA) 0.8 0.6 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 Frequency (MHz) 0.6 0.7 0.8 0.9 1 5.5V 5.0V 4.5V 4.0V 3.3V 3.0V 2.7V 123 1477E-AVR-12/03 Figure 72. (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 25 5.5V 20 5.0V 4.5V ICC (mA) 15 10 4.0V 3.3V 5 2.7V 0 0 2 4 6 8 10 Frequency (MHz) 12 3.0V 14 16 18 20 Figure 73. VCC ( RC 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 14 12 10 ICC (mA) 8 6 4 2 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 -40C 25C 85C 124 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 74. VCC ( RC 4 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4 MHz 8 7 6 5 ICC (mA) 4 3 2 1 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 85C 25C -40C Figure 75. VCC ( RC 2MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 2 MHz 4 3.5 3 2.5 ICC (mA) 2 1.5 1 0.5 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 85C 25C -40C 125 1477E-AVR-12/03 Figure 76. VCC ( RC 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 1.8 1.6 1.4 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 25C 85C -40C Figure 77. VCC (PLL ) ACTIVE SUPPLY CURRENT vs. VCC PLL OSCILLATOR 25 20 -40C 25C 85C ICC (mA) 15 10 5 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 126 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 78. VCC (32 kHz ) ACTIVE SUPPLY CURRENT vs. VCC 32kHz EXTERNAL OSCILLATOR 70 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 25C Figure 79. (0.1 - 1.0 MHz) ICC (uA) IDLE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 0.6 0.5 5.5V 5.0V 0.4 ICC (mA) 4.5V 0.3 4.0V 3.3V 3.0V 2.7V 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 Frequency (MHz) 0.6 0.7 0.8 0.9 1 127 1477E-AVR-12/03 Figure 80. (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 12 10 5.5V 5.0V 8 ICC (mA) 4.5V 6 4.0V 4 2 3.3V 2.7V 3.0V 10 Frequency (MHz) 12 14 16 18 20 0 0 2 4 6 8 Figure 81. VCC ( RC 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 7 6 5 ICC (mA) 4 3 2 1 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 -40C 25C 85C 128 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 82. VCC ( RC 4 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4 MHz 3.5 3 2.5 ICC (mA) 2 1.5 1 0.5 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 -40C 25C 85C Figure 83. VCC ( RC 2 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 2 MHz 1.6 25C 1.4 1.2 1 ICC (mA) 0.8 0.6 0.4 0.2 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 85C -40C 129 1477E-AVR-12/03 Figure 84. VCC ( RC 1 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 0.8 0.7 0.6 0.5 ICC (mA) 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 25C 85C -40C Figure 85. VCC (PLL ) IDLE SUPPLY CURRENT vs. VCC PLL OSCILLATOR 10 25C 85C 8 -40C ICC (mA) 6 4 2 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 130 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 86. VCC (32 kHz ) IDLE SUPPLY CURRENT vs. VCC 32kHz EXTERNAL OSCILLATOR 30 25C 25 20 ICC (uA) 15 10 5 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 Figure 87. VCC ( ) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 1.8 85C 1.6 1.4 1.2 ICC (uA) 1 0.8 0.6 0.4 0.2 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 -40C 25C 131 1477E-AVR-12/03 Figure 88. VCC ( ) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 20 18 16 14 12 ICC (uA) 10 8 6 4 2 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 85C 25C -40C Standby Figure 89. Standby VCC (455 kHz ) STANDBY SUPPLY CURRENT vs. V CC 455 kHz RESONATOR, WATCHDOG TIMER DISABLED 70 60 50 40 30 20 10 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 132 ATtiny26(L) 1477E-AVR-12/03 ICC (uA) ATtiny26(L) Figure 90. Standby VCC (1 MHz ) STANDBY SUPPLY CURRENT vs. V CC 1 MHz RESONATOR, WATCHDOG TIMER DISABLED 60 50 40 ICC (uA) 30 20 10 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 Figure 91. Standby VCC (2 MHz ) STANDBY SUPPLY CURRENT vs. V CC 2 MHz RESONATOR, WATCHDOG TIMER DISABLED 80 70 60 50 ICC (uA) 40 30 20 10 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 133 1477E-AVR-12/03 Figure 92. Standby VCC (2 MHz XTAL ) STANDBY SUPPLY CURRENT vs. V CC 2 MHz XTAL, WATCHDOG TIMER DISABLED 90 80 70 60 ICC (uA) 50 40 30 20 10 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 Figure 93. Standby VCC (4 MHz ) STANDBY SUPPLY CURRENT vs. V CC 4 MHz RESONATOR, WATCHDOG TIMER DISABLED 120 100 80 ICC (uA) 60 40 20 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 134 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 94. Standby VCC (4 MHz XTAL ) STANDBY SUPPLY CURRENT vs. V CC 4 MHz XTAL, WATCHDOG TIMER DISABLED 120 100 80 ICC (uA) 60 40 20 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 Figure 95. Standby VCC (6 MHz ) STANDBY SUPPLY CURRENT vs. V CC 6 MHz RESONATOR, WATCHDOG TIMER DISABLED 160 140 120 100 ICC (uA) 80 60 40 20 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 135 1477E-AVR-12/03 Figure 96. Standby VCC (6 MHzXTAL ) STANDBY SUPPLY CURRENT vs. V CC 6 MHz XTAL, WATCHDOG TIMER DISABLED 180 160 140 120 ICC (uA) 100 80 60 40 20 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 Figure 97. I/O (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 160 85C 140 120 25C -40C 100 IOP (uA) 80 60 40 20 0 0 1 2 3 VOP (V) 4 5 6 136 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 98. I/O (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 85C 70 60 50 IOP (uA) 40 30 20 10 0 0 80 25C -40C 0.5 1 1.5 VOP (V) 2 2.5 3 Figure 99. (Reset) Reset (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 5V 120 -40C 100 25C 85C 80 IRESET (uA) 60 40 20 0 VRESET (V) 137 1477E-AVR-12/03 Figure 100. (Reset) Reset (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 60 -40C 50 25C 85C 40 IRESET (uA) 30 20 10 0 0 0.5 1 1.5 VRESET (V) 2 2.5 3 Figure 101. I/O (VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 90 80 70 -40C 25C 60 IOH (mA) 50 40 30 20 10 0 0 1 2 85C 3 VOH (V) 4 138 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 102. I/O (VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 30 -40C 25 20 IOH (mA) 25C 85C 15 10 5 0 0 0.5 1 1.5 VOH (V) 2 2.5 3 Figure 103. I/O (VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 90 80 70 60 IOL (mA) 50 40 30 20 10 0 0 0.5 1 VOL (V) 1.5 2 2.5 -40C 25C 85C 139 1477E-AVR-12/03 Figure 104. I/O (VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 35 -40C 30 25 IOL (mA) 20 15 10 5 0 0 0.5 1 VOL (V) 1.5 2 2.5 25C 85C Figure 105. Reset I/O - (VCC = 5V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 1.4 -40C 1.2 1 Current (mA) 0.8 0.6 0.4 0.2 0 0 1 2 3 VOH (V) 25C 85C 140 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 106. Reset I/O - (VCC = 2.7V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 2.5 -40C 2 25C Current (mA) 1.5 85C 1 0.5 0 0 0.5 1 1.5 VOH (V) 2 2.5 3 Figure 107. Reset I/O - (VCC = 5V) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 14 -40C 12 10 Current (mA) 8 6 4 2 0 0 0.5 1 VOL (V) 1.5 2 2.5 25C 85C 141 1477E-AVR-12/03 Figure 108. Reset I/O - (VCC = 2.7V) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 4.5 4 3.5 3 Current (mA) 2.5 2 1.5 1 0.5 0 0 0.5 1 VOL (V) 1.5 2 2.5 -40C 25C 85C Figure 109. I/O VCC (VIH, I/O "1") I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2.5 2 -40C 85C 25C Threshold (V) 1.5 1 0.5 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 142 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 110. I/O VCC (VIL, I/O "0") I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 2 1.5 Threshold (V) -40C 25C 85C 1 0.5 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 Figure 111. I/O VCC I/O PIN INPUT HYSTERESIS vs. VCC 0.7 0.6 0.5 Threshold (V) 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 85C 25C -40C 143 1477E-AVR-12/03 Figure 112. Reset I/O VCC (VIH,Reset "1") RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET PIN READ AS '1' 2.5 2 -40C 85C 25C Threshold (V) 1.5 1 0.5 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 Figure 113. Reset I/O VCC (VIL,Reset "0") RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. VCC VIL, RESET PIN READ AS '0' 2.5 2 Threshold (V) 1.5 -40C 25C 85C 1 0.5 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 144 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 114. Reset VCC RESET PIN AS I/O - PIN HYSTERESIS vs. VCC 0.7 0.6 0.5 Threshold (V) 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 85C -40C 25C Figure 115. Reset VCC (VIH,Reset "1") RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET PIN READ AS '1' 2.5 2 Threshold (V) 1.5 1 -40C 25C 85C 0.5 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 145 1477E-AVR-12/03 Figure 116. Reset VCC (VIL,Reset "0") RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, RESET PIN READ AS '0' 2.5 2 Threshold (V) 1.5 1 85C 25C -40C 0.5 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 Figure 117. Reset VCC RESET INPUT PIN HYSTERESIS vs. VCC 0.5 0.45 0.4 0.35 Threshold (V) 0.3 0.25 0.2 0.15 0.1 0.05 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 -40C 25C 85C 146 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) BOD Figure 118. BOD (BOD 4.0V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.0V 4.3 4.2 Rising VCC Threshold (V) 4.1 4 Falling VCC 3.9 3.8 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) Figure 119. BOD (BOD 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7V 3.1 3 Threshold (V) Rising VCC 2.9 2.8 2.7 Falling VCC 2.6 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) 147 1477E-AVR-12/03 Figure 120. VCC BANDGAP vs. VCC 1.236 1.234 1.232 Bandgap Voltage (V) 1.23 1.228 1.226 1.224 1.222 1.22 1.218 1.216 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5 -40C 85C 25C Figure 121. (VCC= 5.0V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 5V 0.009 0.008 Comparator Offset Voltage (V) 0.007 0.006 0.005 0.004 0.003 0.002 0.001 0 0 1 2 3 Common Mode Voltage (V) 4 -40C 25C 85C 148 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 122. (VCC= 2.7V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 2.7V 0.009 0.008 Comparator Offset Voltage (V) 0.007 0.006 0.005 0.004 0.003 0.002 0.001 0 0 0.5 1 1.5 Common Mode Voltage (V) 2 2.5 3 -40C 25C 85C Figure 123. VCC WATCHDOG OSCILLATOR FREQUENCY vs. VCC 1.4 1.35 1.3 FRC (MHz) 1.25 1.2 1.15 1.1 1.05 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 -40C 25C 85C 149 1477E-AVR-12/03 Figure 124. 8 MHz RC CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.9 8.4 FRC (MHz) 7.9 5.0V 7.4 3.5V 6.9 2.7V 6.4 -60 -40 -20 0 20 Ta (C) 40 60 80 100 Figure 125. 8 MHz RC VCC CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC 9 8.5 -40C 25C 85C 8 FRC (MHz) 7.5 7 6.5 6 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 150 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 126. 8 MHz RC Osccal CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 17.5 15.5 13.5 FRC (MHz) 11.5 9.5 7.5 5.5 3.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Figure 127. 4 MHz RC CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 4.3 4.2 4.1 4 FRC (MHz) 3.9 3.8 3.7 3.6 3.5 3.4 -60 -40 -20 0 20 Ta (C) 40 60 80 100 5.0V 3.5V 2.7V 151 1477E-AVR-12/03 Figure 128. 4 MHz RC VCC CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. VCC 4.4 4.3 4.2 4.1 FRC (MHz) 4 3.9 3.8 3.7 3.6 3.5 3.4 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 -40C 25C 85C Figure 129. 4 MHz RC Osccal CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 9.6 8.6 7.6 6.6 5.6 4.6 3.6 2.6 1.6 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE 152 ATtiny26(L) 1477E-AVR-12/03 FRC (MHz) ATtiny26(L) Figure 130. 2 MHz RC CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 2.15 2.1 2.05 2 FRC (MHz) 1.95 1.9 1.85 5.0V 3.5V 2.7V 1.8 1.75 -60 -40 -20 0 20 Ta (C) 40 60 80 100 Figure 131. 2 MHz RC VCC CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. VCC 2.15 2.1 2.05 2 FRC (MHz) 1.95 1.9 1.85 1.8 1.75 1.7 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 -40C 25C 85C 153 1477E-AVR-12/03 Figure 132. 2 MHz RC Osccal CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 4.3 3.8 3.3 FRC (MHz) 2.8 2.3 1.8 1.3 0.8 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Figure 133. 1 MHz RC CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1.04 1.02 1 FRC (MHz) 0.98 0.96 0.94 0.92 0.9 -60 -40 -20 0 20 VCC (V) 40 60 80 100 5.0V 3.5V 2.7V 154 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 134. 1 MHz RC VCC CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. VCC 1.1 1.05 -40C 25C FRC (MHz) 1 85C 0.95 0.9 0.85 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 Figure 135. 1 MHz RC Osccal CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE FRC (MHz) 155 1477E-AVR-12/03 Figure 136. BOD VCC BROWNOUT DETECTOR CURRENT vs. VCC 0.035 0.03 0.025 ICC (mA) 0.02 0.015 0.01 0.005 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 -40C 25C 85C Figure 137. ADC VCC (AREF = AVCC) ADC CURRENT vs. VCC AREF = AVCC 250 -40C 200 25C 85C 150 ICC (uA) 100 50 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 156 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 138. AREF VCC AREF EXTERNAL REFERENCE CURRENT vs. VCC 250 200 -40C 25C 85C 150 ICC (uA) 100 50 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 Figure 139. VCC ANALOG COMPARATOR CURRENT vs. VCC 120 100 85C 25C -40C 80 ICC (uA) 60 40 20 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 157 1477E-AVR-12/03 Figure 140. VCC PROGRAMMING CURRENT vs. VCC 5 4 -40C 25C 85C ICC (mA) 3 2 1 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 Figure 141. VCC (0.1 - 1.0 MHz ) RESET SUPPLY CURRENT vs. VCC 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 3.5 3 2.5 ICC (mA) 2 1.5 1 0.5 0 0 0.1 0.2 0.3 0.4 0.5 Frequency (MHz) 0.6 0.7 0.8 0.9 1 5.5V 5.0V 4.5V 4.0V 3.3V 3.0V 2.7V 158 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) Figure 142. VCC (1 - 20 MHz ) RESET SUPPLY CURRENT vs. VCC 1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 20 18 16 14 ICC (mA) 12 10 8 6 4 2 0 0 2 4 6 8 10 Frequency (MHz) 12 14 16 18 20 5.5V 5.0V 4.5V 4.0V 3.3V 3.0V 2.7V Figure 143. VCC RESET PULSE WIDTH vs. VCC 1200 1000 85C 25C Pulsewidth (ns) 800 -40C 600 400 200 0 0 1 2 3 VCC (V) 159 1477E-AVR-12/03 $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2)B $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) ... $00 ($20) SREG SP GIMSK GIFR TIMSK TIFR MCUCR MCUSR TCCR0 TCNT0 OSCCAL TCCR1A TCCR1B TCNT1 OCR1A OCR1B OCR1C PLLCSR WDTCR EEAR EEDR EECR PORTA DDRA PINA PORTB DDRB PINB USIDR USISR USICR ACSR ADMUX ADCSR ADCH ADCL Bit 7 I SP7 - Bit 6 T SP6 INT0 INTF0 OCIE1A OCF1A Bit 5 H SP5 PCIE1 PCIF OCIE1B OCF1B Bit 4 S SP4 PCIE0 - Bit 3 V SP3 - Bit 2 N SP2 TOIE1 TOV1 Bit 1 Z SP1 TOIE0 TOV0 Bit 0 C SP0 - 17 18 33 34 34 36 - PUD - SE - SM1 - SM0 WDRF PSR0 T/C0 (8 ) BORF CS02 ISC01 EXTRF CS01 ISC00 PORF CS00 38 32 44 45 30 COM1A1 CTC1 COM1A0 PSR1 COM1B1 COM1B0 FOC1A CS13 T/C1 (8 ) T/C1 A (8 ) T/C1 B (8 ) T/C1 C (8 ) PCKE PLLE PLOCK FOC1B CS12 PWM1A CS11 PWM1B CS10 47 49 50 50 51 51 - - - WDCE WDE WDP2 WDP1 WDP0 56 PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 EEAR6 PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 EEAR5 PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 EEAR4 PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 EEAR3 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 EEAR2 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 EEAR1 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 EEAR0 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 58 58 58 EEPROM (8 ) (8 ) USISIF USISIE USIOIF USIOIE USIPF USIWM1 USIDC USIWM0 USICNT3 USICS1 USICNT2 USICS0 USICNT1 USICLK USICNT0 USITC 61 62 63 ACD REFS1 ADEN ACBG REFS0 ADSC ACO ADLAR ADFR ACI MUX4 ADIF ACIE MUX3 ADIE ACME MUX2 ADPS2 ACIS1 MUX1 ADPS1 ACIS0 MUX0 ADPS0 72 82 84 85 85 ADC ADC 160 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID MOV LDI LD LD LD Rd, Rr Rd, Rr Rd, Rr Rd, K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k Rd, Rr Rd, K Rd, X Rd, X+ Rd, -X k Rd, Rr Rd, Rr Rdl, K Rd, Rr Rd, K Rd, Rr Rd, K Rdl, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd, K Rd, K Rd Rd Rd Rd Rd k 1 2 (Z) (Z) Rd Rd + Rr Rd Rd + Rr + C Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z,N,V,C,H Z,N,V,C,H Z,N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None # 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1 1 2 2 2 Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b) = 0) PC PC + 2 or 3 if (Rr(b) = 1) PC PC + 2 or 3 if (P(b) = 0) PC PC + 2 or 3 if (P(b) = 1) PC PC + 2 or 3 if (SREG(s) = 1) then PC PC + k + 1 if (SREG(s) = 0) then PC PC + k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V = 0) then PC PC + k + 1 if (N V = 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if (I = 1) then PC PC + k + 1 if (I = 0) then PC PC + k + 1 "0" "1" I/O "0" I/O "1" "1" "0" "1" "0" "1" "0" T "1" T "0" "1" "0" Rd Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) 161 1477E-AVR-12/03 (Continued) LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR Rd, Z Rd, P P, Rr Rr Rd P, b P, b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Rd, Y Rd, Y+ Rd, -Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr -X, Rr Y, Rr Y+, Rr -Y, Rr Y+q, Rr Z, Rr Z+, Rr -Z, Rr Z+q, Rr k, Rr Rd (Y) SRAM SRAM I/O I/O I/O I/O T T 2 2 SREG T SREG T SREG SREG Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z + 1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd P P Rr STACK Rr Rd STACK None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0) C, Rd(n+1) Rd(n), C Rd(7) Rd(7) C, Rd(n) Rd(n+1), C Rd(0) Rd(n) Rd(n+1), n = 0..6 Rd(3..0) Rd(7..4), Rd(7..4) Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 ( ) ( WDR/ ) 162 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) (1) (MHz) 8 2.7 - 5.5V 20P3 20S 32M1-A 20P3 20S 32M1-A 20P3 20S 32M1-A 20P3 20S 32M1-A (0C 70C) (-40C 85C) (0C 70C) (-40C 85C) ATtiny26L-8PC ATtiny26L-8SC ATtiny26L-8MC ATtiny26L-8PI ATtiny26L-8SI ATtiny26L-8MI 16 4.5 - 5.5V ATtiny26-16PC ATtiny26-16SC ATtiny26-16MC ATtiny26-16PI ATtiny26-16SI ATtiny26-16MI Note: 1. wafer Atmel 20P3 20S 32M1-A 20 0.300" PDIP 20 0.300" SOIC 32 5 x 5 x 1.0 MLF 163 1477E-AVR-12/03 20P3 D PIN 1 E1 A SEATING PLANE L B1 e E B A1 C eC eB SYMBOL A A1 D E E1 B Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB eC e COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 25.493 7.620 6.096 0.356 1.270 2.921 0.203 - 0.000 NOM - - - - - - - - - - - MAX 5.334 - 25.984 8.255 7.112 0.559 1.551 3.810 0.356 10.922 1.524 Note 2 Note 2 NOTE 2.540 TYP 1/12/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 20P3 REV. C R 164 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) 20S C 1 EH N Top View A1 End View COMMON DIMENSIONS (Unit of Measure = inches) e b A D SYMBOL MIN L NOM MAX NOTE A A1 b C D 0.0926 0.0040 0.0130 0.0091 0.4961 0.2914 0.3940 0.0160 0.050 BSC 0.1043 0.0118 0.0200 0.0125 0.5118 0.2992 0.4190 0.050 3 1 2 4 Side View E H L e Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information. 2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. "L" is the length of the terminal for soldering to a substrate. 5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm 1/9/02 (0.024") per side. R 2325 Orchard Parkway San Jose, CA 95131 TITLE 20S2, 20-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) DRAWING NO. 20S2 REV. A 165 1477E-AVR-12/03 32M1-A D D1 1 2 3 0 Pin 1 ID E1 E SIDE VIEW TOP VIEW A2 A3 A1 A 0.08 C P D2 Pin 1 ID COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.80 - - NOM 0.90 0.02 0.65 0.20 REF 0.18 0.23 5.00 BSC 4.75 BSC 2.95 3.10 5.00 BSC 4.75BSC 2.95 3.10 0.50 BSC 0.30 - - 0.40 - - 0.50 0.60 12o 3.25 3.25 0.30 MAX 1.00 0.05 1.00 NOTE 1 2 3 P A A1 E2 A2 A3 b D D1 b e L D2 E BOTTOM VIEW E1 E2 e L Notes: 1. JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. P 0 01/15/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm Micro Lead Frame Package (MLF) DRAWING NO. 32M1-A REV. C R 166 ATtiny26(L) 1477E-AVR-12/03 ATtiny26(L) ATtiny26 Rev. 1477D-05/03 Rev. 1477E-10/03 1. " " 2. "Features" on page 1 3. P2" " SSOP 4. P19Table 3 VRST tRST 5. P30" RC " 6. P122" " VOL, IIL, IIH, ICC VACIO 7. P125"ADC " P122 VINT, INL P122" " 8. P142"" Figure106 P151"BOD" Figure120, Figure121 Figure122 Figure117 Figure118 9. P161" " LPM Rd, Z+ ATtiny26 Rev. 1477C-09/02 Rev. 1477D-05/03 1. P168" " 2. P125"ADC " ADHSM 3. P60" EEPROM " 4. P27" " 5. P49"Bit 0 - PLOCK: PLL " PLL 6. P73 7. P84 {DDxn, PORTxn} 8. P91" " 9. P100Table 49 RSTDISBL 10. P108Figure61 DATA 11. P115Table 59 WD_FUSE 12. P125"ADC " P 122Table 64, " ADC A T = -40C 85C," 13. P127"ATtiny26 " 14. P161" " LPM Rd, Z LPM Rd, Z+ 167 1477E-AVR-12/03 Rev. 1477B-04/02 Rev. 1477C-09/02 Rev. 1477A-03/02 Rev. 1477B-04/02 1. Flash 10,000 1. P24" " 2. P75" " 3. P163" (1)" MLF 168 ATtiny26(L) 1477E-AVR-12/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Printed on recycled paper. 1477E-AVR-12/03 0M |
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