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ADS7826 ADS7827 ADS7829
SLAS388 - JUNE 2003
10/8/12-BIT HIGH SPEED 2.7 V microPOWERTM SAMPLING ANALOG-TO-DIGITAL CONVERTER
FEATURES
* High Throughput at Low Supply Voltage (2.7 V VCC) - ADS7829: 12-bit 125 KSPS - ADS7826: 10-bit 200 KSPS - ADS7827: 8-bit 250 KSPS Very Wide Operating Supply VoltageL: 2.7 V to 5.25 V (as Low as 2.0 V With Reduced Performance) Rail-to-Rail, Pseudo Differential Input Wide Reference Voltage: 50 mV to VCC Micropower Auto Power-Down: - Less Than 60 W at 75 kHz, 2.7 V VCC Low Power Down Current: 3 A Max Ultra Small Chip Scale Package: 8-pin 3 x 3 PDSO (SON, Same Size as QFN) SPITM Compatible Serial Interface
DESCRIPTION
The ADS7826/27/29 is a family of 10/8/12-bit sampling analog-to-digital converters (A/D) with assured specifications at 2.7-V supply voltage. It requires very little power even when operating at the full sample rate. At lower conversion rates, the high speed of the device enables it to spend most of its time in the power down mode-- the power dissipation is less than 60 W at 7.5 kHz. The ADS7826/27/29 also features operation from 2.0 V to 5 V, a synchronous serial interface, and a differential input. The reference voltage can be set to any level within the range of 50 mV to VCC. Ultra-low power and small package size make the ADS7826/27/29 family ideal for battery operated systems. It is also a perfect fit for remote data acquisition modules, simultaneous multichannel systems, and isolated data acquisition. The ADS7826/27/29 family is available in a 3 x 3 8-pin PDSO (SON, same size as QFN) package.
*
* * * * * *
APPLICATIONS
* * * * Battery Operated Systems Remote Data Acquisition Isolated Data Acquisition Simultaneous Sampling, Multichannel Systems
SAR Control
VREF
D OUT +In CDAC -In S/H Amp Comparator Serial Interface DCLOCK CS/SHDN
microPOWER is a trademark of Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2003, Texas Instruments Incorporated
ADS7826 ADS7827 ADS7829
SLAS388 - JUNE 2003
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION
MAXIMUM LINERARITY ERROR (LSB) PRODUCT ADS7829I ADS7829IB ADS7826I ADS7827I ADS7829I ADS7829IB ADS7826I ADS7827I INTEGRAL 2 1.25 1 1 2 1.25 1 1 DIFFERENTIAL 2 -1/1.25 1 1 2 -1/1.25 1 1 PACKAGE (1) SON-8 SON-8 SON-8 SON-8 SON-8 SON-8 SON-8 SON-8
SPECIFICATION TEMPERATURE RANGE -40C to 85C -40C to 85 -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C
PACKAGE MARKING (2) F29 F29 F26 F27 F29 F29 F26 F27
ORDERING NUMBER ADS7829IDRBR ADS7829IBDRBR ADS7826IDRBR ADS7827IDRBR ADS7829IDRBT ADS7829IBDRBT ADS7826IDRBT ADS7827IDRBT
TRANSPORT MEDIA Tape and reel Tape and reel Tape and reel Tape and reel Tape and reel Tape and reel Tape and reel Tape and reel
(1) (2)
For detail drawing and dimension table, see end of this data sheet or package drawing file on web. Performance Grade information is marked on the reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VCC Analog input Logic input Case temperature Junction temperature Storage temperature External reference voltage (1) 6V -0.3 V to (VCC + 0.3 V) -0.3 V to 6 V 100C 150C 125C 5.5 V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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ADS7826 ADS7827 ADS7829
SLAS388 - JUNE 2003
SPECIFICATIONS
At -40C to 85C, VCC = 2.7 V, Vref = 2.5 V, unless otherwise specified.
PARAMETER ANALOG INPUT Full-scale input span Absolute input range Capacitance Leakage current
TEST CONDITIONS
ADS7829IB MIN 0 -0.2 -0.2 25 1 12 12 -1.25 -1 -3 -2 0.4 0.4 0.3 0.3 33 82 12 1.5 16 x fsample 1.25 1.25 3 2 11 -2 -2 -3 -2 TYP MAX Vref VCC +0.2 1.0 MIN 0 -0.2 -0.2
ADS7829 TYP MAX Vref VCC +0.2 1.0 25 1 12 10 0.8 0.8 0.6 0.6 33 82 12 1.5 16 x fsample 125 75 125 75 2 2 3 2 -1 -1 -2 -1 MIN 0 -0.2 -0.2
ADS7826I TYP MAX Vref VCC +0.2 1.0 25 1 10 8 0.3 0.3 0.4 0.3 33 94 10 1.5 14 x fsample 200 85 1 1 2 1 -1 -1 -1 -1 MIN 0 -0.2 -0.2
ADS7827I TYP MAX Vref VCC +0.2 1.0 25 1 8 0.2 0.2 0.4 0.2 33 98 8 1.5 12 x fsample 250 100 1 1 1 1
UNIT
+In - (-In) +In -IN
V V V pF A Bits Bits LSB (1) LSB LSB LSB Vrms dB DCLOCK Cycles DCLOCK Cycles kHz kHz kHz
SYSTEM PERFORMANCE Resolution No missing codes Integral linearity error Differential linearity error Offset error Gain error Noise Power supply rejection SAMPLING DYNAMICS Conversion time Acquisition time fDCLOCK Throughput (sample rate) fsample 2.7 V VCC 5.25 V (2) 2.0 V VCC < 2.7 V (3) (2) -82 72 85
DYNAMIC CHARACTERISTICS Total harmonic distortion SINAD Spurious free dynamic range (SFDR) Voltage range Resistance VIN = 2.5 Vpp at 1 kHz VIN = 2.5 Vpp at 1 kHz -80 70 82 -78 62 81 -72 50 68 dB dB dB
REFERENCE INPUT 2.7 V VCC3.6 V CS = GND, fSAMPLE = 0 Hz CS = VCC Current drain Full speed at Vref/2 fSAMPLE = 7.5 kHz CS = VCC DIGITAL INPUT/OUTPUT Logic family Logic levels VIH VIL IIH = +5 A IIL = +5 A 2.0 -0.3 5.5 0.8 2.0 -0.3 5.5 0.8 2.0 -0.3 5.5 0.8 2.0 -0.3 5.5 0.8 V V CMOS CMOS CMOS CMOS 0.05 5 5 12 0.8 0.001 3 60 VCC-0.2 0.05 5 5 12 0.8 0.001 3 60 VCC-0.2 0.05 5 5 20 0.8 0.001 3 100 VCC-0.2 0.05 5 5 24 0.8 0.001 3 120 VCC-0.2 V G G A A A
(1) (2) (3)
LSB means Least Significant Bit and is equal to Vref / 2 N where N is the resolution of ADC. For example, with Vref equal to 2.5 V, one LSB is 0.61 mV for a 12 bit ADC (ADS7829). See the Typical Performance Curves for VCC = 5 V and Vref = 5 V. The maximum clock rate of the ADS7826/27/29 are less than 1.2 MHz at 2 V VCC <2.7 V. The recommended regerence voltage is between 1.25 V to 1.024 V. 3
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ADS7826 ADS7827 ADS7829
SLAS388 - JUNE 2003
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SPECIFICATIONS (continued)
At -40C to 85C, VCC = 2.7 V, Vref = 2.5 V, unless otherwise specified.
PARAMETER VOH VOL Data format POWER SUPPLY REQUIREMENTS VCC Operating range See (3) and (2) See (2) Quiescent current Full speed (4) fSAMPLE = 7.5 kHz (5), fSAMPLE = 7.5 kHz (6) Power down Specified performance CS = VCC -40 2.7 2.0 3.6 220 20 180 3 85 -40 3.6 2.7 5.25 350 2.7 2.0 3.6 220 20 180 3 85 -40 3.6 2.7 5.25 350 2.7 2.0 3.6 250 20 180 3 85 -40 3.6 2.7 5.25 350 2.7 2.0 3.6 260 20 180 3 85 3.6 2.7 5.25 350 V V V A A A A C TEST CONDITIONS IOH = -250 A IOL = 250 A Straight binary ADS7829IB MIN 2.2 0.4 Straight binary TYP MAX MIN 2.1 0.4 Straight binary ADS7829 TYP MAX MIN 2.1 0.4 Straight binary ADS7826I TYP MAX MIN 2.1 0.4 ADS7827I TYP MAX UNIT V V
TEMPERATURE RANGE
(4) (5) (6)
Full speed: 125 ksps for ADS7829, 200 ksps for ADS7826, and 250 ksps for ADS7827. fDCLOCK = 1.2 MHz, CS = VCC for 145 clock cycles out of every 160 for the ADS7829I and ADS7829IB. See the Power Dissipation section for more information regarding lower sample rates.
At -40C to 85C, VCC = 5 V, Vref = 5 V, unless otherwise specified.
PARAMETER SYSTEM PERFORMANCE Resolution No missing codes Integral linearity error Differential linearity error ANALOG INPUT Offset error Gain error REFERENCE INPUT Voltage range
TEST CONDITIONS
ADS7829IB MIN TYP 12 12 0.6 0.5 2.6 1.2 0.05 VCC 0.05 11 MAX MIN
ADS7829 TYP 12 MAX
ADS7826I MIN TYP 10 10 MAX
ADS7827I MIN TYP 8 8 0.1 0.1 0.7 0.1 VCC 0.05 VCC MAX
UNIT
Bits Bits 1 LSB (7) 1 LSB LSB LSB V
0.8 0.8 2.6 1.2 VCC 0.05
0.15 0.15 1.2 0.2
(7)
LSB means Least Significant Bit . With Vref equal to 5 V, one LSB is 1.22 mV for a 12 bit ADC.
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DEVICE INFORMATION
PIN DESCRIPTION PDSO (SON-8) PACKAGE (TOP VIEW)
REF +IN -IN GND
1 2 3 4
8 7 6 5
+VDD DCLOCK DOUT CS/ SHDN
Terminal Functions
PIN 1 2 3 4 5 6 NAME Vref +In -In GND CS/SHDN DOUT DESCRIPTION Reference input Noninverting input Inverting input. Connect to ground or to remote ground sense point. Ground Chip select when LOW, shutdown mode when HIGH The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After one null bit, the data is valid for the next 12 edges. Data Clock synchronizes the serial data transfer and determines conversion speed. Power supply
7 8
DCLOCK +VCC
5
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ADS7826 ADS7827 ADS7829
SLAS388 - JUNE 2003
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TYPICAL CHARACTERISTICS
At TA = 25C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
ADS7829 INTEGRAL LINEARITY
1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 Integral Linearity - LSB
0
512
1024
1536
2048
2560
3072
3584
Decimal Code Figure 1
ADS7826 INTEGRAL LINEARITY
1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1
Integral Linearity - LSB
0
128
256
384
512 Decimal Code Figure 2
640
768
896
ADS7827 INTEGRAL LINEARITY
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96 128 Decimal Code Figure 3 160 192 224
6
Integral Linearity - LSB
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TYPICAL CHARACTERISTICS (continued)
At TA = 25C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
ADS7829 DIFFERENTIAL LINEARITY
Differential Linearity - LSB 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1
0
512
1024
1536
2048 2560 Decimal Code Figure 4
3072
3584
ADS7826 DIFFERENTIAL LINEARITY
1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 Differential Linearity - LSB
0
128
256
384
512 Decimal Code Figure 5
640
768
896
ADS7827 DIFFERENTIAL LINEARITY
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 Differential Linearity - LSB
0
32
64
96
128 Decimal Code Figure 6
160
192
224
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ADS7826 ADS7827 ADS7829
SLAS388 - JUNE 2003
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TYPICAL CHARACTERISTICS (continued)
At TA = 25C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
CHANGE IN MINIMUM INTEGRAL LINEARITY vs FREE-AIR TEMPERATURE
0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -40 -20 0 20 40 60 80 ADS7829 ADS7827 ADS7826 Delta From 25 C - LSB Delta From 25 C - LSB
CHANGE IN MAXIMUM INTEGRAL LINEARITY vs FREE-AIR TEMPERATURE
0.2 0.15 0.1 ADS7826 0.05 0 -0.05 -0.1 -0.15 -0.2 -40 -20 0 20 40 60 80 ADS7827 ADS7829
TA - Free-Air Temperature - C
TA - Free-Air Temperature - C
Figure 7. CHANGE IN MINIMUM DIFFERENTIAL LINEARITY vs FREE-AIR TEMPERATURE
0.4 0.3 Delta From 25 C - LSB Delta From 25 C - LSB 0.2 0.1 ADS7827 0 -0.1 -0.2 -0.3 -0.4 -40 -20 20 40 60 0 TA - Free-Air Temperature - C 80 ADS7829 ADS7826
Figure 8. CHANGE IN MAXIMUM DIFFERENTIAL LINEARITY vs FREE-AIR TEMPERATURE
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -40 -20 0 20 40 60 80 TA - Free-Air Temperature - C ADS7829 ADS7826 ADS7827
Figure 9. CHANGE IN OFFSET ERROR vs FREE-AIR TEMPERATURE
0.5 0.4 Delta From 25 C - LSB 0.3 ADS7829 0.2 0.4
Figure 10. CHANGE IN GAIN ERROR vs FREE-AIR TEMPERATURE
Delta From 25 C - LSB
0.3 ADS7826 0.2 ADS7829
0.1
0.1 ADS7827 0 -0.1 -40 -20 0 20 40 60 80 TA - Free-Air Temperature - C ADS7826
0 ADS7827 -0.1 -0.2 -40 -20 0 20 40 60 TA - Free-Air Temperature - C 80
Figure 11.
Figure 12.
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ADS7826 ADS7827 ADS7829
SLAS388 - JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA = 25C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
CHANGE IN QUIESCENT CURRENT vs FREE-AIR TEMPERATURE
50 40 I O - Quiescent Current - mA Delta From 2.7 V - LSB 30 20 10 0 -10 -20 -30 -40 -50 -40 -0.2 -20 0 20 40 60 80 2.7 TA - Free-Air Temperature - C
CHANGE IN MAXIMUM INTEGRAL LINEARITY vs SUPPLY VOLTAGE
0.5 Vref = 2.5 V 0.4 0.3 0.2 0.1 0 -0.1 ADS7826 3.2 3.7 4.2 4.7 VCC - Supply Voltage - V 5.2 ADS7829
ADS7827
Figure 13. CHANGE IN MINIMUM INTEGRAL LINEARITY vs SUPPLY VOLTAGE
0.2 Vref = 2.5 V 0.1 Delta From 2.7 V - LSB Delta From 2.7 V - LSB 0 -0.1 -0.2 -0.3 -0.4 -0.5 2.7 ADS7827 ADS7826 ADS7829 0.2
Figure 14. CHANGE IN MAXIMUM DIFFERENTIAL LINEARITY vs SUPPLY VOLTAGE
0.3 Vref = 2.5 V ADS7829 0.1 ADS7827 0 ADS7826 -0.1
-0.2 -0.3 2.7
3.2 3.7 4.2 4.7 VCC - Supply Voltage - V
5.2
3.2
3.7
4.2
4.7
5.2
VCC - Supply Voltage - V
Figure 15. CHANGE IN MINIMUM INTEGRAL LINEARITY vs SUPPLY VOLTAGE
0.1 0.08 Delta From 2.7 V - LSB 0.06 0.04 0.02 0 ADS7826 -0.02 -0.04 -0.06 -0.08 -0.1 2.7 0 3.2 3.7 4.2 4.7 VCC - Supply Voltage - V 5.2 2.7 3.2 Vref = 2.5 V ADS7829 5 ADS7827 Delta From 2.7 V - LSB 4 6 Vref = 2.5 V
Figure 16. CHANGE IN OFFSET ERROR vs SUPPLY VOLTAGE
ADS7829 3 2
ADS7826
1 ADS7827
3.7
4.2
4.7
5.2
VCC - Supply Voltage - V
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
At TA = 25C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
CHANGE IN GAIN vs SUPPLY VOLTAGE
1.2 Vref = 2.5 V Delta From 2.7 V - LSB ADS7829 0.8 0.6 0.4 ADS7826 0.2 ADS7827 0 2.7 3.2 3.7 4.2 4.7 5.2 VCC - Supply Voltage - V Delta From 2.7 V - A 1
CHANGE IN QUIESCENT CURRENT vs SUPPLY VOLTAGE
200 180 160 140 120 100 80 60 40 20 0
2.7 3.2 3.7 4.2 4.7 5.2 ADS7829 Vref = 2.5 V ADS7827 ADS7826
VCC - Supply Voltage - V
Figure 19. REFERENCE CURRENT vs SAMPLE RATE
30 25 Reference Current - A Change in Offset - LSB 1.2 1 0.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 0 0 25 50 75 100 125 150 175 200 225 250 Sample Rate - kHz - 0.8 1 2 VCC = 5 V
Figure 20. ADS7829 CHANGE IN OFFSET ERROR vs REFERENCE VOLTAGE
20
15 10
5
3
4
5
Reference Voltage - V
Figure 21. ADS7829 CHANGE IN GAIN ERROR vs REFERENCE VOLTAGE
2.5 VCC = 5 V 2 Change in Gain - dB 1.5 1 0.5 0 - 0.5 -1 - 1.5 0 2 3 4 5 Reference Voltage - V Peak-To-Peak Noise - LSB 10 9 8 7 6 5 4 3 2 1 0 0.1 VCC = 5 V
Figure 22. ADS7829 PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE
1 Reference Voltage - V
10
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
At TA = 25C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
ADS7829 CHANGE IN INTEGRAL and DIFFERENTIAL LINEARITY vs REFERENCE VOLTAGE
0.20 Data From 2.5 V Reference - LSB VCC = 5 V 0.15 0.10 Change in Integral Linearity - LSB Effective Number of Bits - rms 12 VCC = 5 V 11.75 11.5 11.25 11 10.75 10.5 10.25 10 1 2 3 4 5 0.1 1 Reference Voltage - V 10 Reference Voltage - V
ADS7829 EFFECTIVE NUMBER OF BITS vs REFERENCE VOLTAGE
0.05
0 - 0.05 - 0.10 Change in Differential Linearity - LSB
Figure 25. ADS7829 SPURIOUS FREE DYNAMIC RANGE and SIGNAL-TO-NOISE RATIO vs SAMPLE FREQUENCY
100 90 Spurious Free Dynamic Range Signal-To-Noise Ratio - dB 80 70 60 50 40 30 20 10 0 1 10 100 1000 f - Frequency - kHz Signal-To-Noise Spurious Free Dynamic Range Signal-To-Noise+Distortion - dB
Figure 26. ADS7829 SIGNAL-TO-NOISE + DISTORTION vs FREQUENCY
100 90 80 70 60 50 40 30 20 10 0 1 10 100 1000 f - frequency - kHz
Figure 27. ADS7829 TOTAL HARMONIC DISTORTION vs FREQUENCY
0 THD - Total Harmonic Distortion - dB - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 1 10 100 1000 f - Frequency - kHz Spurious Free Dynamic Range Signal-T o-Noise Ratio - dB
Figure 28. ADS7826 SPURIOUS FREE DYNAMIC RANGE and SIGNAL-TO-NOISE RATIO vs FREQUENCY
100 90 80 70 60 50 40 30 20 10 0 1 10 100 f - Frequency - kHz 1000 Signal-T o-Noise Spurious Free Dynamic Range
Figure 29.
Figure 30. 11
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TYPICAL CHARACTERISTICS (continued)
At TA = 25C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
ADS7826 SIGNAL-TO-NOISE + DISTORTION vs FREQUENCY
100 THD - Total Harmonic Distortion - dB 90 Signal-To-Noise+Distortion - dB 80 70 60 50 40 30 20 10 0 1 10 100 1000 f - frequency - kHz
ADS7826 TOTAL HARMONIC DISTORTION vs FREQUENCY
0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 1 10 100 1000 f - Frequency - kHz
Figure 31. ADS7827 SPURIOUS FREE DYNAMIC RANGE and SIGNAL-TO-NOISE RATIO vs FREQUENCY
100 Signal-To-Noise+Distortion - dB
Figure 32. ADS7827 SIGNAL-TO-NOISE + DISTORTION vs FREQUENCY
100
Spurious Free Dynamic Range Signal-T o-Noise Ratio - dB
80
Spurious Free Dynamic Range
80
60
60
40 Signal-T o-Noise 20
40
20
0 1 10 100 f - Frequency - kHz 1000
0 1 10 100 1000 f - frequency - kHz
Figure 33. ADS7827 TOTAL HARMONIC DISTORTION vs FREQUENCY
0 THD - Total Harmonic Distortion - dB - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 1 10 100 1000 f - Frequency - kHz
Figure 34.
Figure 35.
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THEORY OF OPERATION
The ADS7826/27/29 is a family of micropower classic successive approximation register (SAR) analog-to-digital (A/D) converters. The architecture is based on capacitive redistribution which inherently includes a sample/hold function. The converter is fabricated on a 0.6 m CMOS process. The architecture and process allow the ADS7826/27/29 family to acquire and convert an analog signal at up to 200K/250K/125K conversions per second respectively while consuming very little power. The ADS7826/27/29 family requires an external reference, an external clock, and a single power source (VCC). The external reference can be any voltage between 50 mV and VCC. The value of the reference voltage directly sets the range of the analog input. The reference input current depends on the conversion rate of the ADS7826/27/29 family. The minimum external clock input to DCLOCK can be as low as 10 kHz. The maximum external clock frequency is 2 MHz for ADS7829, 2.8 MHz for ADS7826 and 3 MHz for ADS7827 respectively. The duty cycle of the clock is essentially unimportant as long as the minimum high and low times are at least 400 ns (VCC = 2.7 V or greater). The minimum DCLOCK frequency is set by the leakage on the capacitors internal to the ADS7826/27/29 family. The analog input is provided to two input pins: +In and -In. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The digital result of the conversion is clocked out by the DCLOCK input and is provided serially, most significant bit first, on the DOUT pin. The digital data that is provided on the DOUT pin is for the conversion currently in progress--there is no pipeline delay. The input current on the analog inputs depends on a number of factors: sample rate, input voltage, source impedance, and power down mode. Essentially, the current into the ADS7826/27/29 family charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25 pF) to a 10/8/12-bit settling level within 1.5 DCLOCK cycles. When the converter goes into the hold mode or while it is in the power down mode, the input impedance is greater than 1 G. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the -In input should not drop below GND 200 mV or exceed GND + 1 V. The +In input should always remain within the range of GND - 200 mV to VCC + 200 mV. Outside of these ranges, the converter's linearity may not meet specifications.
REFERENCE INPUT
The external reference sets the analog input range. The ADS7826/27/29 family operates with a reference in the range of 50 mV to VCC. There are several important implications of this. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 2N (where N is 12 for ADS7829, 10 for ADS7826, and 8 for ADS7827). This means that any offset or gain error inherent in the A/D converter appears to increase, in terms of LSB size, as the reference voltage is reduced. The noise inherent in the converter also appears to increase with lower LSB size. With a 2.5 V reference, the internal noise of the converter typically contributes only 0.32 LSB peak-to-peak of potential error to the output code. When the external reference is 50 mV, the potential error contribution from the internal noise is 50 times larger --16 LSBs. The errors due to the internal noise are gaussian in nature and can be reduced by averaging consecutive conversion results. For more information regarding noise, consult the typical performance curves Effective Number of Bits vs Reference Voltage and Peak-to-Peak Noise vs Reference Voltage (only curves for ADS7829 are shown). Note that the effective number of bits (ENOB) figure is calculated based on the converter's signal-to-(noise + distortion) ratio with a 1 kHz, 0 dB input signal. SINAD is related to ENOB as follows:
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ANALOG INPUT
The +In and -In input pins allow for a differential input signal. Unlike some converters of this type, the -In input is not re-sampled later in the conversion cycle. When the converter goes into the hold mode, the voltage difference between +In and -In is captured on the internal capacitor array. The range of the -In input is limited to -0.2 V to 1 V. Because of this, the differential input can be used to reject only small signals that are common to both inputs. Thus, the -In input is best used to sense a remote signal ground that may move slightly with respect to the local ground potential.
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SINAD = 6.02 x ENOB + 1.76 With lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, the converter is more sensitive to external sources of error such as nearby digital signals and electromagnetic interference.
Serial Interface
The ADS7826/27/29 family communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface. Timings for ADS7829 are shown in Figure 36 and Table 1. The DCLOCK signal synchronizes the data transfer with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit. The timings for ADS7826 and ADS7827 serial interface are shown in Figure 37 and Table 1. The DCLOCK signal synchronizes the data transfer with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, athe system can use the fallng edge of DCLOCK to capture each bit.
DIGITAL INTERFACE
Signal Levels The digital inputs of the ADS7826/27/29 family can accommodate logic levels up to 6 V regardless of the value of VCC. Thus, the ADS7826/27/29 family can be powered at 3 V and still accept inputs from logic powered at 5 V. The CMOS digital output (DOUT) swings 0 V to VCC. If VCC is 3 V and this output is connected to a 5-V CMOS logic input, then that IC may require more supply current than normal and may have a slightly longer propagation delay.
tCYC CS/SHDN tSU(CS) DCLOCK tCSD Hi-Z DOUT tSMPL
Null Bit B11 B10 B9 B8 B7 B6 B5 B4 (MSB)
Power Down

B3 B2 B1
B01
tCONV
After completing the data transfer, if further clocks are applied with CS LOW, the A/D outputs LSB-First data then followed with zeroes indefinitely.
Figure 36. ADS7829 Timing
tCYC CS/SHDN tSU(CS) DCLOCK tCSD ADS7826 DOUT Hi-Z
Null Bit B9 B8 (MSB) Null Bit B7 B6 (MSB) B4 B4 Null Bit MSB Null Bit MSB

B3 B2 B1 B01
ADS7827 DOUT tSMPL
Hi-Z
B3 B2 B1 B01
tCONV
Figure 37. ADS7826 and ADS7827 Timing
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Hi-Z
Null Bit B11 B10 B9 B8
tDATA
Power Down
Hi-Z
Hi-Z
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Table 1. Timing Specifications (VCC = 2.7 V and Above -40C to 85C
SYMBOL tSAMPLE tCONV DESCRIPTION Analog input sample time Conversion time ADS7829I or ADS7829IB ADS7826I ADS7827I tCYC Cycle time ADS7829I or ADS7829IB ADS7826 ADS7827 tCSD tSU(CS) th(DO) td(DO) tdis ten tf tr CS falling to DCLOCK LOW CS falling to DCLOCK rising DCLOCK falling to current DOUT not valid DCLOCK falling to next DOUT valid CS rising to DOUT 3-state DCLOCK falling to DOUT enabled DOUT fall time DOUT rise time 30 15 130 40 75 90 110 200 80 175 200 220 16 14 12 0 ns ns ns ns ns ns ns ns MIN 1.5 12 11 9 DCLOCK Cycles TYP MAX 2.0 UNIT DCLOCK Cycles DCLOCK Cycles
A falling CS signal initiates the conversion and data transfer. The first 1.5 to 2.0 clock periods of the conversion cycle are used to sample the input signal. After the second falling DCLOCK edge, DOUT is enabled and outputs a LOW value for one clock period. For the next N (N is 12 for ADS7829, 10 for ADS7826, and 8 for ADS7827) DCLOCK periods, DOUT outputs the conversion result, most significant bit first. After the least significant bit has been sent, DOUT goes to 3-state after the rising edge of CS. A new conversion is initiated only when CS has been taken high and returned low again.
DATA FORMAT
The output data from the ADS7826/27/29 family is in straight binary format. ADS7829 out is shown in Table 2, as an example. This table represents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise. For ADS7826 the last two LSB's are don't cares, while for ADS7827 the last four LSB's are don't cares.
Table 2. Ideal Input Voltages and Output Codes (ADS7829 Shown as an Example)
DESCRIPTION FULL SCALE RANGE LEAST SIGNIFICANT BIT (LSB) Full scale Midscale Midscale - 1 LSB Zero ANALOG VALUE Vref Vref/4096 Vref - 1 LSB Vref/2 Vref/2 - 1 LSB 0V BINARY CODE 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000 DIGITAL OUTPUT STRAIGHT BINARY HEX CODE FFF 800 7FF 000
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1.4 V
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3 kW DOUT Test Point
DOUT tr tf
VOH VOL
100 pF CLOAD Load Circuit for tdDO, tr, and tf
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
Test Point DCLOCK VIL
VCC
th(DO)
3 kW DOUT VOH VOL 100 pF tdisWaveform 1 tdisWaveform 2, ten
DOUT
CLOAD
th(DO)
Voltage Waveforms for DOUT Delay Times, tdDO
Load Circuit for tdis and ten
CS/SHDN DOUT Waveform 1 (1) tdis DOUT Waveform 2 (2)
VIH
CS/SHDN DCLOCK 1 2
90%
10%
DOUT ten
VOL
B11
Voltage Waveforms for tdis
(1) (2)
Voltage Waveforms for ten
Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control.
Figure 38. Timing Diagrams and Test Circuits for the Parameters in Table 1.
POWER DISSIPATION
The architecture of the converter, the semiconductor fabrication process, and a careful design allows the ADS7826/27/29 family to convert at the full sample rate while requiring very little power. But, for the absolute lowest power dissipation, there are several things to keep in mind. The power dissipation of the ADS7826/27/29 family scales directly with conversion rate. Therefore, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that satisfies the requirements of the system. In addition, the ADS7826/27/29 family is in power down mode under two conditions: when the conversion is complete and whenever CS is HIGH. Ideally, each conversion occurs as quickly as possible, preferably, at DCLOCK rate. This way, the converter spends the longest possible time in the power down mode. This is very important as the converter not only uses power on each DCLOCK transition (as is typical for digital CMOS components) but also uses some current for the analog circuitry, such as the comparator. The analog section dissipates power continuously, until the power-down mode is entered. The current consumption of the ADS7826/27/29 family versus sample rate. For this graph, the converter is clocked at maximum DCLOCK rate regardless of the sample rate --CS is HIGH for the remaining sample period. Figure 4 also shows current consumption versus sample rate. However, in this case, the minimum DCLOCK cylce time is used--CS is HIGH for one DCLOCK cycle.
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There is an important distinction between the power down mode that is entered after a conversion is complete and the full power-down mode which is enabled when CS is HIGH. While both shutdown the analog section, the digital section is completely shutdown only when CS is HIGH. Thus, if CS is left LOW at the end of a conversion and the converter is continually clocked, the power consumption is not as low as when CS is HIGH. Power dissipation can also be reduced by lowering the power supply voltage and the reference voltage. The ADS7826/27/29 family operates over a VCC range of 2.0 V to 5.25 V. However, at voltages below 2.7 V, the converter does not run at the maximum sample rate. See the typical performance curves for more information regarding power supply voltage and maximum sample rate.
The reference should be similarly bypassed with a 0.1-F capacitor. Again, a series resistor and large capacitor can be used to lowpass filter the reference voltage. If the reference voltage originates from an op-amp, be careful that the op-amp can drive the bypass capacitor without oscillation (the series resistor can help in this case). Keep in mind that while the ADS7826/27/29 family draws very little current from the reference on average, there are still instantaneous current demands placed on the external reference circuitry. Also, keep in mind that the ADS7826/27/29 family offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply appears directly in the digital results. While high frequency noise can be filtered out as described in the previous paragraph, voltage variation due to the line frequency (50 Hz or 60 Hz), can be difficult to remove. The GND pin on the ADS7826/27/29 family must be placed on a clean ground point. In many cases, this is the analog ground. Avoid connecting the GND pin too close to the grounding point for a microprocessor, microcontroller, or digital signal processor. If needed, run a ground trace directly from the converter to the power supply connection point. The ideal layout includes an analog ground plane for the converter and associated analog circuitry.
LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS7826/27/29 family circuitry. This is particularly true if the reference voltage is low and/or the conversion rate is high. At a 125-kHz to 250-kHz conversion rate, the ADS7826/27/29 family makes a bit decision every 800 ns to 400 ns. That is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled, for example the ADS7829, to a 12-bit level all within one clock cycle. The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such spikes might originate from switching power supplies, digital logic, and high power devices, to name a few. This particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter's DCLOCK signal--as the phase difference between the two changes with time and temperature, causing sporadic misoperation. With this in mind, power to the ADS7826/27/29 family should be clean and well bypassed. A 0.1-F ceramic bypass capacitor should be placed as close to the ADS7826/27/29 family package as possible. In addition, a 1- to 10-F capacitor and a 5- or 10- series resistor may be used to lowpass filter a noisy supply.
APPLICATION CIRCUITS
Figure 39 and Figure 40 show some typical application circuits the ADS7826/27/29 family. Figure 39 uses an ADS7826/27/29 and a multiplexer to provide for a flexible data acquisition circuit. A resistor string provides for various voltages at the multiplexer input. The selected voltage is buffered and driven into Vref. As shown in Figure 39, the input range of the ADS7826/27/29 family programmable to 100 mV, 200 mV, 300 mV, or 400 mV. The 100-mV range would be useful for sensors such as thermocouple shown. Figure 39 shows a basic data acquisition system. The ADS7826/27/29 family input range is 0 V to VCC, as the reference input is connected directly to the power supply. The 5- resistor and 1-F to 10-F capacitor filters the microcontroller noise on the supply, as well as any high-frequency noise from the supply itself. The exact values should be picked such that the filter provides adequate rejection of the noise.
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+3 V
+3 V
+3 V R8 26 k R7 5 0.4 V R9 1 k OPA237 U2 C1 10 F MUX R10 1 k 0.2 V A0 A1 R11 1 k 0.1 V R12 1 k 0.3 V
R1
1
R3 500 k R2 59 k R6 1 M C3 0.1 F VREF
C2 0.1 F
DCLOCK ADS7826/27/29 DOUT CS/SHDN U1 R5 500 C5 0.1 F P
TC1 Thermocouple
TC2 TC3 C4 10 F
R4 1 k
U3
ISO Thermal Block
U4
Figure 39. Thermocouple Application Using a MUX to Scale the Input Range of the ADS7826/27/29 family
+2.7V to +3.6V 5W + 1 mF to 10 mF ADS7826/27/29 VREF 0.1 mF +In -In GND CS DOUT DCLOCK VCC + 1 mF to 10 mF Microcontroller
Figure 40. Basic Data Acquisition System
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