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ADS5122
AD S51 22
SBAS272A - MAY 2003
8-Channel, 10-Bit, 65MSPS, 1.8V CMOS ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 8 DIFFERENTIAL ANALOG INPUTS q 1VPP DIFFERENTIAL INPUT RANGE q INT/EXT VOLTAGE REFERENCE q ANALOG/DIGITAL SUPPLY: 1.8V q DIGITAL I/O SUPPLY: 1.8V/3.3V q DIFFERENTIAL NONLINEARITY: 0.4LSB q INTEGRAL NONLINEARITY: 1.0LSB q SIGNAL-TO-NOISE: 59dB at fIN = 20MHz q POWER DISSIPATION: 733mW q INDIVIDUAL CHANNEL POWER-DOWN q 257-LEAD, 0.8 BALL PITCH, PLASTIC MicroSTAR BGATM (16mm * 16mm)
DESCRIPTION
The ADS5122 is a low-power, 8-channel, 10-bit, 65MSPS CMOS Analog-to-Digital Converter (ADC) that operates from a single 1.8V supply, while offering 1.8V and 3.3V digital I/O flexibility. A single-ended input clock is used for simultaneous sampling of up to eight analog differential input channels. The flexible duty cycle adjust circuit (DCASEL) allows the use of a non-50% clock duty cycle. Individual standby pins allow users the ability to power-down any number of ADCs. The internal reference can be bypassed to use an external reference to suit the accuracy and temperature drift requirements of the application. A 10-bit parallel bus on eight channels is provided with 3-state outputs. The speed, resolution, and low power of the ADS5122 make it ideal for applications requiring high-density signal processing in low-power environments. The ADS5122 is characterized for operation from 0C to 70C.
APPLICATIONS
q PORTABLE ULTRASOUND q PORTABLE INSTRUMENTATION
CLK AINA+ AINA- 10-Bit ADC 3-State Output Buffers AVDD STBY OE DRVDD DVDD
D[9:0]A
AINH- AINH+ 10-Bit ADC
3-State Output Buffers
D[9:0]H
IREFR
Internal Reference Circuit
CM DCASEL
AGND
BG
PDREF REFT REFB
CML DRVGND DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroSTAR BGA is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2003, Texas Instruments Incorporated
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ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage: AVDD to AGND, DVDD to DGND ............. -0.3V to +2.2V DRVDD to DRGND ................................... -0.3V to +4.0V AGND to DGND ...................................... -0.3V to +0.3V AVDD to DVDD .......................................... -2.2V to +2.2V Reference Voltage Input Range REFT, REFB to AGND ... -0.3V to AVDD + 0.3V Analog Input Voltage Range AIN to AGND ........... -0.3V to AVDD + 0.3V Clock Input CLK to DGND ..................................... -0.3V to AVDD + 0.3V Digital Input to DGND ........................................... -0.3V to DVDD + 0.3V Digital Outputs to DRGND .................................. -0.3V to DRVDD + 0.3V Operating Temperature Range (TJ) ................................... 0C to +105C Storage Temperature Range (TSTG) ................................. -65C + 150C NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE DESIGNATOR(1) GHK SPECIFIED TEMPERATURE RANGE 0C to +70C PACKAGE MARKING ADS5122CGHK ORDERING NUMBER ADS5122CGHK TRANSPORT MEDIA, QUANTITY Tray, 90
PRODUCT ADS5122
PACKAGE-LEAD MicroSTAR BGA-257
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
BLOCK DIAGRAM
AVDD CLK AINA+ AINA- 10-Bit ADC STBY OE DRVDD DVDD
3-State Output Buffers
D[9:0]A
AINB- AINB+ 10-Bit ADC
3-State Output Buffers
D[9:0]B
AINC+ AINC- 10-Bit ADC
3-State Output Buffers
D[9:0]C
AIND- AIND+ 10-Bit ADC
3-State Output Buffers
D[9:0]D
AINE+ AINE- 10-Bit ADC
3-State Output Buffers
D[9:0]E
AINF- AINF+ 10-Bit ADC
3-State Output Buffers
D[9:0]F
AING+ AING- 10-Bit ADC
3-State Output Buffers
D[9:0]G
AINH- AINH+ 10-Bit ADC
3-State Output Buffers
D[9:0]H
IREFR
Internal Reference Circuit
CM DCASEL
AGND
BG
PDREF REFT
REFB CML DRVGND DGND
2
ADS5122
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SBAS272A
DC CHARACTERISTICS
AVDD = DVDD = 1.8V, DRVDD = 3.3V, Clock = 65MSPS, 50% Clock Duty Cycle, -0.5dBFS Input Span, Internal Reference, IREFR = 4.42k, TMIN = 0C, TMAX = +70C, and typical values at TA = 25C, unless otherwise noted. ADS5122 PARAMETER RESOLUTION DC ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) No Missing Codes Gain Error Offset Error Gain Temperature Coefficient Gain Matching ANALOG INPUT Input Voltage Range (AIN+, AIN-) Input Voltage, Differential Full-Scale Input Common-Mode Range Input Resistance, RIN Input Capacitance, CIN INTERNAL REFERENCE VOLTAGES Reference, Top (REFT) Reference, Bottom (REFB) Int Reference Temperature Coefficient EXTERNAL REFERENCE GENERATION Reference, Top (REFT) Reference, Bottom (REFB) Input Resistance, REFRIN (between REFB and REFT) POWER SUPPLY Operating Supply Current, IDD Analog Operating Supply Current, IAVDD Digital Operating Supply Current, IDVDD Driver Operating Supply Current, IDRVDD Operating Voltage AVDD DVDD DRVDD Power-Dissipation Power Standby fIN = 3.5MHz 357 226 64 60 31 1.65 1.65 1.65 DRVDD = 3.3V DRVDD = 1.8V CLK Running CLK Stopped PDREF = 1, External REF, CLK Running PDREF = 1, External REF, CLK Stopped 5%, AVDD 1.8 1.8 1.8 733 590 68 54 14 1.6 5 375 245 74 70 40 2.0 2.0 3.6 800 615 mA mA mA mA mA V V V mW mW mW mW mW mW mV/V -0.9 -2.5 External Reference External Reference -1.0 CONDITION MIN TYP 10 0.4 1.0 Tested 0.1 0.2 6 0.7 +1.0 +2.5 +1.0 +2.5 MAX UNITS Bits LSB LSB %FSR %FSR ppm/C %FSR V VPP V k pF V V ppm/C V V
REFB 1 (REFT + REFB)/ 2 83 5 1.30 0.76 1.35 0.82 10 1.25 0.75 80
REFT
fCLK = 65MSPS
1.42 0.87
1.15 0.65
1.35 0.85
CL = 20pF, 3.3V CL = 20pF, 1.8V
18 5
Power-Supply Rejection Ratio, PSRR
DC CHARACTERISTICS
AVDD = DVDD = 1.8V, DRVDD = 3.3V, Clock = 65MSPS, 50% Clock Duty Cycle, -0.5dBFS Input Span, Internal Reference, and TMIN to TMAX, unless otherwise noted. ADS5122 PARAMETER DIGITAL INPUTS (STBY A-H, PDREF, OE) High-Level Input Voltage, VIH Low-Level Input Voltage, VIL High-Level Input Current, IIH Low-Level Input Current, IIL DIGITAL INPUTS (DCASEL) High-Level Input Voltage, VIH Low-Level Input Voltage, VIL High-Level Input Current, IIH Low-Level Input Current, IIL DIGITAL OUTPUTS (DRVDD = 3.3/1.8V) High-Level Output Voltage, VOH Low-Level Output Voltage, VOL External Load Capacitance, CL 3-State Leakage Current, ILEAK CONDITION DRVDD = 3.3V/1.8V VIH = DRVDD VIL = 0V MIN TYP MAX UNITS
0.70 * DRVDD 0.25 * DRVDD 1 1 0.70 * DVDD 0.25 * DVDD 1 1 0.8 * DRVDD 0.2 * DRVDD 15 1
V V A A V V A A V V pF A
VIH = DVDD VIL = 0V
IOH = -50A IOL = 50A OE = HIGH
ADS5122
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AC CHARACTERISTICS
AVDD = DVDD = 1.8V, DRVDD = 3.3V, 50% Clock Duty Cycle, CLK = 65MSPS, Analog Input at -0.5dBFS Input Span, Internal Voltage Reference, TMIN = 0C, TMAX = 70C, and typical values at TA = 25C, unless otherwise noted. ADS5122 PARAMETER Signal-to-Noise Ratio (SNR) CONDITION fIN = 3.5MHz fIN = 10MHz fIN = 20MHz Signal-to-Noise and Distortion (SINAD) fIN = 3.5MHz fIN = 10MHz fIN = 20MHz Effective Number of Bits (ENOB) fIN = 3.5MHz fIN = 10MHz fIN = 20MHz Spurious-Free Dynamic Range (SFDR) fIN = 3.5MHz fIN = 10MHz fIN = 20MHz 2nd-Harmonic Distortion (HD2) fIN = 3.5MHz fIN = 10MHz fIN = 20MHz 3rd-Harmonic Distortion (HD3) fIN = 3.5MHz fIN = 10MHz fIN = 20MHz 2-Tone Intermodulation Distortion Channel-to-Channel Crosstalk Effective Resolution Bandwidth Over-Voltage Recovery Time(1) Differential Gain(1) Differential Phase(1) NOTE: (1) Assured by design. (IMD) f1 = 4.43MHz, f2 = 4.53MHz at -6.5dB fIN = 10MHz, DRVDD = 3.3V 65 65 68 68 65 65 9.0 9.0 56 56 MIN 56 56 TYP 59 59 59 58 58 58 9.3 9.3 9.3 72 72 68 83 79 79 72 72 68 -69 89 30 20 1 0.25 MAX UNITS dB dB dB dB dB dB Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dB MHz ns % Degrees
SWITCHING CHARACTERISTICS
AVDD = DVDD = 1.8V, DRVDD = 3.3V, 50% Clock Duty Cycle, CLK = 65MSPS, Analog Input at -0.5dBFS Input Span, Internal Voltage Reference, TMIN = 0C, TMAX = 70C, and typical values at TA = 25C. ADS5122 PARAMETER Maximum Conversion Rate Clock Duty Cycle Data Latency(1) Clock to Data Valid OE to Outputs Enabled OE Rising to Outputs Tri-Stated Aperture Delay Aperture Uncertainty (Jitter) CONDITION MIN 5 DCASEL Enabled tDO(1) tEN(1) tDIS 30 to 70 6.5 8 8 8 1 2 TYP MAX 65 UNITS MSPS % Clk Cycles ns ns ns ns ps, r ms
10
TIMING DIAGRAM (Per ADC Channel)
Sample 1 Analog Input CLK 1 OE tEN D[9:0] S-6 S-5 S-4 S-3 S-2 S-1 tDIS S1 S2 S3 2 3 4 5 6 7 8 9 Sample 2
tDO
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ADS5122
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SBAS272A
PIN CONFIGURATION
Bottom View
0,80 W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 14,40 TYP
BGA
PIN DESCRIPTIONS
NAME AVDD AGND AINA+ AINA- AINB+ AINB- AINC+ AINC- AIND+ AIND- AINE+ AINE- AINF+ AINF- AING+ AING- AINH+ AINH- CLK REFT REFB CML BG IREFR DNC DNC NC DCASEL DVDD DGND PDREF PINS C6, C7, E6, F1, F2, F3, F5, F6, J6, N3, P3, P5, P6, P7, R6, V6, W6 A3, A5, B5, B9, C1, C5, C9, E3, E7, F7, G1, G5, G6, H6, J1, J2, M2, N5, N6, P8, R1, R2, R3, R7, U1, U5, U10, V5, V10, W3, W7 U7 V7 W4 V4 T1 T2 P2 P1 G3 G2 D1 D2 A4 B4 B6 A6 W9 K3, L1, J3 K5, J5, L5 L2, L3 K1 K6 L6 M1 E1, E2, E5, K2, U6, W5 N2 C2, C3, C4, D3, E8, F8, H3, H5, M3, M5, R8, T3, U3, U4, U8, V3, P13, R13 P17, L15, J14, F17, F12, E12 A2, A7, B1, B2, B3, B7, B13, C13, G15, H1, H2, H17, L17, M6, N1, N15, U2, U13, U14, V1, V2, V8, W2, W8 V9 I/O I I I I I I I I I I I I I I I I I I I/O I/O O I/O I I I I I I I I TERMINAL DESCRIPTION Analog Supply (1.8V) Analog Ground Analog Input Channel A Complementary Analog Input Channel A Analog Input Channel B Complementary Analog Input Channel B Analog Input Channel C Complementary Analog Input Channel C Analog Input Channel D Complementary Analog Input Channel D Analog Input Channel E Complementary Analog Input Channel E Analog Input Channel F Complementary Analog Input Channel F Analog Input Channel G Complementary Analog Input Channel G Analog Input Channel H Complementary Analog Input Channel H Clock Input Reference Top Reference Bottom Common-Mode Level Output Bandgap Decoupling (Decouple with 0.1F cap to AGND) Internal Reference Bias Current (Connect 4.42k resistor from this pin AGND to set internal bias amplifier current.) Do Not Connect Do Not Connect No Internal Connection Duty Cycle Adjust Digital Supply (1.8V) Digital Ground Power-Down Ref: 0 = internal reference, 1 = external reference. In external reference mode connect REFT to BG pin. Power-Down Channel A Power-Down Channel B Power-Down Channel C Power-Down Channel D Power-Down Channel E Power-Down Channel F Power-Down Channel G Power-Down Channel H Enable all Digital Outputs, Ch. A-H. OE: 0 = Outputs Enable. OE: 1 = Outputs disabled (3-state). Driver Digital Supply (1.8V or 3.3V) Driver Digital Ground
STBY A STBY B STBY C STBY D STBY E STBY F STBY G STBY H OE DRVDD DRGND
W10 P9 R9 U9 C8 B8 A8 A9 P10 B17, C16, D17, E9, E10, E11, E17, F9, H14, H15, K17, L14, N14, P12, P14, P15 R10, R12, R14 E13, F10, F11, F13, F14, F15, G14, G17, M14, M15, M17, N17, U11, U12, U15, U16
I I I I I I I I I I I I
ADS5122
SBAS272A
0,80
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DATA OUTPUT PINS
NAME D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A D0B D1B D2B D3B D4B D5B D6B D7B D8B D9B D0C D1C D2C D3C D4C D5C D6C D7C D8C D9C D0D D1D D2D D3D D4D D5D D6D D7D D8D D9D PINS V14 W14 V13 W13 V12 W12 R11 P11 V11 W11 V19 V18 U17 W18 V17 W17 V16 W16 V15 W15 P19 P18 R19 R18 R17 T19 T18 U19 U18 T17 K14 K15 K18 K19 L18 L19 M19 M18 N19 N18 I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O TERMINAL DESCRIPTION Bit 1, Channel A (LSB) Bit 2, Channel A Bit 3, Channel A Bit 4, Channel A Bit 5, Channel A Bit 6, Channel A Bit 7, Channel A Bit 8, Channel A Bit 9, Channel A Bit 10, Channel A (MSB) Bit 1, Channel B (LSB) Bit 2, Channel B Bit 3, Channel B Bit 4, Channel B Bit 5, Channel B Bit 6, Channel B Bit 7, Channel B Bit 8, Channel B Bit 9, Channel B Bit 10, Channel B (MSB) Bit 1, Channel C (LSB) Bit 2, Channel C Bit 3, Channel C Bit 4, Channel C Bit 5, Channel C Bit 6, Channel C Bit 7, Channel C Bit 8, Channel C Bit 9, Channel C Bit 10, Channel C (MSB) Bit 1, Channel D (LSB) Bit 2, Channel D Bit 3, Channel D Bit 4, Channel D Bit 5, Channel D Bit 6, Channel D Bit 7, Channel D Bit 8, Channel D Bit 9, Channel D Bit 10, Channel D (MSB) NAME D0E D1E D2E D3E D4E D5E D6E D7E D8E D9E D0F D1F D2F D3F D4F D5F D6F D7F D8F D9F D0G D1G D2G D3G D4G D5G D6G D7G D8G D9G D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H PINS F18 F19 G18 G19 H18 H19 J15 J17 J18 J19 A18 B18 C17 B19 C18 C19 D18 D19 E18 E19 A14 B14 C14 A15 B15 E14 C15 A16 B16 A17 C10 B10 A10 C11 B11 A11 A12 B12 C12 A13 I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O TERMINAL DESCRIPTION Bit 1, Channel E (LSB) Bit 2, Channel E Bit 3, Channel E Bit 4, Channel E Bit 5, Channel E Bit 6, Channel E Bit 7, Channel E Bit 8, Channel E Bit 9, Channel E Bit 10, Channel E (MSB) Bit 1, Channel F (LSB) Bit 2, Channel F Bit 3, Channel F Bit 4, Channel F Bit 5, Channel F Bit 6, Channel F Bit 7, Channel F Bit 8, Channel F Bit 9, Channel F Bit 10, Channel F (MSB) Bit 1, Channel G (LSB) Bit 2, Channel G Bit 3, Channel G Bit 4, Channel G Bit 5, Channel G Bit 6, Channel G Bit 7, Channel G Bit 8, Channel G Bit 9, Channel G Bit 10, Channel G (MSB) Bit 1, Channel H (LSB) Bit 2, Channel H Bit 3, Channel H Bit 4, Channel H Bit 5, Channel H Bit 6, Channel H Bit 7, Channel H Bit 8, Channel H Bit 9, Channel H Bit 10, Channel H (MSB)
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ADS5122
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TYPICAL CHARACTERISTICS
TA = 25C, AVDD = DVDD = 1.8V, DRVDD = 3.3V, fIN = -0.5dBFS, Internal Reference, Clock = 65MSPS, and Differential Input Range = 1Vp-p, unless otherwise noted.
SPECTRAL PERFORMANCE 0 fIN = 3.5MHz -20
Amplitude (dB) Amplitude (dB)
SPECTRAL PERFORMANCE 0 fIN = 9.8MHz -20 -40 -60 -80 -100 -120
-40 -60 -80 -100 -120 0 5 10 15 20 25 30 Frequency (MHz)
0
5
10
15
20
25
30
Frequency (MHz)
SPECTRAL PERFORMANCE 0 fIN = 19.8MHz -20
Amplitude (dB)
DIFFERENTIAL NONLINEARITY 0.6 0.4 0.2
DNL (LSB)
-40 -60 -80 -100 -120 0 5 10 15 20 25 30 Frequency (MHz)
0 -0.2 -0.4 -0.6 0 256 512 Code 768 1024
INTEGRAL NONLINEARITY 1.5 1.0
Amplitude (dBc)
2ND- AND 3RD-HARMONIC vs INPUT FREQUENCY -60 -65 -70 -75 -80 -85 -90 -95 -100 -105 2nd-Harmonic 3rd-Harmonic
0.5
INL (LSB)
0 -0.5 -1.0 -1.5 0 256 512 Code 768 1024
-110 1 10 Input Frequency (MHz) 100
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TYPICAL CHARACTERISTICS (Cont.)
TA = 25C, AVDD = DVDD = 1.8V, DRVDD = 3.3V, fIN = -0.5dBFS, Internal Reference, Clock = 65MSPS, and Differential Input Range = 1Vp-p, unless otherwise noted.
SNR AND SFDR vs CLOCK FREQUENCY 85 fIN = 3.5MHz 80 SFDR
SNR (dB) SFDR (dBc) SNR (dB) SFDR (dBc)
SNR AND SFDR vs CLOCK FREQUENCY 85 fIN = 10MHz 80 SFDR 75 70 65 60 SNR
75 70 65 SNR 60 55 5 10 15 20 25 30 35 40 45 50 55 60 65 70 Clock Frequency (MHz)
55 50 5 10 15 20 25 30 35 40 45 50 55 60 65 70 Clock Frequency (MSPS)
SNR AND SFDR vs CLOCK FREQUENCY 85 80 75
SNR (dB) SFDR (dBc)
68
SNR vs INPUT FREQUENCY
fIN = 20MHz SFDR
64 60
SNR (dB)
70 65 60 55 50 45 5 10 15 20 25 30 35 40 45 50 55 60 65 70 Clock Frequency (MSPS) SNR
56 52 48 44 1 10 Input Frequency (MHz) 100
SNR vs SWEPT INPUT POWER 70 60
SNR (dBFS, dBc)
SNR SWEPT INPUT POWER 70 dBFS fIN = 10MHz
dBFS
fIN = 3.5MHz 60
SNR (dBFS, dBc)
50 40 30 20 10 0 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 Input Amplitude (dBFS) dBc
50 40 30 20 10 0 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 Input Amplitude (dBFS) dBc
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ADS5122
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SBAS272A
TYPICAL CHARACTERISTICS (Cont.)
TA = 25C, AVDD = DVDD = 1.8V, DRVDD = 3.3V, fIN = -0.5dBFS, Internal Reference, Clock = 65MSPS, and Differential Input Range = 1Vp-p, unless otherwise noted.
DYNAMIC PERFORMANCE vs DUTY CYCLE 75 SFDR 70
SINAD (dB) SINAD (dB)
DYNAMIC PERFORMANCE vs CLOCK DUTY CYCLE 72 70 68 66 SFDR fIN = 10MHz
fIN = 3.5MHz
65 SNR SINAD 55
64 62 60 58 56 SNR
60
SINAD
50 25 30 35 40 45 50 55 60 65 70 75 Duty Cycle (%)
54 25 30 35 40 45 50 55 60 65 70 75 Clock Duty Cycle (%)
IAVDD vs CLOCK FREQUENCY 220 215 210 205 200 195 190 185 5 10 15 20 25 30 35 40 45 50 55 60 65 70 Clock Frequency (MSPS)
IDVDD (mA)
90 80 70 60 50 40 30 20 10 0 5
IDVDD vs CLOCK FREQUENCY
IAVDD (mA)
10 15 20 25 30 35 40 45 50 55 60 65 70 Clock Frequency (MSPS)
IDRVDD vs CLOCK FREQUENCY 80 70 60
IDRVDD (mA)
POWER vs TEMPERATURE 750 3.3V DRVDD 700
IDRVDD = 3.3V
Power (mW)
50 40 30 20
650
600
IDRVDD = 1.8V 10 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 Clock Frequency (MSPS)
550 -40 -20 0 20 40
1.8V DRVDD
60
80
100
Temperature (C)
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TYPICAL CHARACTERISTICS (Cont.)
TA = 25C, AVDD = DVDD = 1.8V, DRVDD = 3.3V, fIN = -0.5dBFS, Internal Reference, Clock = 65MSPS, and Differential Input Range = 1Vp-p, unless otherwise noted.
TOP REFERENCE vs TEMPERATURE 1.3485 1.3480 1.3475
Top Reference (V)
BOTTOM REFERENCE vs TEMPERATURE 0.8240 0.8235 Bottom Reference (V) 0.8230 0.8225 0.8220 0.8215 0.8210 0.8205 0.8200 0.8195
1.3470 1.3465 1.3460 1.3455 1.3450 1.3445 1.3440 1.3435 1.3430 -40 -20 0 20 40 60 80 100 Temperature (C)
-40
-20
0
20
40
60
80
100
Temperature (C)
GAIN ERROR vs TEMPERATURE 0.4 0.3 0.2 0.1
Gain Error (%) Error (%)
ZERO ERROR vs TEMPERATURE 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 Ch-A Ch-B Ch-C Ch-D Ch-E Ch-F Ch-G Ch-H
0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -40 -20 0 20 40 60 80 100 Temperature (C) Ch-A Ch-B Ch-C Ch-D Ch-E Ch-F Ch-G Ch-H
-40
-20
0
20
40
60
80
100
Temperature (C)
10
ADS5122
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SBAS272A
APPLICATION INFORMATION
CONVERTER OPERATION
The ADS5122 is an 8-channel, simultaneous sampling ADC. Its low power and high sampling rate of 65MSPS is achieved using a state-of-the-art switched capacitor pipeline architecture built on an advanced low-voltage CMOS process. The ADS5122 primarily operates from a +1.8V single supply. For additional interfacing flexibility, the digital I/O supply (DRVDD) can be set to either +1.8V or +3.3V. The ADC core of each channel consists of 10 pipeline stages. Each of the 10 stages produces one digital bit per stage. Both the rising and the falling clock edges are utilized to propagate the sample through the pipeline every half clock, for a total of five clock cycles. One and a half additional clock cycles are needed to pass the sample data through the digital error correction logic and the output latches. The total pipeline delay, or data latency, is therefore 6.5 clock cycles long. Since a common clock controls the timing of all eight channels, the analog signal is sampled at the same time, as well as the data on the parallel ports that become updated simultaneously.
used for input biasing purposes. The voltage at CML will assume the mid-point for either internal or external reference operation. In any case, it is recommended to bypass the CML pin with a ceramic 0.1F capacitor.
DRIVING THE ANALOG INPUTS Differential versus Single-Ended
The analog input of the ADS5122 allows it to be driven either single-ended or differentially. Differential operation of the ADS5122 requires an input signal that consists of an inphase and a 180 out-of-phase part simultaneously applied to the inputs (AIN+, AIN-). The differential operation offers a number of advantages, which in most applications will be instrumental in achieving the best dynamic performance of the ADS5122: * Signal swing is half that required for the single-ended operation and is therefore less demanding to achieve while maintaining good linearity performance from the signal source. * Reduced signal swing allows for more headroom of the interface circuitry and therefore a wider selection of the best suitable driver op amp. * Even-order harmonics are minimized. * Improved noise immunity based on the converter's common-mode input rejection. For the single-ended mode, the signal is applied to one of the inputs while the other input is biased with a DC voltage to the required common-mode level. Both inputs are identical in terms of their impedance and performance. Applying the signal to the complementary input (AIN-) instead of the AIN+ input, however, will invert the orientation of the input signal relative to the output code. This could be helpful, for example, if the input driver operates in inverting mode using input AIN- as the signal input will restore the phase of the signal to its original orientation.
INPUT IMPEDANCE
Due to the switched capacitor input, the input impedance of the ADS5122 is effectively capacitive, and the driving source needs to provide sufficient slew current to charge and discharge the input sampling capacitor. The input impedance of the ADS5122 is also a function of the sampling rate. As the sampling frequency increases, the input impedance decreases at a linear rate of 1/fs. For most applications, this does not represent a limitation since the impedance remains relatively high, for example, approximately 20k at the max sampling rate of 65MSPS. For applications using an op amp to drive the ADC, it is recommended that a series resistor, typically 10 to 50, be added between the amplifier's output and the converter inputs. This will isolate the converter's capacitive input from the driver and avoid potential gain peaking, or instability.
INPUT DRIVER CONFIGURATIONS
Transformer-Coupled Interface If the application requires a signal conversion from a singleended source to drive the ADS5122 differentially, an RFtransformer might be a good solution. The selected transformer must have a center tap in order to apply the commonmode DC voltage necessary to bias the converter inputs. ACgrounding the center tap will generate the differential signal swing across the secondary winding. Consider a step-up transformer to take advantage of signal amplification without the introduction of another noise source. Furthermore, the reduced signal swing from the source may lead to an improved distortion performance.
INPUT BIASING
The ADS5122 operates from a single +1.8V analog supply, and requires each of the analog inputs (AIN+, AIN-) to be externally biased by a suitable common-mode voltage. For example, with a common-mode voltage of +1V, the 1VPP fullscale, differential input signal will swing symmetrically around +1V, or between 0.75V and 1.25V. This is determined by the two reference voltages, the top reference (REFT), and the bottom reference (REFB). Typically, the input common-mode level is related to the reference voltages and defined as (REFT + REFB)/2. This reference mid-point is provided at the common-mode level output (CML) pin and can directly be
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The differential input configuration may provide a noticeable advantage of achieving good SFDR performance over a wide range of input frequencies. In this mode, both inputs (AIN+ and AIN-) of the ADS5122 see matched impedances. Figure 1 shows the schematic for the suggested transformercoupled interface circuit. The component values of the R-C low-pass may be optimized depending on the desired roll-off frequency. Single-Ended, AC-Coupled Driver The circuit of Figure 2 shows an example for driving the inputs of the ADS5122 in a single-ended configuration. The signal is AC-coupled between the driver amplifier and the converter input (AIN+). This allows for setting the required common-mode voltages for the ADC and op amp separately. The single-supply op amp is biased at mid-supply by two resistors connected at its noninverting input. Connecting each input to the CML pin provides the required commonmode voltage for the inputs of the ADS5122. Here, two resistors of equal value ensure that the inputs see closely
matched source impedances. If the op amp features a disable function, it could be easily tied together with the power-down pin of the ADS5122 channel (STBY). In the circuit example depicted in Figure 2, the OPA355's EN pin is directly connected to the STBY pin to allow for a power-down mode of the entire circuit. Other suitable op amps for singlesupply driver applications include the OPA634, OPA635, or OPA690, for example. DC-Coupled Interface with Differential Amplifier Differential input/output amplifiers can simplify the driver circuit for applications requiring input DC-coupling. Flexible in their configurations, such amplifiers can be used for singleended to differential conversion, allow for signal amplification, and also for filtering prior to the ADC. See Figure 3 for one possible circuit implementation using the THS4130 amplifier. Here, the amplifier operates with a gain of +1. The common- mode voltage available at the CML pin can be conveniently connected to the amplifier's VOCM pin to set the required input bias for the ADS5122.
+5V -5V
VIN OPA690 R1
RS
0.1F
1:n RT
RIN AIN+ RIN CIN AIN- CML ADS5122
R2 0.1F
FIGURE 1. Converting a Single-Ended Input Signal into a Differential Signal Using an RF-Transformer.
+3V/+5V R1
0.1F VIN OPA355 R2 RF 604 EN
RS 24
STBY 0.1F AIN+
33pF ADS5122 1.82k AIN- 1.82k RG 604 0.1F 0.1F CML
FIGURE 2. Single-Ended, AC-Coupled Driver Configuration for Single Supply.
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390 ADS5122 390 VIN+ VOCM THS4130 390 20 AIN+ 20 33pF AIN- 390
INTERNAL REFERENCE
The internal reference circuit of the ADS5122 consists of a bandgap voltage reference, the drivers for the top and bottom reference, and the resistive reference ladder. The corresponding reference pins are REFT, REFB, CML, IREFR, BG, and PDREF. In order to enable the internal reference, PDREF must be at a logic LOW (= 0) level. In addition, the bandgap pin (BG) should be decoupled with a 0.1F capacitor. The reference circuit provides the reference voltages to each of the eight channels. The reference buffers can be utilized to supply up to 1mA (sink and source) to an external circuitry. The CML pin represents the mid-point of the internal resistor ladder and is an unbuffered node. Loading of this pin should be avoided, as it will lead to degradation of the converter's linearity.
CML 0.1F 2.2F
FIGURE 3. DC-Coupled Interface Using Diferential I/O Amplifier THS4130. REFERENCE OPERATION For proper operation of the ADS5122 and its reference, an external 4.42k resistor must be connected from the IREFR pin to analog ground (AGND), as shown in Figure 4. While a 1% resistor tolerance is adequate, deviating from this resistor value will cause altered and degraded performance. To ensure proper operation with any reference configuration, it is necessary to provide solid bypassing at all reference pins in order to keep the clock feedthrough to a minimum. Figure 4 shows the recommended decoupling scheme. Good performance can be obtained using 0.1F low inductance ceramic capacitors. Adding tantalum capacitors (1F to 10F) may lead to a performance improvement, depending on the application. All bypassing capacitors should be located as close as possible to their respective pins.
USING EXTERNAL REFERENCES
For even more design flexibility, the internal reference can be disabled and an external reference voltage used. The utilization of an external reference may be considered for applications requiring higher accuracy or improved temperature performance. Especially in multi-channel applications, the use of a common external reference has the benefit of obtaining better matching of the full-scale range between converters. Setting the ADS5122 for external reference mode requires taking the PDREF pin HIGH. In addition, pins BG and REFT must be connected together (see Figure 5). The commonmode voltage at the CML pin will be maintained at approximately the mid-point of the applied reference voltages, according to CML (VREFT - VREFB)/2. The internal buffer amplifiers for REFT and REFB are disabled when the
+1.8V
AVDD
PDREF
ADS5122 BG 0.1F REFT CML REFB IREFR
0.1F
+
2.2F
0.1F
0.1F
+
4.42k 2.2F
FIGURE 4. Internal Reference; Recommended Configuration and Bypassing.
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ADS5122 operates in the external reference mode. The external reference circuit must be designed to drive the internal reference ladder (80) located between the REFT and REFB pins. For example, setting REFT = +1.25V and REFB = +0.75V will require a current drive capability of at least 0.5V/ 80 = 6.25mA. The external references can vary as long as the value of the external top reference (REFTEXT) stays within the range of +1.15V to +1.35V, and the external bottom reference (REFBEXT) stays within +0.65V to +0.85V (as shown in Figure 6).
The DCASEL pin is a logic input, with its logic levels related to the DVDD supply (+1.8V only): a) DCASEL = LOW (GND); in this mode the clock conditioning circuitry is disabled. Use this setting if the applied clock signal is a square-wave clock with a duty cycle of 50%, or if the duty cycle stays within a range of 48% to 52%. b) DCASEL = HIGH (DVDD); in this mode the clock conditioning circuitry is enabled. Use this setting if the applied external clock signal is a square-wave clock that does not meet the criteria listed above, but has a duty cycle in the range of 30% to 70%.
DIGITAL INPUTS AND OUTPUTS Clock Input
The clock input is designed to operate with +1.8V or +3.3V CMOS logic levels. The clock circuitry is internally connected to the DRVDD supply. Therefore, the input HIGH and LOW levels will vary depending on the applied DRVDD supply, see the DC Characteristic tables. Since both edges of the clock are used in this pipeline ADC, the ideal clock should be a square-wave logic signal with a 50% duty-cycle. Since this condition cannot always easily be met, the ADS5122 features an internal clock conditioning circuitry that can be activated through the duty-cycle adjust pin (DCASEL).
MINIMUM SAMPLING RATE
The pipeline architecture of the ADS5122 uses a switched capacitor technique for the internal track-and-hold stages. With each clock cycle, charges representing the captured signal level are moved within the ADC pipeline core. The high sampling rate necessitates the use of very small capacitor values. In order to hold the droop errors low, the capacitors require a minimum `refresh rate.' To maintain full accuracy of the acquired sample charge, the sampling clock of the ADS5122 should not be lower than the specified minimum of 5MSPS.
+1.8V
AVDD ADS5122 BG REFT CML REFB
PDREF
IREFR
0.1F
+
2.2F
0.1F
0.1F
+
4.42k 2.2F
REFTEXT
REFBEXT
FIGURE 5. External Reference; Recommended Configuration and Bypassing.
+5V +5V 1/2 OPA2234 + R3 2.2F 0.1F
4.7k
REFT
R1 REF1004 +2.5V + 10F
R4
ADS5122
1/2 OPA2234 R2 0.1F + 2.2F 0.1F
REFB
FIGURE 6. Circuit Example of an External Circuit Using a Single-Supply, Low-Power, Dual Op Amp (OPA2234).
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DATA OUTPUT FORMAT
The output data format of the ADS5122 is a positive Straight Offset Binary (SOB) code. Tables I and II show output coding of a single-ended and differential signal. For all data output channels, the MSBs are located at the D9x pins.
SINGLE-ENDED INPUT (AIN- = CML) +FS - 1LSB (AIN+ = CML + FSR/2) +1/2 FS Bipolar Zero (AIN+ = CML) -1/2 FS -FS (AIN+ = CML - FSR/2) STRAIGHT OFFSET BINARY (SOB) 11 1111 1111 11 0000 0000 10 0000 0000 01 0000 0000 00 0000 0000
channels. Note that the OE pin has no internal pull-up resistor and therefore requires a defined potential to be applied. The timing relations between OE and the output bus enable/disable times are shown in the Timing Diagram.
POWER-DOWN (STANDBY)
The ADS5122 is equipped with a power-down function for each of the eight channels. Labeled as STBY pins, the channel is in normal operating mode when the STBY pin is connected to logic high (H = 1). The selected ADC channel will be in a power-down mode if the corresponding STBY pin is connected to logic LOW (L = 0). The logic levels for the STBY pins are dependent on the DRVDD supply. The powerdown function controls internal biasing nodes, and as a consequence, any data present in the pipeline of the converter will become invalid. This is independent of whether the clock remains applied during power-down or not. Following a power-up, new valid data will become available after a minimum of seven clock cycles. As a note, the operation of the STBY pins is not intended for the use of dynamically multiplexing between the eight channels of the ADS5122.
TABLE I. Coding Table for Single-Ended Input Configuration with Input AIN- Tied to the Common-Mode Voltage (CML).
STRAIGHT OFFSET BINARY (SOB) 11 1111 1111 11 0000 0000 10 0000 0000 01 0000 0000 00 0000 0000
DIFFERENTIAL INPUT +FS - 1LSB (AIN+ = REFT, AIN- = REFB) +1/2 FS Bipolar Zero (AIN+ = AIN- = CML) -1/2 FS -FS (AIN+ = REFB, AIN- = REFT)
DIGITAL OUTPUT DRIVER SUPPLY, DRVDD
The ADS5122 uses a dedicated supply connection for the output logic drivers, DRVDD, along with its digital driver ground connections, labeled DRGND. Setting the voltage at DRVDD to either +3.3V or +1.8V alse sets the output logic levels accordingly, allowing the ADS5122 to directly interface to a selected logic family. The output stages are designed to supply sufficient current to drive a variety of logic families. However, it is recommended to use the ADS5122 with a +1.8V driver supply. This will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply lines, which otherwise may affect the AC performance of the converter. In some applications it might be advantageous to decouple the DRVDD supply with additional capacitors or a pi-filter.
TABLE II. Coding Table for Differential Input Configuration and 1VPP Full-Scale Range.
DIGITAL OUTPUT LOADING
Minimizing the capacitive loading on the digital outputs is very important in achieving the best performance. The total load capacitance is typically made up of two sources: the next stage input capacitance, and the parasitic/pc-board capacitance. It is recommended to keep the total capacitive loading on the data lines as low as possible ( 20pF). Higher capacitive loading will cause larger dynamic currents as the digital outputs are dynamic states. High current surges may cause feedback into the analog portion of the ADS5122 and affect the performance. If necessary, external buffers or latches close to the converter's output pins may be used to minimize the capacitive loading. A suggested device is the SN74AVC16827 (20-bit buffer/driver), a member of the `Advanced Very Low Voltage CMOS' logic family (AVC). Using such a logic device can also provide the added benefit of isolating the ADS5122 from any digital noise activities on the bus coupling back high-frequency noise. Some applications may also benefit from the use of series resistors ( 100) in the data lines. This will provide a current limit and reduce any existing over- or undershoot.
GROUNDING AND DECOUPLING
Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for highfrequency designs. Multilayer pc-boards are recommended for best performance since they offer distinct advantages such as minimizing ground impedance, separation of signal layers by ground layers, etc. The ADS5122 should be treated as an analog component. Whenever possible, the supply pins should be powered by the analog supply. This will ensure the most consistent results, since digital supply lines often carry high levels of noise which otherwise would be coupled into the converter and degrade the achievable performance. The ground pins should directly connect to an analog ground plane covering the pc-board area under the converter. While designing the layout it is important to keep the analog signal traces separated from any digital line to prevent noise coupling onto the analog signal path. Due to its high sampling rate, the ADS5122 generates high-frequency current transients and noise (clock feedthrough) that are fed
OUTPUT ENABLE
The ADS5122 provides one output enable pin (OE) that controls the digital outputs of all channels simultaneously. A LOW (L = 0) level on the OE pin will have all channels active and the converter in normal operation. Taking the OE pin HIGH (H = 1) will disable or tri-state the outputs of all
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back into the supply and reference lines. This requires that all supply and reference pins are sufficiently bypassed. In most cases 0.1F ceramic chip capacitors at each pin are adequate to keep the impedance low over a wide frequency range. Their effectiveness depends largely on the proximity to the individual supply pin. Therefore, they should be located as close as possible to the supply pins. In addition, a larger bipolar capacitor (1F to 22F) should be placed on the pc-board in proximity to the converter circuit.
GAIN ERROR
Gain Error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.
GAIN MATCHING
Variation in Gain Error between adjacent channels.
2ND-HARMONIC DISTORTION LAYOUT OF THE PCB WITH A MICROSTAR BGA PACKAGE
The ADS5122 is housed in a polymide film-based chipscale package (CSP). Like most CSPs, solder alloy balls are used as the interconnect between the package substrate and the board on which the package is soldered. For detailed information regarding these packages, please refer to literature number SSYZ015B, MicroStar BGA Packaging Reference Guide, which addresses the specific considerations required when integrating a MicroStar BGA package into the PCB design. This document can be found at: http://www-s.ti.com/sc/psheets/ssyz015b/ssyz015b.pdf The ratio of the rms signal amplitude to the rms value of the 2nd-harmonic component, reported in dBc.
3RD-HARMONIC DISTORTION
The ratio of the rms signal amplitude to the rms value of the 3rd-harmonic component, reported in dBc.
INTERMODULATION DISTORTION (IMD)
The 2-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) Intermodulation products. The individual input tone levels are at -6.5dB fullscale, and their envelope is at -0.5dB full-scale.
TERMINOLOGY
ANALOG BANDWIDTH
The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3dB.
OFFSET ERROR (ZERO-SCALE ERROR)
The first transition should occur for an analog value 1/2 LSB above negative full-scale. Offset error is defined as the deviation of the actual transition from that point.
OFFSET MATCHING APERTURE DELAY
The delay between the 50% point of the rising edge of the Clock and the instant at which the analog input is sampled. The change in offset error between adjacent channels.
POWER-SUPPLY REJECTION RATIO (PSRR)
The ratio of a change in input offset voltage to a change in power-supply voltage.
APERTURE UNCERTAINTY (JITTER)
The sample-to-sample variation in aperture delay.
SIGNAL-TO-NOISE AND DISTORTION (SINAD) EFFECTIVE NUMBER OF BITS (ENOB)
The ENOB is calculated from the measured SINAD based on the equation: SINAD - 1.76dB ENOB = 6.02 The ratio of the rms signal amplitude (set 0.5dB below fullscale) to the rms value of the sum all other spectral components, including harmonics but excluding DC.
SIGNAL-TO-NOISE RATIO (WITHOUT HARMONICS)
The ratio of the rms signal amplitude (set 0.5dB below fullscale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and DC.
EFFECTIVE RESOLUTION BANDWIDTH
The maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by half a bit.
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or dBFS (always related back to converter full-scale).
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PACKAGE DRAWING
GHK (S-PBGA-N257)
16,10 SQ 15,90 0,80 W V U T R P N M L K J H G F E D C B A 1 2 0,95 0,85 1,40 MAX 3 4 5 6 7 8 9
PLASTIC BALL GRID ARRAY
14,40 TYP
11 10 12
13 14
15 16
17 18
19
Seating Plane 0,12 0,08 0,55 0,45 0,08 M 0,10
0,45 0,35
4145273-3/C 12/99 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGATM configuration
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