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| ADS2806 ADS 280 6 (R) www.ti.com Dual, 12-Bit, 32MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM FEATURES q SPURIOUS FREE DYNAMIC RANGE: 73dB at 10MHz fIN q HIGH SNR: 67dB (2Vp-p), 69dB (3Vp-p) q INTERNAL OR EXTERNAL REFERENCE q LOW DLE: 0.4LSB q FLEXIBLE INPUT RANGE: 2Vp-p to 3Vp-p q TQFP-64 POWER PACKAGE APPLICATIONS q COMMUNICATIONS IF PROCESSING q COMMUNICATIONS BASESTATIONS q TEST EQUIPMENT q MEDICAL IMAGING q VIDEO DIGITIZING q CCD DIGITIZING DESCRIPTION The ADS2806 is a dual, high-speed, high dynamic range, 12-bit pipelined Analog-to-Digital Converter (ADC). This converter includes a high-bandwidth trackand-hold that gives excellent spurious performance up to and beyond the Nyquist rate. The differential nature of this track-and-hold and ADC circuitry minimizes even-order harmonics and gives excellent commonmode noise immunity. The track-and-hold can also be operated single-ended. The ADS2806 provides for setting the full-scale range of the converter without any external reference circuitry. +VS The internal reference can be disabled allowing low drive, internal references to be used for improved tracking in multichannel systems. The ADS2806 provides an overrange indicator flag to indicate an input signal that exceeds the full-scale input range of the converter. This flag can be used to reduce the gain of front end gain control circuitry. There is also an output enable pin to allow for multiplexing and testability on a PC board. The ADS2806 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. The ADS2806 is available in a TQFP-64 power package. OEA OVRA ADS2806 VIN INA T/H INA (Opt.) 12-Bit Pipelined A/D Error Correction Logic D12A * * * D1A 3-State Outputs INT/EXT FSSEL Internal Reference Timing Circuitry CLK VIN INB T/H INB (Opt.) CM 12-Bit Pipelined A/D Error Correction Logic 3-State Outputs D12B * * * D1B Optional External Reference OEB OVRB Copyright (c) 2000, Texas Instruments Incorporated SBAS178 Printed in U.S.A. December, 2000 SPECIFICATIONS At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 32MSPS, unless otherwise noted. ADS2806Y PARAMETER RESOLUTION SPECIFIED TEMPERATURE RANGE ANALOG INPUT 2V Full-Scale Input Range (Differential) 2V Full-Scale Input Range (Single-Ended) 3V Full-Scale Input Range (Differential) 3V Full-Scale Input Range (Single-Ended) Analog Input Bias Current Analog Input Bandwidth Input Impedance CONVERSION CHARACTERISTICS Sample Rate Data Latency DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 1MHz f = 10MHz No Missing Codes Integral Linearity Error, f = 1MHz Spurious Free Dynamic Range(1) f = 1MHz (-1dB input) f = 10MHz (-1dB input) Two-Tone Intermodulation Distortion(3) f = 9MHz and 10MHz (-7dB each tone) Signal-to-Noise Ratio (SNR) f = 1MHz (-1dB input) f = 10MHz (-1dB input) f = 1MHz (-1dB input) f = 10MHz (-1dB input) Signal-to-(Noise + Distortion) (SINAD)(4) f = 1MHz (-1dBFS input) f = 10MHz (-1dBFS input) f = 1MHz (-1dBFS input) f = 10MHz (-1dBFS Input) Channel-to-Channel Crosstalk Output Noise Aperture Delay Time Aperture Jitter Overvoltage Recovery Time DIGITAL INPUTS Logic Family Convert Command High Level Input Current(5) (VIN = 5V) Low Level Input Current (VIN = 0V) High Level Input Voltage Low Level Input Voltage Input Capacitance DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (IOL = 50A) Low Output Voltage, (IOL = 1.6mA) High Output Voltage, (IOH = 50A) High Output Voltage, (IOH = 0.5mA) Low Output Voltage, (IOL = 50A) High Output Voltage, (IOH = 50A) 3-State Enable Time 3-State Disable Time Output Capacitance Ambient Air 2Vp-p, INT or EXT Ref 2Vp-p, INT or EXT Ref 3Vp-p, INT or EXT Ref 3Vp-p, INT or EXT Ref -40 2 1.5 1.75 1 1 270 1.25 || 3 10k 6 32 CONDITIONS MIN TYP 12 Guaranteed +85 3 3.5 3.25 4 MAX UNITS Bits C V V V V A MHz M || pF Samples/s Clock Cycles 0.35 0.4 Guaranteed 2.5 73 73 -74.6 64 63 3Vp-p 3Vp-p 62 61 3Vp-p 3Vp-p 2Vp-p Input Grounded 67 66 69 68 66 65 69 69 80 0.2 2 1.2 2 +3V/+5V CMOS Compatible Rising Edge of Convert Clock 1.0 LSB LSB LSBs dBFS(2) dBFS dBc dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc LSBs rms ns ps rms ns 4.0 67 Start Conversion +50 +10 +2.0 +0.8 5 CMOS Straight Offset Binary VDRV = 5V VDRV = 5V VDRV = 5V VDRV = 5V VDRV = 3V VDRV = 3V OE = L(5) OE = H(5) +0.1 +0.2 +4.9 +4.8 +0.4 +2.4 20 2 5 40 10 A A V V pF V V V V V V ns ns pF 2 ADS2806 SBAS178 SPECIFICATIONS (Cont.) At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 32MSPS, unless otherwise noted. ADS2806Y PARAMETER CONDITIONS MIN TYP 0.5 16 1.5 66 1.0 23 70 10 20 10 20 3 2 375 +5.0 78 430 400 450 420 21.5 MAX 2.0 UNITS %FS ppm/C %FS ppm/C %FS ppm/C dB mV mV mV mV V V V mA mW mW mW mW C/W ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted) Zero Error (Midscale) at 25C Zero Error Drift (Midscale) Gain Error(6) at 25C Gain Error Drift(6) at 25C Gain Error(7) Gain Error Drift(7) Power Supply Rejection of Gain VS = 5% REFT Tolerance 2V Full Scale Deviation From Ideal 3.0V 3V Full Scale Deviation From Ideal 3.25V REFB Tolerance 2V Full Scale 3V Full Scale External REFT Voltage Range External REFB Voltage Range Reference Input Resistance POWER-SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Dissipation: VDRV = 5V VDRV = 3V VDRV = 5V VDRV = 3V Thermal Resistance, JA TQFP-64 Deviation From Ideal 2.0V Deviation From Ideal 1.75V REFB + 0.4 1.70 65 100 65 100 VS - 1.70 REFT - 0.4 Operating Operating External Reference External Reference Internal Reference Internal Reference +4.75 +5.25 475 NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full Scale. (3) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (4) Effective number of bits (ENOB) is defined by as (SINAD - 1.76) /6.02. (5) A 50k pull-down resistor is inserted internally on OE pins. (6) Includes internal reference. (7) Excludes internal reference. ADS2806 SBAS178 3 ABSOLUTE MAXIMUM RATINGS +VS ....................................................................................................... +6V Analog Input ........................................................... (-0.3V) to (+VS + 0.3V) Logic Input ............................................................. (-0.3V) to (+VS + 0.3V) Case Temperature ......................................................................... +100C Junction Temperature .................................................................... +150C Storage Temperature ..................................................................... +150C ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE DESIGNATOR PAP " SPECIFIED TEMPERATURE RANGE -40C to +85C " PACKAGE MARKING ADS2806Y " ORDERING NUMBER(1) ADS2806Y/1K5 ADS2806Y/250 TRANSPORT MEDIA Tape and Reel Tape and Reel PRODUCT ADS2806Y " PACKAGE TQFP-64 Power Package " NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K5 indicates 1500 devices per reel). Ordering 1500 pieces of "ADS2806Y/1K5" will get a single 1500-piece Tape and Reel. TIMING DIAGRAM N+1 Analog In N tD Clock tCONV N+2 N+3 N+4 N+5 tL tH N+6 N+7 6 Clock Cycles t2 Data Out N-6 N-5 N-4 N-3 N-2 N-1 t1 t3 Data Valid t4 N N+1 Data Invalid SYMBOL tCONV tL tH tD t1(1) t2(1) t3 t4 DESCRIPTION Convert Clock Period Clock Pulse Low Clock Pulse High Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max Data Valid Falling Edge Delay, CL = 15pF max Data Valid Rising Edge Delay, CL = 15pF max MIN 31.25 14.6 14.6 2.7 TYP tCONV/2 tCONV/2 2 8.2 7.5 5.6 MAX 100s UNITS ns ns ns ns ns ns ns ns 12 NOTE: (1) t1 and t2 times are valid for VDRV voltages of +2.7V to +5V. 4 ADS2806 SBAS178 PIN CONFIGURATION INT/EXT Top View REFBB REFTB GND GND CMB +VS INB INB TQFP REFBA REFTA GND GND 49 48 GND 47 GND 46 +VS 45 SEL 44 GND 43 +VS 42 OEA 41 GND 40 VDRVA 39 OVRA 38 A1 (MSB) 37 A2 36 A3 35 A4 34 A5 33 A6 32 CMA INA 51 30 64 GND GND +VS GND +VS OEB GND VDRVB OVRB 1 2 3 4 5 6 7 8 9 63 62 61 60 59 58 57 56 55 54 53 52 50 ADS2806Y B12 (LSB) 10 B11 11 B10 12 B9 13 B8 14 B7 15 B6 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 B5 B4 B3 B2 A9 A8 INA GND CLK GND A11 DVB B1(MSB) DVA PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 I/O DESIGNATOR GND GND +VS GND +VS OEB GND VDRVB OVRB B12 (LSB) B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 (MSB) DVB GND CLK GND DVA A12 (LSB) A11 A10 A9 A8 A7 A6 DESCRIPTION Ground Ground +5V Supply Ground +5V Supply Output Enable, Channel B GND Logic Driver Supply Voltage, Channel B Out of Range Indicator, Channel B Data Bit 12 (D0), Channel B Data Bit 11 (D1), Channel B Data Bit 10 (D2), Channel B Data Bit 9 (D3), Channel B Data Bit 8 (D4), Channel B Data Bit 7 (D5), Channel B Data Bit 6 (D6), Channel B Data Bit 5 (D7), Channel B Data Bit 4 (D8), Channel B Data Bit 3 (D9), Channel B Data Bit 2 (D10), Channel B Data Bit 1 (D11), Channel B Data Valid, Channel B Ground Clock Ground Data Valid, Channel A Data Bit 12 (D0), Channel A Data Bit 11 (D1), Channel A Data Bit 10 (D2), Channel A Data Bit 9 (D3), Channel A Data Bit 8 (D4), Channel A Data Bit 7 (D5), Channel A Data Bit 6 (D6), Channel A PIN 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I/O O O O O O O DESIGNATOR A5 A4 A3 A2 A1 (MSB) OVRA VDRVA GND OEA +VS GND SEL +VS GND GND GND INA INA CMA REFTA REFBA GND INT/EXT +VS GND REFBB REFTB CMB INB INB GND DESCRIPTION Data Bit 5 (D7), Channel A Data Bit 4 (D8), Channel A Data Bit 3 (D9), Channel A Data Bit 2 (D10), Channel A Data Bit 1 (D11), Channel A Out of Range Indicator, Channel A Logic Driver Supply Voltage, Channel A Ground Output Enable, Channel A +5V Supply Ground Input Range Select: HIGH = 3V, LOW = 2V +5V Supply Ground Ground Ground Analog Input, Channel A Complementary Analog Input, Channel A Common-Mode, Channel A Top Reference/Bypass, Channel A Bottom Reference/Bypass, Channel A Ground Reference Select: HIGH = External, LOW = Internal 50k Pull-Up Resistor +5V Supply Ground Bottom Reference/Bypass, Channel B Top Reference/Bypass, Channel B Common-Mode, Channel B Complementary Analog Input, Channel B Analog Input, Channel B Ground I O O O O O O O O O O O O O O I O O O O O O O O I I I I O I/O I/O I I/O I/O O I I ADS2806 SBAS178 A12 (LSB) A10 A7 5 TYPICAL PERFORMANCE CURVES At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 32MSPS, unless otherwise noted. SPECTRAL PERFORMANCE (Differential, 2Vp-p) 0 -20 fIN = 1MHz SFDR = 73.5dBFS SNR = 67.4dBFS 0 -20 SPECTRAL PERFORMANCE (Differential, 2Vp-p) fIN = 10MHz SFDR = 73.1dBFS SNR = 66dBFS Amplitude (dBFS) -40 -60 -80 -100 -120 0 4 8 Frequency (MHz) 12 16 Amplitude (dBFS) -40 -60 -80 -100 -120 0 4 8 Frequency (MHz) 12 16 SPECTRAL PERFORMANCE (Differential, 3Vp-p) 0 -20 fIN = 1MHz SFDR = 71.3dBFS SNR = 69.2dBFS SPECTRAL PERFORMANCE (Differential, 3Vp-p) 0 -20 fIN = 10MHz SFDR = 70.8dBFS SNR = 67.9dBFS Amplitude (dBFS) -40 -60 -80 -100 -120 0 4 8 Frequency (MHz) 12 16 Amplitude (dBFS) -40 -60 -80 -100 -120 0 4 8 Frequency (MHz) 12 16 TWO-TONE INTERMODULATION DISTORTION 0 -20 f1 = 9MHz (-7dBFS) f2 = 10MHz (-7dBFS) IMD(3) = 74.6dBc SNR/SFDR vs CLOCK 80 78 76 SNR, SFDR (dBFS) REF = 2V fIN = 3.5MHz SFDR Amplitude (dBFS) -40 -60 -80 -100 -120 0 4 8 Frequency (MHz) 12 16 74 72 70 68 66 64 62 60 24 26 28 30 32 34 36 Frequency (MHz) SNR 6 ADS2806 SBAS178 TYPICAL PERFORMANCE CURVES (Cont.) At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 32MSPS, unless otherwise noted. SNR/SFDR vs CLOCK 80 78 76 REF = 3V fIN = 3.5MHz DYNAMIC PERFORMANCE vs INPUT FREQUENCY 75 SFDR Dynamic Performance (dBFS) 70 THD 65 60 SINAD 55 50 45 Power = -1dBFS 40 SNR SFDR (dBFS) 74 72 70 68 66 64 62 60 24 26 28 SNR SFDR 30 Clock (MHz) 32 34 36 1 10 Frequency (MHz) 100 DYNAMIC PERFORMANCE vs INPUT FREQUENCY 85 80 100 90 80 SWEPT POWER (SFDR) dBFS fIN = 10MHz Dynamic Performance (dBFS) SFDR SFDR (dBFS, dBc) 75 70 65 60 55 50 45 40 1 10 Frequency (MHz) 100 Power = -6dBFS SINAD SNR THD 70 60 50 40 30 20 10 0 -60 -50 -40 -30 -20 -10 0 Input Amplitude (dBFS) dBc DIFFERENTIAL LINEARITY ERROR (Differential, 2Vp-p) 0.5 fIN = 10MHz 0.25 INTEGRAL LINEARITY ERROR (Differential, 2Vp-p) 4 3 2 ILE (LSB) fIN = 10MHz DLE (LSB) 1 0 -1 -2 -3 0 -0.25 -0.5 0 1024 2048 Code 3072 4096 -4 0 1024 2048 Code 3072 4096 ADS2806 SBAS178 7 TYPICAL PERFORMANCE CURVES (Cont.) At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 32MSPS, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR (Differential, 3Vp-p) 0.5 fIN = 10MHz 0.25 DLE (LSB) INTEGRAL LINEARITY ERROR (Differential, 3Vp-p) 4 3 2 ILE (LSB) fIN = 10MHz 1 0 -1 -2 -3 0 -0.25 -0.5 0 1024 2048 Code 3072 4096 -4 0 1024 2048 Code 3072 4096 OUTPUT NOISE HISTOGRAM (DC Input) 500k 3V Full Scale CROSSTALK (Channel A) 0 fIN = 4.8MHz -20 400k Amplitude (dBFS) -40 -60 -80 -100 Counts 300k 200k 100k N-2 N-1 N Code N+1 N+2 -120 0 4 8 Frequency (MHz) 12 16 SFDR/SNR vs TEMPERATURE 75 SFDR 70 Amplitude (dBFS) CROSSTALK (Channel B) 0 fIN = 3.5MHz -20 -40 -60 -80 -100 65 (dBFS) SNR 60 55 fIN = 10MHz -60 -40 -20 0 20 40 60 80 100 50 Temperature (C) -120 0 4 8 Frequency (MHz) 12 16 8 ADS2806 SBAS178 APPLICATION INFORMATION THEORY OF OPERATION The ADS2806 integrates two high-speed CMOS ADCs and an internal reference. The ADCs utilize a pipelined converter architecture consisting of eleven internal stages. Each stage feeds its data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at the 12-bit level. The output data becomes valid after the rising clock edge (see Timing Diagram). The pipeline architecture results in a data latency of 6 clock cycles. The analog input of the ADS2806 consists of a differential track-and-hold circuit. The differential topology along with tightly matched poly-poly capacitors produce a high level of AC performance at high sampling rates and in some undersampling applications. Both inputs (IN, IN) require external biasing using a common-mode voltage that is typically at the mid-supply level (+VS/2). DRIVING THE ANALOG INPUTS The analog inputs of the ADS2806 are very high impedance and should be driven through an R-C network designed to pass the highest frequency of interest. This prevents highfrequency noise in the input from affecting SFDR and SNR. The ADS2806 can be used in a wide variety of applications and deciding on the best performing analog interface circuit depends on the type of application. The circuit definition should include considerations of input frequency spectrum and amplitude, single-ended or differential drive and available power supplies. For example, communication (frequency domain) applications process frequency bands not including DC. In imaging (time domain) applications, the input DC component must be maintained into the ADC. Features of the ADS2806, including full-scale select (SEL), external reference, and CM output, provide flexibility to accommodate a wide range of applications. The ADS2806 should be configured to meet application objectives, while observing the headroom requirements of the driving amplifiers, to yield the best overall performance. The ADS2806 input structure allows it to be driven either single-ended or differentially. Differential operation of the ADS2806 requires an in-phase input signal and a 180 outof-phase part simultaneously applied to the inputs (IN, IN). The differential operation offers a number of advantages that, in most applications, will be instrumental in achieving the best dynamic performance of the ADS2806: * the signal swing is half of that required for the single-ended operation and, therefore, is less demanding to achieve while maintaining good linearity performance from the signal source * the reduced signal swing allows for more headroom in the interface circuitry and, therefore, a wider selection of the best suitable driver op amp * even-order harmonics are minimized * improves the noise immunity based on the converter's common-mode input rejection Using the single-ended mode, the signal is applied to one of the inputs, while the other input is biased with a DC voltage to the required common-mode level. Both inputs are equal in terms of their impedance and performance, except that applying the signal to the complementary input (IN) instead of the IN input will invert the input signal relative to the output code. For example, in case the input driver operates in inverting mode, using IN as the signal input will restore the phase of the signal to its original orientation. Time-domain applications may benefit from a single-ended interface configuration and its reduced circuit complexity. Driving the ADS2806 with a single-ended signal will result in a reduction of the distortion performance, while maintaining good signal-to-noise ratio (SNR). Employing dual-supply amplifiers and AC-coupling will usually yield the best results, while DC-coupling and/or single-supply amplifiers impose additional design constraints due to their headroom requirements, especially when selecting the 3Vp-p input range. However, single-supply amplifiers have the advantage of inherently limiting their output swing to within the supply rails. Alternatively, a voltage limiting amplifier, like the OPA688, may be considered to set fixed-signal limits and avoid any severe overrange condition for the ADC. The full-scale input range of the ADS2806 is defined by the reference voltages. For example, setting the range select pin to SEL = LOW, and using the internal references (REFT = +3.0V and REFTB = +2.0V), the full-scale range is defined as: FSR = 2 * (REFT - REFB) = 2Vp-p. The trade-off of the differential input configuration versus the single-ended is its higher complexity. In either case, the selection of the driver amplifier should be such that the amplifier's performance will not degrade the ADC's performance. The ADS2806 operates on a single power supply that requires a level shift to ground-based bipolar input signals to comply with its input voltage range requirements. The input of the ADS2806 is of a capacitive nature and the driving source needs to provide the current to charge or discharge the input sampling capacitor while the track-andhold is in track mode. This effectively results in a dynamic input impedance that depends on the sampling frequency. In most applications, it is recommended to add a series resistor, typically 20 to 50, between the drive source and the converter inputs. This will isolate the capacitive input from the source, which can be crucial to avoid gain peaking when using wideband operational amplifiers. Secondly, it will create a first-order, low-pass filter in conjunction with the specified input capacitance of the ADS2806. Its cutoff frequency can be adjusted even further by adding an external shunt capacitor from each signal input to ground. The optimum values of this R-C network depend on a variety of factors that include the ADS2806 sampling rate, the selected op amp, the interface configuration and the particular application (time domain versus frequency domain). Generally, increasing the size of the series resistor and/or capacitor will ADS2806 SBAS178 9 improve the SNR performance, but depending on the signal source, large resistor values may be detrimental to achieving good harmonic distortion. In any case, optimizing the R-C values for the specific application is encouraged. Transformer Coupled, Single-Ended to Differential Configuration If the application requires a signal conversion from a singleended source to drive the ADS2806 differentially, an RF transformer might be a good solution. The selected transformer must have a center tap in order to apply the commonmode DC voltage necessary to bias the converter inputs. AC grounding the center tap will generate the differential signal swing across the secondary winding. Consider a step-up transformer to take advantage of a signal amplification without the introduction of another noise source. Furthermore, the reduced signal swing from the source may lead to improved distortion performance. The differential input configuration provides the noticeable advantage of achieving high SFDR over a wide range of input frequencies. In this mode, both inputs of the ADS2806 see matched impedances. Figure 1 shows the schematic for the suggested transformer coupled interface circuit. The component values of the R-C low-pass may be optimized depending on the desired roll-off frequency. The resistor across the secondary side (RT) should be calculated using the equation RT = n2 x RG to match the source impedance (RG) for good power transfer and VSWR. The circuit example of Figure 1 shows voltage feedback amplifier OPA680 driving the RF transformer, which converts the single-ended signal into a differential. The OPA680 can be employed for either single- or dual-supply operation. For details on how to optimize its frequency response, refer to the OPA680 data sheet. With the 49.9 series output resistor, the amplifier emulates a 50 source (RG). Any DC content of the signal can be easily blocked by a capacitor (0.1F) to avoid DC loading of the op amp's output stage. AC-Coupled, Single-Ended to Differential Interface with Dual-Supply Op Amps Some applications demand a very high dynamic range and low levels of intermodulation distortion, but usually allow the input signal to be AC-coupled into the ADC. Appropriate driver amplifiers need to be selected to maintain the excellent distortion performance of the ADS2806. Often, these op amps deliver the lowest distortion with a small, ground-centered signal swing that requires dual power supplies. Because of the AC-coupling, this requirement can be easily accomplished, and the needed level shifting of the input signal can be implemented without affecting the driver circuit. RG VIN OPA680 47pF R1 RT 24.9 R2 47pF IN 1/2 ADS2806Y CM +2.5V 49.9 0.1F 1:n 24.9 IN + 10F 0.1F One Channel of Two FIGURE 1, Converting a Single-Ended Input Signal into a Differential Signal Using an RF-Transformer. 10 ADS2806 SBAS178 Figure 2 shows an example of such an interface circuit specifically designed to maximize the dynamic performance. The voltage feedback amplifier, OPA642, maintains an excellent distortion performance for input frequencies of up to 15MHz. The two amplifiers (A1, A2) are configured as an inverting and noninverting gain stage to convert the input signal from single-ended to differential. The nominal gain for this stage is set to +2V/V. The outputs of the OPA642s are AC-coupled to the converter's differential inputs. This will keep the distortion performance at its best since the signal range stays within the linear region of the op amp and sufficient headroom to the supply rails can be maintained. Four resistors located between the top (REFT) and bottom (REFB) reference shift the input signal to a common-mode voltage of approximately +2.5V. The interface circuit of Figure 2 can be modified to extend the bandwidth to approximately 25MHz, by replacing the OPA642 with its decompensated version, the OPA643. The OPA643 provides the necessary slew rate for a low distor- tion front end to the ADS2806. With a minimum gain stability of +3, the gain resistors have to be modified, as well as optimizing the series resistor and shunt capacitance at each of the converter inputs. AC-Coupled, Single-Ended-to-Differential Interface for Single-Supply Operation The previously discussed interface circuit can be modified if the system only allows for a single-supply operation, e.g., VS = +5V. Single-supply operation requires the driver amplifier to be biased as well in order to process a bipolar input signal. Typically, single-supply amplifiers do not achieve distortion performance as well as dual-supply op amps. The driver amplifier's output swing must exceed the full-scale input range of the converter. In addition, dual op amps, such as the current-feedback OPA2681, should be considered since they provide the closest open-loop gain and phase matching between the two channels. Shown in Figure 3 is a single-supply interface circuit for an AC-coupled input signal. With the ADS2806 set to the 2Vp-p input range, the top 402 200 VIN A1 OPA642 16.5 0.1F 1.82k 1.82k IN 100pF REFT 402 402 1/2 ADS2806Y A2 OPA642 16.5 0.1F IN 100pF 1.82k 1.82k REFB One Channel of Two FIGURE 2. AC-Coupled Differential Driver Interface with OPA642. RF 499 0.1F VIN RIN 249 1/2 OPA2681 RS 24.9 IN RP 499 VCM = +2.5V CM +5V 1/2 OPA2681 RS 24.9 IN 68pF 0.1F 68pF 499 1/2 ADS2806Y RF 499 RG 249 0.1F RP 499 One Channel of Two FIGURE 3. AC-Coupled, Differential Interface for Single-Supply Operation. ADS2806 SBAS178 11 and bottom references (REFT, REFB) provide an output voltage of +3.0V and +2.0V, respectively. The CM output of the ADS2806 is used to bias the inputs of the driving amplifiers. Using the OPA2681 on a single +5V supply, its ideal common-mode point is +2.5V, which coincides with the recommended common-mode input level for the ADS2806, thus eliminating the need for coupling capacitors between the amplifiers and the converter. The addition of a small series resistor (RS) between the output of the op amps and the input of the ADS2806 will be beneficial in almost all interface configurations. It will decouple the op amp's output from the capacitive load and avoid gain peaking that can result in increased noise. For best spurious and distortion performance, the resistor value should be kept below 100. Furthermore, the series resistor, in combination with the shunt capacitor, establishes a passive low-pass filter limiting the bandwidth for the wideband noise, thus improving the SNR. The spurious free dynamic range of this single-supply front end is limited by the second harmonic distortion. An improvement of several dB may be realized by adding a pull-down resistor (RP) at the output of each amplifier. This pulls a DC bias current out of the output stage of the amplifier. It is set to approximately 5mA, see Figure 3, but will vary depending on the amplifier used. Single-Ended, AC-Coupled, Dual-Supply Interface The circuit provided in Figure 4 shows typical connections for using the ADS2806 in a single-ended input configuration. The bias requirements for AC-coupling are provided by a single resistor to the CM output lead. The single-ended mode of operation should be considered for ease of interface complexity and applications where the dynamic performance can be compromised. The series resistor RS, along with the shunt capacitance, provide the means to adjust the bandwidth and optimize the performance towards good signal-to-noise ratio. In addition, the amplifier configuration can be easily modified for an anti-aliasing filter based on a second-order Sallen-Key or Multiple-Feedback topology. The interface example, shown in Figure 4, operates with the full-scale range of the ADS2806 set to 2Vp-p, leaving sufficient headroom for the output of the OPA642 to drive the converter and maintain low signal distortion. +5V VIN OPA642 68pF -5V RF 402 1.82k CM IN RG 402 0.1F 1/2 ADS2806Y RS 16.5 0.1F IN One Channel of Two FIGURE 4. AC-Coupling the Dual-Supply Amplifier OPA642 to the ADS2806 for a 2Vp-p Full-Scale Input Range. 12 ADS2806 SBAS178 DC-Coupled, Differential Driver with Level Shift Several applications will require that the bandwidth of the signal path include DC, in which case, the signal has to be DC-coupled to the ADC. An op amp based interface circuit can be configured to scale and level shift the input signal to be compatible with the selected input range of the ADC. The circuit shown in Figure 5 employs a dual op amp, OPA2681, to drive the input of the ADS2806 differentially. The singlesupply, general-purpose op amp OPA234 is added to buffer the common-mode voltage of +2.5V, available at the CM pin, and apply it to the input of the driver amplifier. This sets the correct DC voltage to bias the inputs of the ADS2806. It should be noted that any DC voltage differences between the IN and IN inputs of the ADS2806 will result in an offset error. Using the OPA2681, this circuit can be operated either with a single or a dual 5V supply. REFERENCE OPERATION The internal reference consists of a bandgap voltage reference, the drivers for the top and bottom reference, and the resistive reference ladder. References are internally connected, e.g.: REFTA is connected to REFTB, and REFBA is connected to REFBB. The bandgap reference circuit includes logic functions that allow setting the analog input swing of the ADS2806 to a differential full-scale range of either 2Vp-p or 3Vp-p by simply tying the SEL pin to a LOW or HIGH potential, respectively. While operating the ADS2806 in the external reference mode, the buffer amplifiers for REFT and REFB are disabled. The ADS2806 has an internal 50k pull-down resistor at the range select pin (SEL). Therefore, this pin can be either hardwired to ground or left unconnected, which will default the converter to a 2Vp-p full-scale input range (FSR). While set for the 2Vp-p range, the top and bottom reference voltages will be REFT = +3.0V and REFB = +2.0V. Switching to the 3Vp-p range changes those voltages to REFT = +3.25V and REFB = +1.75V. The reference buffers can be utilized to supply up to 1mA /channel (2mA total, sink and source) to external circuitry. To ensure proper operation with any reference configuration, it is necessary to provide solid bypassing at all reference pins in order to keep the clock feedthrough to a minimum, as shown in Figure 6. Good performance requires using 0.1F low inductance capacitors. All bypassing capacitors should be located as close to their respective pins as possible. 1/2 ADS2806 REFT CM REFB + 10F 0.1F + 10F 0.1F + 10F 0.1F FIGURE 6. Recommended Bypassing for the Reference Pins. 499 249 VIN 1/2 OPA2681 24.9 IN 22pF 249 499 1/2 ADS2806Y 499 IN 249 24.9 1/2 OPA2681 CM 22pF 499 24.9 249 0.1F 0.1F 1k OPA234 0.1F One Channel of Two FIGURE 5. DC-Coupled Input Driver with Level Shifting. ADS2806 SBAS178 13 USING EXTERNAL REFERENCES For even more design flexibility, the internal reference can be disabled and an external reference voltage used. Driving both channels with an external reference offers the best performance, as it allows the channels to maintain balance. The utilization of an external reference may be considered for applications requiring higher accuracy, improved temperature performance, or a wide adjustment range of the converter's full-scale range. In multichannel applications, the use of a common external reference has the benefit of obtaining better matching and drift of the full-scale range between converters. Figure 7 gives an example of an external reference circuit using a single-supply, lowpower, dual op amp (OPA2234). The external references can vary as long as the value of the external top reference (REFT) stays within the range of VS - 1.70V and REFB + 0.4V, and the external bottom reference (REFB) stays within 1.70V and REFT - 0.4V. Note that the function of the range selector pin (SEL) is disabled while the converter operates in external reference mode. Setting the ADS2806 for external reference mode requires the INT/EXT pin (pin 18) to be HIGH. The logic level applied to the INT/EXT pin of the ADS2806 determines if the converter operates with either the built-in reference or external reference voltages. Due to this function pin having an internal 50k pull-up resistor, the default configuration is external reference mode. Grounding this pin will activate the internal reference option. The input track and hold amplifier is differential. A positive 1Vp-p on the IN and its compliment, a negative 1Vp-p, on the IN (as shown in Figure 3) results in 2Vp-p on the output of the T/H. Likewise, 2Vp-p on the IN and 0Vp-p on the IN (as shown in Figure 4) results in 2Vp-p on the output of the T/H. Therefore, the reference voltages, REFT and REFB, are the same for both differential and single-ended inputs. See Table I. INPUT 2Vp-p Differential 1Vp-p Times 2 Inputs 2Vp-p Single-Ended 2Vp-p Times 1 Input 3Vp-p Differential 1.5Vp-p Times 2 Inputs 3Vp-p Single-Ended 3Vp-p Times 1 Input REFERENCE IN (Pin-50, 63) IN (Pin-51, 62) Internal or External Internal or External Internal or External Internal or External 2V to 3V 1.5V to 3.5V 3V to 2V 2.5VDC REFT REFB +3V +3V +2V +2V 1.75V to 3.35V 3.25V to 1.75V +3.25V +1.75V 1V to 4V 2.5VDC +3.25V +1.75V TABLE I. Reference Voltages for Input Signal Ranges. The external references may be changed for different tasks. The ADS2806 will follow the external references with a latency of 8 to 10 clock cycles. If it is desired to use INT/EXT and SEL to change the configuration of a circuit for different tasks, a large amount of time must be allowed. This time could be hundreds of microseconds. Refer to the Diagram on the front page. Note that there is no disconnect for external references. If it is desired to switch between internal and external references, disconnect switches must be added between the external references and the ADS2806. +5V +5V OPA2234 A1 R3 R4 < 3.30V Top Reference 4.7k R1 REF1004 +2.5V + 10F R2 0.1F OPA2234 A2 > 1.70V Bottom Reference One Channel of Two FIGURE 7. Example for an External Reference Driver Using the Dual, Single-Supply Op Amp, OPA2234. 14 ADS2806 SBAS178 DIGITAL INPUTS AND OUTPUTS Clock Input Requirements Both channels of the ADS2806 are controlled by the same clock on the rising edge. Utilizing a single clock reduces timing uncertainty in the sampling of the two channels. Clock jitter is critical to the SNR performance of high-speed, high-resolution ADCs. Clock jitter leads to aperture jitter (tA), which adds noise to the signal being converted. The ADS2806 samples the input signal on the rising edge of the CLK input. Therefore, this edge should have the lowest possible jitter. The jitter noise contribution to total SNR is given by the following equation. If this value is near your system requirements, input clock jitter must be reduced. Jitter SNR = 20 log 1 rms signal to rms noise 2 IN t A SINGLE-ENDED INPUT (IN = CM, Pins 52, 61) +FS-1LSB (IN = CMV + FSR/2) +1/2 FS Bipolar Zero (IN = VCM) -1/2 FS -FS (IN = CMV - FSR/2) STRAIGHT OFFSET BINARY (SOB) 1111 1111 1111 1100 0000 0000 1000 0000 0000 0100 0000 0000 0000 0000 0000 TABLE II. Coding Table for Single-Ended Input Configuration with IN Tied to the Common-Mode Voltage. STRAIGHT OFFSET BINARY (SOB) 1111 1111 1111 1100 0000 0000 1000 0000 0000 0100 0000 0000 0000 0000 0000 DIFFERENTIAL INPUT +FS-1LSB (IN = +3V, IN = +2V) +1/2 FS Bipolar Zero (IN = IN = VCM) -1/2 FS -FS (IN = +2V, IN = +3V) where: IN is input signal frequency tA is rms clock jitter Particularly in undersampling applications, special consideration should be given to clock jitter. The clock input should be treated as an analog input in order to achieve the highest level of performance. Any overshoot or undershoot of the clock signal may cause degradation of the performance. When digitizing at high sampling rates, the clock should have 50% duty cycle (tH = tL), along with fast rise and fall times of 2ns or less. The clock input of the ADS2806 can be driven with either 3V or 5V logic levels. Using low-voltage logic (3V) may lead to improved AC performance of the converter. Over Range Indicator (OVR) If the analog input voltage exceeds the set full-scale range, an over range condition exists. The "OVR" pin of the ADS2806 can be used to monitor any such out-of-range condition. This "OVR" output is updated along with the data output corresponding to the particular sampled analog input voltage. Therefore, the OVR data is subject to the same pipeline delay as the digital data. The OVR output is LOW when the input voltage is within the defined input range. It will go to HIGH if the applied signal exceeds the full-scale range. Data Outputs The digital outputs of the ADS2806 can be set to a highimpedance state by driving OE (pins 6 and 42) with a logic HIGH. Normal operation is achieved with pins 6 and 42 LOW due to internal pull-down resistors. This function is provided for testability purposes and is not meant to drive digital buses directly, or be dynamically changed during the conversion process. The output data format of the ADS2806 is in positive Straight Offset Binary code, as shown in Tables I and II. This format can easily be converted into the Binary Two's Complement code by inverting the MSB. TABLE III. Coding Table for Single-Ended Input Configuration with IN Tied to the Common-Mode Voltage. Data output is in the form of two parallel words. It is recommended that the capacitive loading on the data lines be as low as possible (< 15pF). Higher capacitive loading will cause larger dynamic currents as the digital outputs are changing. Those high current surges can feed back to the analog portion of the ADS2806 and affect the performance. If necessary, external buffers or latches close to the converter's output pins may be used to minimize the capacitive loading. They also provide the added benefit of isolating the ADS2806 from high-frequency digital noise on the bus coupling back into the converter. Digital Output Driver Supply (VDRV) Each channel of the ADS2806 has a separate dedicated supply pin (8, 40) for the output logic drivers, VDRV, which are not internally connected to the other supply pins. Setting the voltage at VDRV to +5V or +3V, the ADS2806 produces corresponding logic levels and can directly interface to the selected logic family. The output stages are designed to supply sufficient current to drive a variety of logic families. However, it is recommended to use the ADS2806 with +3V logic supply. This will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply line that may affect the AC performance of the converter. In some applications, it might be advantageous to decouple the VDRV pin with additional capacitors or a pi-filter. OUTPUT ENABLE (OE) The digital outputs of the ADS2806 can be set to high impedance (tri-state) by driving OEA and OEB (pins 6, 42) with a logic HIGH. Normal operation is achieved with the same pins pulled LOW. ADS2806 SBAS178 15 GROUNDING AND DECOUPLING Proper grounding, bypassing, short trace lengths, and the use of power and ground planes are particularly important for high-frequency designs. Multilayer PC boards are recommended for best performance since they offer distinct advantages, such as minimizing ground impedance, separation of signal layers by ground layers, etc. The ADS2806 should be treated as an analog component. Whenever possible, the supply pins should be powered by the analog supply. This will ensure the most consistent results, since digital supply lines often carry high levels of noise that otherwise would be coupled into the converter and degrade the achievable performance. The ground pins should directly connect to an analog ground plane that covers the PC board area under the converter. While designing the layout it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog signal path. Due to its high sampling rate, the ADS2806 generates high-frequency current transients and noise (clock feedthrough) that are fed back into the supply and reference lines. This requires that all supply and reference pins are sufficiently bypassed. Figure 8 shows the recommended decoupling scheme for the ADS2806. In most cases, 0.1F ceramic chip capacitors at each pin are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual supply pin. Therefore, they should be located as close to the supply pins as possible. If system supplies are not a low enough impedance, adding a small tantalum capacitor will yield the best results. ADS2806 +VS 57 0.1F GND 55, 58 +VS 3 (46) 0.1F GND 1, 2, 64 (47, 48, 49) +VS 5 (43) 0.1F GND 4 (44) GND 7 (41) 0.1F VDRV 8 (40) GND 23, 25 +5V Numbers In Parenthesis Indicate Pins for Channel A +3V/+5V FIGURE 8. Recommended Bypassing for the Supply Pins. 16 ADS2806 SBAS178 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, license, warranty or endorsement thereof. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Resale of TI's products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright (c) 2001, Texas Instruments Incorporated |
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