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Preliminary Technical Data
FEATURES
Output frequency range: 50 MHz to 2200 MHz Modulation bandwidth: dc to 700 MHz 1 dB output compression: +9 dBm @ 350 MHz Noise floor: -158 dBm/Hz Sideband Suppression: -40 dBc @ 350 MHz Single supply: 4.75 V to 5.5 V 24-lead exposed-paddle LFCSP package
ENBL
50 MHz to 2200 MHz Quadrature Modulator ADL5385
FUNCTIONAL BLOCK DIAGRAM
BIAS IBBP TEMPERATURE SENSOR
TEMP
IBBN
APPLICATIONS
Radiolink Infrastructure Cable Modem Termination Systems Wireless Infrastructure Systems Wireless LAN/wireless local loop LMDS/broadband wireless access systems
LOIP Divide-by-2 Quadrature Phase Splitter LOIN VOUT
QBBP
QBBN
Figure 1 Block Diagram
PRODUCT DESCRIPTION
The ADL5385 is a silicon, monolithic, quadrature modulator that is designed for use from 50 MHz to 2200 MHz. Its excellent phase accuracy and amplitude balance enable high performance IF or direct RF modulation for communication systems. The single-ended two-times-LO input signal is buffered, and then split into in-phase and quadrature signals at one-timesLO. These two LO signals are further buffered and then mixed with the corresponding I channel and Q channel baseband signals in two Gilbert cell mixers. The mixers' outputs are then summed together in the output amplifier. The output amplifier is designed to drive 50 loads. The ADL5385 can be used as a IF or direct-to-RF modulator in digital communication systems. The wide baseband input bandwidth allows for baseband drive or drive from a complex IF. Typical applications are in Radiolink Transmitters, Cable Modem Termination systems and Broadband Wireless Access Systems. The ADL5385 is fabricated using Analog Devices' advanced Silicon Germanium bipolar process and is available in a 24Lead Pb-free LFCSP with exposed paddle. Performance is specified over a -40C to +85C temperature range. A Pb-free evaluation board is available.
Pr. E 3.3.06
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2006 Analog Devices, Inc. All rights reserved.
ADL5385 SPECIFICATIONS
Preliminary Technical Data
Table 1. VS = 5 V; Ambient Temperature = 25C; LO = -7 dBm; I/Q inputs = 1.4 V p-p differential sine waves in quadrature on a 500 mV dc bias; baseband frequency = 1 MHz; LO source and RF output load impedances are 50 , unless otherwise noted.
Parameter Output Frequency Range External LO Frequency Range Output Frequency = 50 MHz Output Power Output P1 dB Carrier Feedthrough Sideband Suppression Second Baseband Harmonic Third Baseband Harmonic Output IP3 Noise Floor Output Return Loss Output Frequency = 140 MHz Output Power Output P1 dB Carrier Feedthrough Sideband Suppression Second Baseband Harmonic Third Baseband Harmonic Output IP3 Noise Floor Output Return Loss Output Frequency = 350 MHz Output Power Output P1 dB Carrier Feedthrough Sideband Suppression Second Baseband Harmonic Third Baseband Harmonic Output IP3 Noise Floor Output Return Loss Output Frequency = 860 MHz Output Power Output P1 dB Carrier Feedthrough Sideband Suppression Second Baseband Harmonic Third Baseband Harmonic Output IP3 Noise Floor Output Return Loss Single (lower) Sideband Output unadjusted (nominal drive level) unadjusted (nominal drive level) (FLO - (2 x FBB)) (FLO + (3 x FBB)) F1= 3.5 MHz, F2 = 4.5 MHz, POUT = -5 dBm per tone 20 MHz offset from LO, all BB inputs at a bias of 500 mV 20 MHz offset from LO, Output Power = -5 dBm Conditions External LO frequency is twice output frequency Single (lower) Sideband Output unadjusted (nominal drive level) unadjusted (nominal drive level) (FLO - (2 x FBB)) (FLO + (3 x FBB)) F1= 3.5 MHz, F2 = 4.5 MHz, POUT = -5 dBm per tone 20 MHz offset from LO, all BB inputs at a bias of 500 mV 20 MHz offset from LO, Output Power = -5 dBm Min 50 100 Typ Max 2200 4400 Unit MHz MHz dBm dBm dBm dBc dBc dBc dBm dBm/Hz dBm/Hz dB dBm dBm dBm dBc dBc dBc dBm dBm/Hz dBm/Hz dB
6 10 -50 -50 -50 -50 24 -158 -158 10 6 10 -46 -50 -50 -50 24 -158 -158 10
Single (lower) Sideband Output unadjusted (nominal drive level) unadjusted (nominal drive level) (FLO - (2 x FBB)) (FLO + (3 x FBB)) F1= 3.5 MHz, F2 = 4.5 MHz, POUT = -5 dBm per tone 20 MHz offset from LO, all BB inputs at a bias of 500 mV 20 MHz offset from LO, Output Power = -5 dBm
6 10 -41 -40 -50 -50 24 -158 -158 10 4.5 9 -37 -35 -50 -50 24 -158 -158 10
dBm dBm dBm dBc dBc dBc dBm dBm/Hz dBm/Hz dB dBm dBm dBm dBc dBc dBc dBm dBm/Hz dBm/Hz dB
Single (lower) Sideband Output unadjusted (nominal drive level) unadjusted (nominal drive level) (FLO - (2 x FBB)) (FLO + (3 x FBB)) F1= 3.5 MHz, F2 = 4.5 MHz, POUT = -5 dBm per tone 20 MHz offset from LO, all BB inputs at a bias of 500 mV 20 MHz offset from LO, Output Power = -5 dBm
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Preliminary Technical Data
Parameter LO INPUTS LO Drive Level Input Impedance Input Return Loss BASEBAND INPUTS I and Q Input Bias Level Bandwidth (3 dB) TEMPERATURE OUTPUT Output Voltage Temperature Slope POWER SUPPLIES Voltage Supply Current Conditions Pins LOIP and LOIN Characterization performed at typical level 350 MHz Pins IBBP, IBBN, QBBP, QBBN Min Typ -7 50 -10 500 700 TEMP TA = 27.15C, 300K, RL = 1 M -40C TA +85C, RL = 1 M Pins VPS1 and VPS2 4.75 210 1.5 4.7
ADL5385
Max Unit dBm dB mV MHz V mV/C 5.5 V mA
Rev. PrE | Page 3 of 7
ADL5385 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
Preliminary Technical Data
QBBP 18
QBBN 17
IBBN 14
COM2 16
COM2 15
IBBP 13 ENBL 12 VPS2 11 TEMP 10 VPS1 9 VPS1 8 VOUT 7 6 COM1
19 COM3
20 COM3
21 LOIP
ADL5385
4 x 4 LFCSP
Exposed Paddle 5 COM1
22 LOIN
23 VPS3
24 VPS3 1 NC 2 NC
3 NC
Figure 2 ADL5385 Pinout
Table 2. Pin Function Descriptions
Pin No. 1,2,3,4 5,6,15,16, 19,20 7 8,9,11,23,24 10 12 13,14,17,18 Mnemonic NC COM1, COM2, COM3 VOUT VPS1, VPS2, VPS3 TEMP ENBL IBBP, IBBN, QBBN, QBBP Description No Connection. These pins can be left open or tied to ground. Common Pins. COM1, COM2, and COM3 should all be connected to a ground plane via a low impedance path. Device Output. Single-ended, 50 internally biased RF/IF output. Pin must be ac-coupled to the load. Power Supply Pins. Decouple each pin with a 0.1uF capacitor. Pins 8 and 9 can share a single capacitor as can pins 23 and 24 Temperature Sensor Output Chip Enable. Set to 0V to enter sleep mode. Set to supply voltage to activate device. Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs should be dc-biased to approximately 500 mV dc, and should be driven from a low impedance source. Nominal characterized ac signal swing is 700 mV p-p on each pin (150 mV to 850 mV). This results in a differential drive of 1.4 V p-p with a 500 mV dc bias. These inputs are not self-biased and must be externally biased. Single-Ended two-times Local Oscillator Input. Internally dc-biased . LOIP should be accoupled. Common for LO Input. AC couple through a low impdeance path to ground. Equivalent Circuit
21 22
LOIP LOIN
Rev. PrE | Page 4 of 7
4 NC
Preliminary Technical Data BASIC CONNECTIONS
Refer to the evaluation board schematic for the basic connections for operating the AD5385 (Figure 2). A single power supply of between 4.75 V and 5.5 V is applied to pins VPS1 and VPS2 and VPS3. All VPS pins must be connected to the same potential. Each pin should be decoupled with a 0.1 uF capacitor. These capacitors should be located as close as possible to the device. Pins 8 and 9 can share a single capacitor as can pins 23 and 24. The voltage applied to Pin 12 (ENBL) determines whether the part is in a sleep mode or active mode. When this pin is grounded the internal biasing circuitry is disabled and the part draws minimal supply current. When this pin is tied to the supply voltage, the bias circuitry is activated and the part is in active mode. Pins COM1, COM2, and COM3 should all be tied to the same ground plane through low impedance paths. The exposed paddle on the under side of the package should be soldered to a low impedance ground plane. If multiple ground planes exist on the circuit board, these should be stitched together with multiple vias to enhance thermal and electrical performance.
ADL5385
The baseband inputs QBBP, QBBN, IBBP and IBBN must be driven from a differential source. The nominal drive level of 1.4 Vpp differential (700 mVpp on each pin) should be biased at 500 mV. A Single -ended Local Oscillator should be applied to the LOIP pin through an ac-coupling capacitor. The recommended LO drive power is -7 dBm. The LO return pin, LOIN, should be accoupled to ground though a low impedance path. The RF output is available at pin 7, VOUT. This pin should also be ac-coupled. Both LOIP and VOUT have nominal broadband input and output impedances of 50 and do not need further external matching. Pin 10, TEMP, provides a output voltage that is proportional to ambient temperature. At 25 degC, the output voltage on this pin is 1.5 V. The temperature coefficient of this pin is 4.71 mV/C.
Rev. PrE | Page 5 of 7
ADL5385 EVALUATION BOARD
QBBP QBBN IBBN IBBP RFPQ 0 RFNQ 0 RFNI 0 RFPI 0
Preliminary Technical Data
CFPQ Open
RTQ Open
CFNQ Open
CFNI Open
RTI Open
CFPI Open
QBBN 17
QBBP 18
IBBN 14
COM2 16
COM2 15
IBBP 13
OFF ENBL ENBL 12 R22 10k R21 SW21 49.9
ON ENBL
19 COM3
20 COM3 LO CLOP 0.1uF CLON 0.1uF 21 LOIP
Z1
VPS2 11 C16 0.1uF R13 0 C15 OPEN
VPOS
22 LOIN
ADL5385
4 x 4 LFCSP
Exposed Paddle
5 COM1 6 COM1 1 NC 2 NC 3 NC 4 NC
TEMP 10
TEMP TEMP VPS1 9 RTEMP 200
23 VPS3
VPS1 8 C14 0.1uF VOUT 7 R12 0 C13 OPEN
VPOS
24 VPS3 C11 OPEN R11 0 C12 0.1uF
VOUT COUT 0.1uF
VPOS
GND
Figure 3. Evaluation Board Schematic
Figure 3. Layout of Evaluation Board, Top Layer
A populated ADL5385 evaluation board is available. The ADL5385 has an exposed paddle underneath the package, which is soldered to the board. The Table 3. Evaluation Board Configuration Options
Component VPOS, GND SW21 RFNQ, CFNQ, RTQ, CFPQ, RFPQ, RFNI, CFNI, RTI, CFPI, RFPI
evaluation board is designed without any components on the underside of the board so that heat may be applied to the underside for easy removal and replacement of the ADL5385.
Function Power Supply and Ground Clip Leads Chip Enable Select. SW21 sets the voltage on the ENBL pin. OFF = 0 V (disabled) ON = 5V (enabled) Baseband Input Filters: These components can be used to implement a low-pass filter for the baseband signals.
Default Condition Not applicable SW21 = ON RFNQ, RFPQ, RFNI RFPI = 0 (0402) RTQ, RTI = Open (0402) CFNQ,CFPQ,CFNI,CFPI = Open (0402)
Rev. PrE | Page 6 of 7
ADL5385 OUTLINE DIMENSIONS
Figure 4. 24-Lead LFCSP with exposed paddle. Dimensions shown in millimeters
TABLE 4. ORDERING GUIDE
Model ADL5385ACPZ-R71 ADL5385ACPZ-WP ADL5385-EVAL Temperature Range (C) -40 to +85 -40 to +85 Package Description 7" Tape and Reel Waffle Pack Evaluation Board Package Option
1
Z indicates Pb-free
(c) 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06118-0-4/06(PrE)
Rev. 0 | Page 7 of 7

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