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Preliminary Datasheet
FEATURES
Optimized for Fiber-Optic Photodiode Interfacing Measures Current Over Three Decades Law Conformance 0.3 dB from 100 nA to 100 A Single or Dual Supply Operation (3 V to 5.5 V total) Full Log-Ratio Capabilities Temperature Stable Nominal slope of 10 mV/dB (200 mV/decade) Nominal Intercept of 1 nA (set by external resistor) Optional Adjustment of Slope and Intercept Rapid Response Time for a given Current Level Miniature 16 pin Chip Scale Package (LFCSP 3x3 mm) Low Power: ~5mA Quiescent Current
60dB-range (100nA-100A) Low-Cost Logarithmic Converter
ADL5306
APPLICATIONS
Low Cost Optical Power Measurement Wide Range Baseband Logarithmic Compression Measurement of Current- and Voltage-Ratios Optical Absorbance Measurement PRODUCT DESCRIPTION The ADL5306 is a low cost micro-miniature logarithmic converter optimized for the determination of optical power in fiber-optic systems. The ADL5306 is a derivative of the popular AD8304 and AD8305 translinear logarithmic converters. The family of devices provide wide measurement dynamic range in a versatile and easily-used form. A single supply voltage of between 3 V and 5.5 V is adequate; dual supplies may optionally be used. The low quiescent current (typically 5 mA) permits use in battery-operated applications. The input current IPD, of 100 nA to 100 A, applied to the INPT pin is the collector current of an optimally-scaled NPN transistor, which converts this current to a voltage (its VBE) with a precise logarithmic relationship. A second such converter is used to handle the reference current, IREF, applied to pin IREF. These input nodes are biased slightly above ground (0.5 V). This is generally acceptable for photodiode applications where the anode does not need to be grounded. Similarly, this bias voltage is easily accounted for in generating IREF. The output of the logarithmic front-end is available at pin VLOG. The basic logarithmic slope at this output is nominally 200 mV/decade (10 mV/dB). Thus, a 60-dB range corresponds to an output change of 600mV. When this voltage (or the buffer output) is applied to an ADC that permits an external reference voltage to be employed, the ADL5306's voltage reference output of 2.5 V at pin VREF can be used to improve the scaling accuracy. Suitable ADCs include the AD7810 (serial 10-bit), AD7823 (serial 8-bit) and the AD7813 (parallel, 8/10 bits). Other values of the logarithmic slope can be provided using a simple external resistor network. The logarithmic intercept (also known as the reference current) is nominally positioned at 1 nA by the use of the externally generated current, IREF, of 100 A, provided by a 200 k resistor connected between VREF, at 2.5 V, and the reference input IREF, at 0.5 V. The intercept can be adjusted over a narrow range by varying this resistor. The ADL5306 can also operate in a log-ratio mode, with limited accuracy, where the numerator current applied to INPT and the denominator current applied to IREF. A buffer amplifier is provided for driving a substantial load, for use in raising the basic slope of 10 mV/dB to higher values, as a precision comparator (threshold detector), or in implementing low-pass filters. Its rail-to-rail output stage can swing to within 100 mV of the positive and negative supply rails, and its peak current-sourcing capacity is 25 mA. It is a fundamental aspect of translinear logarithmic converters that the small-signal bandwidth falls as the current level diminishes, and the low-frequency noise-spectral density increases. At the 100 nA level, the bandwidth of the ADL5306 is about 100 kHz, and increases in proportion to IPD up to a maximum value of about 10 MHz. Using the buffer amplifier, the increase in noise level at low currents can be addressed by using it to realize low-pass filters of up to three poles. The ADL5306 is available in a 16 pin LFCSP package and specified for operation from -40C to +85C. US Patents 4,604,532, 5,519,308 and others pending.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Rev. PrC 03/18/03
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 World Wide Web Site: http://www.analog.com (c)Analog Devices, Inc., 2003
Preliminary Technical Data
ADL5306-SPECIFICATIONS
Parameters
INPUT INTERFACE Specified Current Range, IPD Input Current Min/Max Limits Reference Current, IREF, Range Summing Node Voltage Temperature Drift Input Offset Voltage LOGARITHMIC OUTPUT Logarithmic Slope -40C < TA < +85C -40C < TA < +85C Law Conformance Error Wideband Noise2 Small Signal Bandwidth2 Maximum Output Voltage Minimum Output Voltage Output Resistance REFERENCE OUTPUT Voltage wrt Ground Maximum Output Current Incremental Output Resistance OUTPUT BUFFER Input Offset Voltage Input Bias Current Incremental Input Resistance Output Range Incremental Output Resistance Peak Source/Sink Current Small Signal Bandwidth Slew Rate POWER SUPPLY Positive Supply Voltage Quiescent Current Negative Supply Voltage (Optional)
Notes
ADL5306
VP = 5V, VN = 0, TA = 25C, RREF = 200k, unless otherwise noted Min
100n 100n 0.46 -20 190 185 TBD TBD 0.1 0.7 0.7 1.7 0.01 5 2.5 20 2 -20 0.4 35
VP -0.1 0.5
Conditions
Pin 4, INPT, Pin 3, IREF Flows toward INPT pin Flows toward INPT pin Flows toward IREF pin Internally pre-set; may be altered by user -40C < TA < +85C VIN -VSUM , VIREF-VSUM Pin 9, VLOG
Typ
Max
100 10m 100 0.54 20
Units
A A A V mV/C mV mV/dec mV/dec nA nA dB V/Hz MHz V V k V V mA mV A M V mA MHz V/s
0.5 0.015
200
210 215 TBD TBD TBD
Logarithmic Intercept1
1
100 nA < IPD < 100 A IPD > 1 A IPD > 1 A Limited by VN=0 V 4.375 Pin 2, VREF -40C < TA < +85C Sourcing (grounded load) Load current < 10 mA Pin 10, BFIN; pin 11, SCAL; pin 12, VOUT 2.435 2.4
5.625 2.565 2.6
20
Flowing out of pin 10 or 11
RL = 1 k to ground Load current < 10 mA GAIN = 1 0.2V to 4.8V output swing Pins 8, VPOS; pin 6, VNEG ( VP - VN ) 11 V ( VP - VN ) 11 V
50 TBD 15 3 -5.5 5 5.4 0 5.5 6.5
V mA V
1) 2)
Other values of logarithmic intercept can be achieved by adjustment of RREF Output Noise and Incremental Bandwidth are functions of Input Current, measure using output buffer connected for GAIN = 1.
REV. PrC 03/18/2003
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Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS* Supply Voltage VP - VN..........................................12 V Input Current ...................................................20mA Internal Power Dissipation .... ................................ TBD JA .......................................................... 135C/W Maximum Junction Temperature .........................+125C Operating Temperature Range .................-40 C to +85C Storage Temperature Range ..................-65 C to +150C Lead Temperature Range (Soldering 60 sec) .......... +300C
ADL5306
Pin Function Descriptions
Pin 1 2 3 4 Name NC VREF IREF INPT Function N/A Reference output voltage of 2.5 V. Accepts (sinks) reference current, IREF. Accepts (sinks) photodiode current IPD. Usually connected to photodiode anode such that photo-current flows into INPT. Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and IREF node potential. Optional Negative Supply, VN (this pin is usually grounded; for details of usage see APPLICATIONS). Positive Supply, ( VP - VN ) 11V. Output of the logarithmic front-end. Buffer Amplifier non-inverting input. Buffer Amplifier inverting input. Buffer Output. Analog Ground.
5
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VSUM
6,7 8 9 10 11 12 13,14, 15, 16
VNEG VPOS VLOG BFIN SCAL VOUT COMM
C U IO AT N
E S D ( e le c t r o s t a t i c d is c h a r g e ) s e n s it i v e d e v ic e . E lectrostatic cha rg es as hig h as 4000 V readily a c c u m u la t e o n t h e h u m a n b o d y a n d t e s t e q u ip m ent a nd c an discharg e witho ut detec tion. Althoug h t h e A D 8 3 0 5 f e a t u r e s p r o p r ie t a r y E S D p r o t e c t i o n circuitry, pe rm anent da m ag e m ay o ccur on d e v ic e s s u b j e c t e d t o h ig h e n er g y [ > 2 5 0 V H B M ] electrostatic discharg es. T herefore, proper E SD p r e c a u t i o n s a r e r e c o m m e n d e d t o a v o id p e r f o r m ance d eg rad atio n or loss of functionality.
W N A G ESD SENSITIVE DEVICE
ORDERING GUIDE
Model ADL5306ACP ADL5306ACP-REEL7 ADL5306-EVAL Temp. Range -40 C to +85 C Package Description 16-Lead LFCSP 7" Tape and Reel Evaluation Board Package Option CP-16
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Preliminary Technical Data
Typical Performance Characteristics
1.2 1 0.8 TA = -40C, 0C, 25C, 70C, 85C V N = 0V
ADL5306
(VP = 5V, VN = 0V, RREF = 200k, TA = 25C, unless noted)
2 1.5 1
TA = -40C, 0C, 25C, 70C, 85C V N = 0V
Error - dB (10mV/dB)
85C 0.5 0 -0.5 -40C -1 -1.5 0C
70C
V LOG - V
0.6 0.4 0.2 0 1.E-08
-40C 25C 85C 0C 70C
25C
1.E-07
1.E-06 IPD - A
1.E-05
1.E-04
1.E-03
-2 1.E-08
1.E-07
1.E-06 IPD - A
1.E-05
1.E-04
1.E-03
TPC 1. VLOG vs. IPD for Multiple Temperatures
1.4 1.2 1
V LOG - V
TPC 4. Law Conformance Error vs. IPD (at IREF = 10uA) for Multiple Temperatures, Normalized to 25C
2 1.5 1
Error - dB (10mV/dB)
0C 70C 25C 85C -40C
TA = -40C, 0C, 25C, 70C, 85C V N = 0V
TA = -40C, 0C, 25C, 70C, 85C V N = 0V
0.8 0.6 0.4 0.2 0 1.E-08
0.5 0 -0.5 -1 -1.5
70C
85C
25C 0C -40C
1.E-07
1.E-06 IREF - A
1.E-05
1.E-04
1.E-03
-2 1.E-08
1.E-07
1.E-06 IREF - A
1.E-05
1.E-04
1.E-03
TPC 2. VLOG vs. IREF for Multiple Temperatures
1.6 1.4 1.2
TPC 5. Law Conformance Error vs. IREF (at IPD = 10uA) for Multiple Temperatures, Normalized to 25C
0.5 0.4 0.3
Error - dB (10mV/dB)
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 1.E-08 1uA 10uA
100uA
100nA
1
V LOG - V
0.8 0.6 0.4 0.2 0 1.E-08 100n 1u 10uA 100u
1.E-07
1.E-06 IPD - A
1.E-05
1.E-04
1.E-03
1.E-07
1.E-06 IPD - A
1.E-05
1.E-04
1.E-03
TPC 3. VLOG vs. IPD for Multiple Values of IREF (Decade Steps from 10 nA to 1 mA)
TPC 6. Law Conformance Error vs. IPD for Multiple Values of IREF (Decade Steps from 10 nA to 1 mA)
Rev. PrC 03/18/2003
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Preliminary Technical Data
GENERAL STRUCTURE The ADL5306 addresses a wide variety of interfacing conditions to meet the needs of fiber-optic supervisory systems, and will also be useful in many non-optical applications. These notes explain the structure of this unique style of translinear log amp. Figure 1 is a simplified schematic showing the key elements.
ADL5306
typically only 10-17A, and kT/q is the thermal voltage, proportional to absolute temperature (PTAT) and is 25.85mV at 300K. The current IS is never precisely defined, and it exhibits an even stronger temperature dependence, varying by a factor of roughly a billion between -35C and +85C. Thus, to make use of the BJT as an accurate logarithmic element, both of these temperature-dependencies must be eliminated. The difference between the base-emitter voltages of a matched pair of BJTs, one operating at the photodiode current IPD and the second operating at a reference current IREF can be written as VBE1 - VBE2 = kT/q ln(IPD / IS) - kT/q ln(IREF/ IS) = ln(10) kT/q log10(IPD / IREF) (2)
= 59.5mV log10(IPD / IREF) (T = 300K) The uncertain and temperature-dependent saturation current IS which appears in Equation (1) has thus been eliminated. To eliminate the temperature variation of kT/q this difference voltage is processed by what is essentially an analog divider. Effectively, it puts a variable under equation (2). The output of this process, which also involves a conversion from voltage-mode to current-mode, is an intermediate, temperaturecorrected current: ILOG = IY log10(IPD / IREF)
Figure 1:
Simplified Schematic
The photodiode current IPD is received at pin INPT. The voltage at this node is essentially equal to that on the two adjacent guard pins, VSUM and IREF, due to the low offset voltage of the JFET op amp. Transistor Q1 converts the input current IPD to a corresponding logarithmic voltage, as shown in Equation (1). A finite positive value of VSUM is needed to bias the collector of Q1, for the usual case of a single supply voltage. This is internally set to 0.5 V, that is, one fifth of the reference voltage of 2.5 V appearing on pin VREF. The resistance at the VSUM pin is nominally 16 k; this voltage is not intended as a general bias source. The ADL5306 also supports the use of an optional negative supply voltage, VN , at pin VNEG. When VN is -0.5 V or more negative, VSUM may be connected to ground; thus INPT and IREF assume this potential. This allows operation as a voltage-input logarithmic converter by the inclusion of a series resistor at either or both inputs. Note that the resistor setting IREF will need to be adjusted to maintain the intercept value. It should also be noted that the collector-emitter voltages of Q1 and Q2 are now the full VN, and effects due to self-heating will cause errors at large input currents. The input-dependent VBE1 of Q1 is compared with the reference VBE2 of a second transistor, Q2, operating at IREF . This is generated externally, to a recommended value of 10 A. However, other values over a severaldecades range can be used with a slight degradation in law conformance (see TPC1). Theory The base-emitter voltage of a BJT (bipolar junction transistor) can be expressed by the following equation, which immediately shows its basic logarithmic nature: VBE = kT/q ln(IC / IS) (1)
(3)
where IY is an accurate, temperature-stable scaling current which determines the slope of the function (the change in current per decade). For the ADL5306, IY is 44 A, resulting in a temperature-independent slope of 44 A/decade, for all values of IPD and IREF . This current is subsequently converted back to a voltage-mode output, VLOG, scaled 200mV/decade. It is apparent that this output should be zero for IPD = IREF, and would need to swing negative for smaller values of input current. To avoid this, IREF would need to be as small as the smallest value of IPD. However, it is impractical to use such a small reference current as 1 nA. Accordingly, an internal offset voltage is added to VLOG to shift it upward by 0.8 V. This has the effect of moving the intercept to the left by 4 decades, from 10 A to 1 nA: ILOG = IY log10(IPD / IINTC)
(4)
where IINTC is the operational value of the intercept current. Since values of IPD < IINTC result in a negative VLOG, a negative supply of sufficient value is required to accommodate this situation (discussed later). The voltage VLOG is generated by applying ILOG to an internal resistance of 4.55 k, formed by the parallel combination of a 6.69 k resistor to ground and the 14.2 k resistor to the internal 2.5V reference. The output current ILOG generates a voltage at the VLOG pin of
where IC is its collector current, IS is a scaling current,
Rev. PrC 03/18/2003
-5-
Preliminary Technical Data
VLOG = ILOG x 4.55 k = 44 A x 4.55 k x log10 (IPD / IREF) = VY log10 (IPD / IREF)
(5) where VY = 200 mV/decade, or 10 mV/dB. Note that any resistive loading on VLOG will lower this slope, and also result in an overall scaling uncertainty, due to the variability of the on-chip resistors. Consequently, this practice is not recommended. VLOG may also swing below ground when dual supplies (VP and VN) are used. When VN = -0.5V or larger, the input pins INPT and IREF may now be positioned at ground level by simply grounding VSUM. Managing Intercept and Slope As noted above, this introduces an accurate offset voltage of +0.8V at the VLOG pin, equivalent to four decades, resulting in a logarithmic transfer function that can be written as
ADL5306
The ADL5306 is easy to use in optical supervisory systems and in similar situations where a wide-ranging current is to be converted to its logarithmic equivalent, that is, represented in decibel terms. Basic connections for measuring a single current input are shown in Figure 2, which also includes various non-essential components, as will be explained.
Figure 2: Basic Connections for Fixed Intercept Use The 2 V difference in voltage between the VREF and INPT pins in conjunction with the external 200 k resistor RREF provide a reference current IREF of 100 A into pin IREF. The internal reference raises the voltage at VLOG by 0.8V, effectively lowering the intercept current IINTC by a factor of 104 , to position it at 1 nA. Any temperature variation in RREF must be taken into account when estimating the stability of the intercept. Also, the overall noise will increase when using very low values of IREF. In fixed-intercept applications, there is little benefit in using a large reference current, since this only compresses the lowcurrent end of the dynamic range, when operated from a single supply, here shown as 5 V. The capacitor between VSUM and ground is recommended to minimize the noise on this node and help to provide a clean reference current. Since the basic scaling at VLOG is 0.2 V/dec, and thus a swing of 4V at the buffer output would correspond to 20 decades, it will often be useful to raise the slope, to make better use of the rail-to-rail voltage range. For illustrative purposes, the circuit in Figure 2 provides an overall slope of 0.5 V/dec (25 mV/dB). Thus, using IREF = 100 A, VLOG runs from 0.2 V at IPD = 100 nA to 0.8 V at IPD = 100uA while the buffer output runs from 0.5 to 2.0 V, corresponding to a dynamic range of 60 dB (electrical, that is, 30 dB optical power). The optional capacitor from VLOG to ground forms a single-pole low-pass filter in combination with the 4.55-k resistance at this pin. For example, using a CFLT of 10 nF the -3dB corner frequency is 3.2 kHz. Such filtering is useful in minimizing the output noise, particularly when IPD is small. Multi-pole filters are more effective in reducing the total noise; examples are provided in the AD8304 Data Sheet. The dynamic response of this overall input system is influenced by the external RC networks connected from the two inputs (INPT, IREF) to ground. These
VLOG = VY log10 (104 x IPD / IREF ) = VY log10 (IPD / IINTC )
where IINTC = IREF/10 . Thus, the effective intercept current IINTC is only one ten-thousandth of IREF, corresponding to 10 nA when using the recommended value of IREF = 100 A. The slope can be reduced by attaching a resistor to the VLOG pin. This is strongly discouraged, in view of the fact that the on-chip resistors will not ratio correctly to the added resistance. Also, it is rare that one would wish to lower the basic slope of 10 mV/dB, and if this is needed, it should be effected at the low-impedance output of the buffer, which is provided to avoid such miscalibration and also allow higher slopes to be used. The ADL5306 buffer is essentially an uncommitted op- amp with rail-to-rail output swing, good loaddriving capabilities and a unity-gain bandwidth of >20 MHz. In addition to allowing the introduction of gain, using standard feedback networks, and thereby increase the slope voltage, VY, the buffer can be used to implement multi-pole low-pass filters, threshold detectors, and a variety of other functions. Further details of these can be found in the Data Sheet for the AD8304. Response Time and Noise Considerations The response time and output noise of the ADL5306 are fundamentally a function of the signal current IPD. For small currents the bandwidth is proportional to IPD. The output low-frequency voltage-noise spectraldensity is a function of IPD and also increases for small values of IREF. Details of the noise and bandwidth performance of translinear log amps can be found in the AD8304 Data Sheet. APPLICATIONS
Rev. PrC 03/18/2003
4
(6)
-6-
Preliminary Technical Data
are required to stabilize the input systems over the full current range. The bandwidth changes with the input current due to the widely varying pole frequency. The RC network adds a zero to the input system to ensure stability over the full range of input current levels. The network values shown in Figure 2 will usually suffice, but some experimentation may be necessary when the photodiode capacitance is high. Although the two current inputs are similar, some care is needed to operate the reference input at extremes of current (<100nA) and temperature (<0C). Modifying the RC network to 4.7nF and 2k will allow operation to -40C at 10nA. By inspecting the transient response to perturbations in IREF at representative current levels, the capacitor value can be adjusted to provide fast rise and fall times with acceptable settling. To fine tune the network zero, the resistor value should be adjusted. USING A NEGATIVE SUPPLY Most applications of the ADL5306 will require only a single supply of 3.0 V to 5.5 V. However, to provide further versatility, dual supplies may be employed, as illustrated in Figure 4.
ADL5306
The use of a negative supply, VN, allows the summing node to be placed at ground level whenever the input transistor (Q1 in Figure 1) has a sufficiently negative bias on its emitter. When VN = -0.5 V, the VCE of Q1 and Q2 will be the same as for the default case when VSUM is grounded. This bias need not be accurate, and a poorly defined source can be used. The source does however need to be able to support the quiescent current as well as the INPT and IREF signal current. For example, it may be convenient to utilize a forward-biased junction voltage of about 0.7V or a Schottky barrier voltage of a little over 0.5 V. With the summing node at ground, the ADL5306 may now be used as a voltage-input log amp, at either the numerator input INPT or the denominator input IREF by inserting a suitably scaled resistor from the voltage source to the relevant pin. The overall accuracy for small input voltages is limited by the voltage offset at the inputs of the JFET op amps. The use of a negative supply also allows the output to swing below ground, thereby allowing the intercept to correspond to a midrange value of IPD. However, the voltage VLOG remains referenced to the ACOM pin, and while it does not swing negative for default operating conditions, it is free to do so. Thus, adding a resistor from VLOG to the negative supply lowers all values of VLOG, which raises the intercept. The disadvantage of this method is that the slope is reduced by the shunting of the external resistor, and the poorly-defined ratio of on-chip and off-chip resistances causes errors in both the slope and the intercept. A more accurate method for repositioning the intercept is described below.
Figure 4: Negative Supply Application
Rev. PrC 03/18/2003
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Preliminary Technical Data
OUTLINE DIMENSIONS
ADL5306
Rev. PrC 03/18/2003
-8-

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