View AD10677_973715.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

16-Bit, 65 MSPS A/D Converter AD10677
PERFORMANCE FEATURES 65 MSPS Sample Rate 80 dBFS Signal-to-Noise Ratio Transformer Coupled Analog Input Single PECL Clock Source Digital Outputs True Binary Format 3.3 V and 5 V CMOS Compatible APPLICATIONS Low Signature Radar Medical Imaging Communications Instrumentation Instrumentation Antenna Array Processing
ANALOG POWER AGND +5VA +3.3VE AGND
FUNCTIONAL BLOCK DIAGRAM
AIN
AD10677
AIN ADC 14 DOUT 0 ADC 14 DIGITAL POSTPROCESSING DOUT 15 ADC 14
ADC
14
OUTPUT DATA BITS
CLOCK DISTRIBUTION CIRCUIT DGND +3.3V DGND ENCODE ENCODE DIGITAL POWER
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD10677 is a 16-bit, high performance, analog-to-digital converter for applications that demand increased SNR levels. Exceptional noise performance and a typical signal-to-noise ratio of 80 dB is obtained by digitally post processing the outputs of four ADCs. Only a single analog input and PECL sampling clock are required as well as 3.3 V and 5 V power supplies. The AD10677 is assembled using a 0.062" thick laminate board with three sets of connector interface pads to accommodate analog and digital isolation. Analog Devices recommends using the following connector from Samtec: FSI-110-03-G-D-AD-K-TR. The overall card fits a 2.2" 2.8" PCB specified from 0C to 70C.
1. Guaranteed sample rate of 65 MSPS 2. Input signal conditioning with optimized noise performance 3. Fully tested and guaranteed performance
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
AD10677-SPECIFICATIONS
DC SPECIFICATIONS
Parameter RESOLUTION Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error POWER SUPPLY REJECTION (PSRR) ANALOG INPUTS (AIN, AIN)1 Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance Input Bandwidth VSWR2 POWER SUPPLY3 Supply Current IAVCC (AVCC = 5.0 V) IEVCC (EVCC = 3.3 V) IVDD (VDD = 3.3 V) Total Power Dissipation4
(AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V; TA = 25 C, Differential Encode = 65 MSPS, CLOAD 10 pF, unless otherwise noted.)
Test Level I I V V V V V V V V IV V Min -0.30 -7 Typ +0.12 0.7 4 13 200 60 2.15 50 19 0.40 1.04:1 210 Max +0.30 +7 Unit %FS %FS LSB LSB ppm/C ppm/C dB V p-p pF MHz Ratio
I I I I
0.95 0.15 0.49 6.86
1.05 0.2 0.625 7.5
A A A W
NOTES 1 Measurement includes the recommended interface connector. 2 Input VSWR, see TPC 6. 3 Supply voltages should remain stable within 5% for normal operation. However, rated ac (harmonics) performance is valid only over the range AV CC = 5.0 V to 5.25 V. 4 Power dissipation measures with encode at rated speed and -1 dBFS analog input at midband. Specifications subject to change without notice.
DIGITAL SPECIFICATIONS unless otherwise noted.)
Parameter ENCODE INPUTS (ENCODE, ENCODE) Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance LOGIC OUTPUTS (D15-D0) Logic Compatibility Logic 1 Voltage--ILOAD 100 mA Logic 0 Voltage--ILOAD 100 mA Output Coding Series Output Resistance--per bit
Specifications subject to change without notice.
(AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V; TA = 25 C, Differential Encode = 65 MSPS, CLOAD 10 pF,
Test Level IV V V Min 0.4 100 160 CMOS 0.9 VDD 0.4 True Binary 120 Typ Max Unit V p-p pF
IV IV
V V
SWITCHING SPECIFICATIONS
Parameter Maximum Conversion Rate Minimum Conversion Rate Duty Cycle
Specifications subject to change without notice.
(AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V; TA = 25 C, Differential Encode = 65 MSPS, CLOAD 10 pF, unless otherwise noted.)
Test Level I IV IV Min 65 40 15 60 Typ Max Unit MSPS MSPS %
-2-
REV. 0
AD10677 AC SPECIFICATIONS
Parameter SNR Analog Input @ -1 dBFS SINAD2 Analog Input @ -1 dBFS
1
(AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V; TA = 25 C, Differential Encode = 65 MSPS, CLOAD 10 pF, unless otherwise noted.)
Test Level Min 77.5 77.5 76.5 77.2 77.2 74.5 84 84 79.5 Typ 80 80 78.5 79 79 77 92 92 84 Max Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
2.5 MHz 10 MHz 30 MHz 2.5 MHz 10 MHz 30 MHz
I I I I I I I I I
SPURIOUS FREE DYNAMIC RANGE (SFDR)3 Analog Input 2.5 MHz @ -1 dBFS 10 MHz 30 MHz TWO-TONE4 Analog Input @ -7 dBFS--IMD f1 = 10 MHz f2 = 12 MHz
V
96
dBFS
NOTES 1 Analog Input signal power at -1 dBFS; signal-to-noise (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 65 MSPS. SNR is reported in dBFS, related back to converter full scale. 2 Analog Input signal power at -1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS. SINAD is reported in dBFS, related back to converter full scale. 3 Analog Input signal equal -1 dBFS; SFDR is ratio of converter full scale to worst spur. 4 Both input tones at -7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third-order intermod product. Specifications subject to change without notice.
SWITCHING SPECIFICATIONS unless otherwise noted.)
Parameter ENCODE INPUTS PARAMETERS Encode Period @ 65 MSPS--tENC Encode Pulsewidth High @ 65 MSPS--tENCH Encode Pulsewidth Low @ 65 MSPS--tENCL ENCODE/DATA (D15:0) Propagation Delay--tPDH Valid Time--tPDL APERTURE DELAY--tA APERTURE UNCERTAINTY (JITTER)--tJ PIPELINE DELAYS
Specifications subject to change without notice.
(AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V; TA = 25 C, Differential Encode = 65 MSPS, CLOAD 10 pF,
Test Level V V V Min Typ 15.4 7.7 7.7 6.7 7.3 V V V 480 500 9 Max Unit ns ns ns ns ns ps ps rms Cycles
REV. 0
-3-
AD10677
ABSOLUTE MAXIMUM RATINGS* Table I. Output Coding (True Binary)
AVCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +7 V EVCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +6 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +3.8 V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 0 V to AVCC Analog Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Encode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 0 V to 5 V Digital Output Voltage . . . . . . . . . . . . . . . . . . . -0.5 V to VDD Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C Storage Temperature Range Ambient . . . . . . -65C to +150C Maximum Operating Temperature Ambient . . . . . . . . . . 92C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Code 65535 . . . 32768 32767 . . . 0
AIN (V) +1.1 . . . 0 -0.000034 . . . -1.1
Digital Output 1111 1111 1111 1110 . . . 1000 0000 0000 0000 0111 1111 1111 1111 . . . 0000 0000 0000 0000
ORDERING GUIDE
Model
OPERATING RANGE*
Temperature Range 0C to 70C (Ambient) 25C
Package Option 2.2" 2.8" Evaluation Board
Operating Ambient Temperature Range . . . . . . . . 0C to 70C
*See Thermal Considerations section
AD10677BWS AD10677/PCB
EXPLANATION OF TEST LEVELS
100% production tested 100% production tested at 25C and sample tested at specified temperatures III Sample tested only IV Parameter is guaranteed by design and characterization testing V Parameter is a typical value only VI 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices
I II
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD10677 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
-4-
REV. 0
AD10677 Test Circuits
t0
N N+1 N+2 N+3 N+4 N+5 N+6
ANALOG INPUT
tENC
ENCODE, ENCODE
tENCL
N+1
tENCH
N+2 N+3 N+4 N+5 N+6
N
tPDH
DATA BITS, D[15:0]
tPDL
N-7 N-6 N-5 N-4
N-9
N-8
Figure 1. Timing Diagram
VCH
AVCC
BUF 1:1 AIN 200 AIN 25 500 VCH 25 4 AVCC 500 BUF VCL 500 BUF
T/H
VREF
T/H
VCL
Figure 2. Analog Input Stage
EVCC
VDD VDD P
37.5k ENC 100 ENC PECL DRIVER
MACROCELL LOGIC N 120 D0-D15
Figure 3. Equivalent Encode Input
Figure 4. Digital Output Stage
REV. 0
-5-
AD10677
INTERFACES 1 AND 2: DIGITAL PIN FUNCTION DESCRIPTIONS
P1: Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Name DGND DGND Dout15 NC Dout14 DGND Dout13 NC Dout12 DGND Dout11 NC Dout10 DGND Dout9 NC Dout8 DGND DGND NC
Function Digital Ground Digital Ground Data Bit Output No Connection Data Bit Output Digital Ground Data Bit Output No Connection Data Bit Output Digital Ground Data Bit Output No Connection Data Bit Output Digital Ground Data Bit Output No Connection Data Bit Output Digital Ground Digital Ground No Connection
P2: Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Name DGND DGND +3.3VD Dout0 +3.3VD Dout1 +3.3VD Dout2 DGND Dout3 DGND Dout4 DGND Dout5 DGND Dout6 +3.3VD Dout7 +3.3VD DGND
Function Digital Ground Digital Ground Digital Voltage Data Bit Output Digital Voltage Data Bit Output Digital Voltage Data Bit Output Digital Ground Data Bit Output Digital Ground Data Bit Output Digital Ground Data Bit Output Digital Ground Data Bit Output Digital Voltage Data Bit Output Digital Voltage Digital Ground
INTERFACE 3: ANALOG PIN FUNCTION DESCRIPTIONS
P3: Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Name +3.3VE +5.0VA +3.3VE +5.0VA AGND +5.0VA AGND +5.0VA AGND AGND AGND AIN AGND AIN ENCODE AGND ENCODE AGND AGND AGND
Function Encode Voltage Analog Voltage Encode Voltage Analog Voltage Analog Ground Analog Voltage Analog Ground Analog Voltage Analog Ground Analog Ground Analog Ground Analog Input Analog Ground Analog Input Encode Input Analog Ground Encode Input Analog Ground Analog Ground Analog Ground
-6-
REV. 0
AD10677
TOP VIEW OF INTERFACE PCB ASSEMBLY
Dimensions shown in inches Tolerances: 0.xx = 10 mils 0.xxx = 5 mils
0.466
P2 MH4
0.960 0.888 P3 MH2 2.148
1.223 1.693 0.433
0.925 0.805 MH1 0.526 MH3 0.900
P1
0.955
0.757
INTERFACE NOTES: SUGGESTED INTERFACE MANUFACTURER: SAMTEC INTERFACE PART NUMBERS FOR P1-P3: FSI-110-03-G-D-AD-K-TR (20-PIN) HOLES 1-4 ACCOMMODATE 2-56 THREADED HARDWARE. USE FOUR 2-56 NUTS FOR SECURING THE PART TO INTERFACE PCB. MANUFACTURER: BUILDING FASTENERS PART NUMBER: HNSS256 DIGIKEY #: H723-ND
Figure 5. Header Interface Dimensions (Inches)
REV. 0
-7-
AD10677-Typical Performance Characteristics
0 -10 -20 -30 -40 -50 ENCODE = 65MSPS AIN = 2.3MHz SNR = 80.1dBFS SFDR = 96.16dBFS 0 -10 -20 -30 -40 -50 ENCODE = 65MSPS AIN = 10.1MHz AND 12.1MHz IMD = 97.03dBFS
dBFS
-70 -80 -90
dBFS
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 FREQUENCY - MHz
-60
-60 -70 -80 -90
-100 -110 -120 -130
-100 -110 -120 -130 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 FREQUENCY - MHz
TPC 1. Single-Tone at 2.5 MHz
0 -10 -20 -30 -40 -50 ENCODE = 65MSPS AIN = 10.1MHz SNR = 80.22dBFS SFDR = 94.3dBFS
TPC 4. Two-Tone @ 10.1 MHz and 12.3 MHz
0 -0.2 -0.4 AIN = -1dBFS -0.6 -0.8
dBFS
dBFS
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 FREQUENCY - MHz
-60 -70 -80 -90
-1.0 -1.2 -1.4 -1.6 -1.8 -2.0 1.0 10.9 20.8 30.7 40.6 50.5 60.4 70.3 80.2 90.1 100.0
-100 -110 -120 -130
FREQUENCY - MHz
TPC 2. Single-Tone at 10 MHz
0 -10 -20 -30 -40 -50 ENCODE = 65MSPS AIN = 31.7MHz SNR = 78.95dBFS SFDR = 85.5dBFS 2.0 1.9 1.8 1.7 1.6 VSWR 1.5 1.4 1.3 1.2 1.1 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 FREQUENCY - MHz 1.0 0.1
TPC 5. Gain Flatness
dBFS
-60 -70 -80 -90
-100 -110 -120 -130
1.0
10.0 FREQUENCY - MHz
100.0
1000.0
TPC 3. Single-Tone at 32 MHz
TPC 6. Analog Input VSWR
-8-
REV. 0
AD10677
100 90 80 70 60 SFDR 2.5MHz 96 94 92 90 SNR 30MHz 88
dBc
50 SFDR 10MHz 40 30 20 10 SNR 10MHz 0 -80 -70 -60 -50 -40 -30 -20 -10 0 SNR 2.5MHz
dBc
SFDR 30MHz
86 84 82 80 78 76 0 5 10 15 20 25 SNR
SFDR
30
35
FUNDAMENTAL LEVEL - dBFS
ANALOG INPUT FREQUENCY - MHz
TPC 7. SFDR and SNR vs. Analog Input Level
TPC 8. SFDR and SNR vs. Analog Input Frequency
REV. 0
-9-
11/11/02 10:15 AM AKOS
AD10677
DEFINITION OF SPECIFICATIONS Analog Bandwidth Two-Tone Intermodulation Distortion Rejection
The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.
Aperture Delay
The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBc.
Voltage Standing-Wave Ratio (VSWR)
The ratio of the amplitude of the elective field at a voltage maximum to that at an adjacent voltage minimum.
THERMAL CONSIDERATIONS
The delay between the 50% point on the rising edge of the ENCODE command and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
Due to the high power nature of the part, it is critical that the following thermal conditions be met for the part to perform to data sheet specifications. This also ensures that the maximum junction temperature (150C) is not exceeded. * Operation temperature (tA) must be within 0 to 70C. * All mounting standoffs should be fastened to the interface PCB assembly with 2-56 nuts. This ensures good thermal paths as well as excellent ground points. * The unit rises to ~72C (tC) on the heat sink in still air (0 linear feet per minute (LFM)). 100 linear feet per minute (LFM) in either direction across the heat sink is the minimum recommended air flow. See Figure 6.
75 70
The deviation of any code from an ideal 1 LSB step.
Integral Nonlinearity
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specifications define an acceptable Encode duty cycle.
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the worst harmonic component.
Minimum Conversion Rate
TEMPERATURE (CASE) - C
65 60 55 50 45 40 35 30 0 50 100 150 AIR FLOW - LFM 200 250 300
The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% point of the rising edge of the ENCODE command and the time when all output data bits are within valid logic levels.
Power Supply Rejection Ratio
Figure 6. Temperature (Case) vs. Air Flow (Ambient)
The ratio of a change in output offset voltage to a change in power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. May be reported in dBc (i.e., degrades as signal levels is lowered) or in dBFS (always related back to converter full scale).
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. May be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale).
Spurious-Free Dynamic Range
The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale).
-10-
REV. 0
AD10677
THEORY OF OPERATION
The AD10677 employs four parallel high speed analog-todigital converters in a correlation technique, which improves the dynamic range of the ADCs. The technique consists of summing the parallel outputs of the four converters to reduce the uncorrelated noise introduced by the individual converters. Signals processed through the high speed adder are correlated and summed coherently. Noise is not correlated and sums on an rms basis. The four high speed analog-to-digital converters employ three-stage subrange architecture. The AD10677 provides complementary analog input pins, AIN and AIN. Each analog input is centered around 2.4 V and should swing 0.55 V around the reference. Since AIN and AIN are 180 degrees out of phase, the differential analog input signal is 2.15 V p-p. The analog input is designed to meet a 50 input impedance for ease of interface to commercially available cables, filters, and drivers, among others. The AD10677 encode inputs are ac-coupled to a PECL differential receiver/driver. The output of the receiver/driver provides a clock source for a 1:5 PECL Clock driver and a PECL to TTL translator. The 1:5 PECL Clock driver provides the differential encode signal for each the four high speed analog-to-digital converters. The PECL to TTL translator is used to provide a clock source for the Complex Programmable Logic Device (CPLD). The digital outputs from the four ADCs drive 120 series output terminators and are applied to the CPLD for post processing. The digital outputs are added together in the Complex Programmable Logic Device through a ripple-carry adder, which provides the 16-bit data output. The AD10677 provides valid data following nine pipeline delays. The result is a 16-bit parallel digital CMOS compatible word coded as true binary.
INPUT STAGE
that can flow into the output stage. To minimize capacitive loading there should only be one gate on each of the output pins. A typical CMOS gate combined with the PCB trace has a load of approximately 10 pF. It should be noted that extra capacitive loading increases output timing and invalidate timing specifications. Digital output timing is guaranteed with 10 pF.
ANALOG AND DIGITAL POWER SUPPLIES
Care must be taken when selecting a power source. Linear supplies are recommended. Switching supplies tend to have radiated components that may be coupled into the ADCs. The AD10677 features separate analog and digital supply and ground currents, helping to minimize digital corruption of sensitive analog signals. The 3.3 V supply provides power for the output section of the ADCs, the CPLD, and the clock circuit. The +3.3VE supply provides power to the clock distribution circuit. The +3.3VD supply provides power to digital output section of the ADCs, the PCEL to TTL translator, and the CPLD. Separate +3.3VE and +3.3VD supplies are utilized to prevent modulation of the clock signal with digital noise. The 5 V supply provides power to the analog sections of the ADCs. Decoupling capacitors are strategically placed throughout the circuit to provide low impedance noise shunts to ground. The +5VA supply (analog power) should be decoupled to AGND (analog ground) and +3.3VD (digital power) should be decoupled to DGND (digital ground). The +3.3VE supply (analog power) should be decoupled to AGND. The evaluation board schematic and layout data provide a typical PCB implementation of the AD10667.
ANALOG AND DIGITAL GROUNDING
The user is provided with a single to differential transformer coupled input. The input impedance is 50 and requires a 2.15 V p-p input level to achieve full scale.
ENCODING THE AD10677
The AD10677 encode signal must be a high quality, low phase noise source to prevent performance degradation. The clock input must be treated as an analog input signal as aperture jitter may affect dynamic performance. For optimum performance, the AD10677 must be clocked differentially.
OUTPUT LOADING
Care should be taken when designing the data receivers for the AD10677. The Complex Programmable Logic Device 16-bit outputs drive 120 series resistors to limit the amount of current
While the AD10677 provides separate analog and digital ground pins, the device should be treated as an analog component. Proper grounding is essential in high speed, high resolution systems. Multilayer printed circuit boards are recommended to provide optimal grounding and power distribution. The use of power and ground planes provides distinct advantages. Power and ground planes minimize the loop area encompassed by a signal and its return path, minimize the impedance associated with power and ground paths, and provide a distributed capacitor formed by the power plane printed circuit board material and ground plane. The AD10677 unit is provided with four metal standoffs (see Figure 5). MH2 is located in the center of the unit and MH1 is located directly below analog header P3. Both of these standoffs are tied to analog ground and should be connected accordingly on the next level assembly for optimum performance. The two stand-offs located near P1 and P2 (MH3 and MH4) are tied to digital ground and should be connected accordingly on the next level assembly.
REV. 0
-11-
AD10677
OTHER NOTES
The circuit is configured on a 2.2" 2.8" laminate board with three sets of connector interface pads. The pads are configured in such a way that easy "keying" is provided to the user. The pads are made for low profile applications and have a total height of 0.12" after mating. The part numbers for the header mates are provided in Figure 5. All pins of the analog and digital sections are described in the Pin Function Description tables.
EVALUATION BOARD
5 V power supply. The clock source is buffered on the board to provide the clock for the AD10677, a latch, and a data ready signal. The ADC digital outputs are latched on board by a 74LCX16374. The digital outputs and output clock are available on a 40-pin connector J1. Power is supplied to the board via uninsulated metal banana jacks. The analog input is connected via an SMA connector AIN. The analog input section provides for a single-ended input option or a differential input option. The board is shipped in a single-ended analog input option. Removing a ground tie at E17 converts the circuit to a differential analog input configuration.
The AD10677 evaluation board provides an easy way to test the 16-bit 65 MSPS A/D converter. The board requires a clock source, an analog input signal, two 3.3 V power supplies, and a
PCB BILL OF MATERIAL
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Quantity Reference Designator 1 1 3 3 6 2 1 1 19 1 4 17 6 4 1 1 J1 U1 L1-L3 J11-J13 P1, P2, P8-P10, P12 U5, U6 U7 R24 R0-R16, R20, R23 R17 R18, R19, R21, R22 C1, C10-C13, C16-C18, C23-C26, C29-C32 C8, C9, C4, C15, C27, C33 J2, J3, J5, J6 A1 AD106xx Evaluation Board
Description Connector, 40-position Header, Male Straight IC, LV 16-Bit D-Type Flip-Flop w/5 V Tolerant IO Common-Mode Surface-Mount Ferrite Bead 20 Connector, 1 mm Single Element Interface Uninsulated BANANA JACK All Metal IC, 3.3 V/5 V ECL Differential Receiver/Driver IC, 3.3 V Dual Differential LVPECL to LVTTL Translator RES 0.0 1/10 W 5% 0805 SMD RES 51.1 1/10 W 1% 0805 SMD RES 18.2 k 1/10 W 1% 0805 SMD RES 100 1/10 W 1% 0805 SMD CAP 0.1 F 16 V CERAMIC X7R 0805 CAP 10 F 10 V CERAMIC Y5V 1206 CONNECTOR, SMA JACK 200 Mil STR GOLD ASSEMBLY, AD10677BWS GS04483 (PCB)
-12-
REV. 0
19 17 15 13 11 9 7 5 3 1
AD10677 PART OUTLINE
MH1-4 = DUT MOUNTING HOLES
20 18 16 14 12 10 8 6 4 2
19 17 15 13 11 9 7 5 3 1
J11
20 18 16 14 12 10 8 6 4 2
+3.3VE DGND DGND
FSI-110-03-G-D-AD-TR
J5 ENCODE
19 17 15 13 11 9 7 5 3 1
R20 51.1
J12
R19 100 AGND
AGND AGND SINGLE ENDED DIFFERENTIAL INPUT OPTION INPUT OPTION MH3
19 17 15 13 11 9 7 5 3 1
+3.3VE
DGND
1 2 3 4
R21 R22 100 100 MC100ELT23D DRY
R28 DNI R31 DNI
AGND AGND AGND
DGND
DGND
POWER CONNECTIONS
+3.3VD
BYPASS CAPACITORS
+3.3VE
HEADER 732mm
DGND
1 3 5 7 9 11 13
Figure 7. Evaluation Board Schematic
AGND FSI-110-03-G-D-AD-TR E17 J3 AGND MH1 DGND
20 18 16 14 12 10 8 6 4 2 20 18 16 14 12 10 8 6 4 2
MC10EL16D
D0 D0 D1 D1 VCC Q0 Q1 GND
8 7 6 5
R24 0.0 BUFMEM
J8
1 2 3 4
NC VCC D Q D Q VBB VEE
8 7 6 5
R30 DNI LATCH C17 0.1 F 16V
R23 51.1
2 4 6 8 10 12 14
U7
R29 DNI
R17 18.2k +3.3VD DGND +3.3VD
U6
DRY
DGND
SI-110-03-G-D-AD-TR
REV. 0
+3.3VD DGND C33 10 F 10V C31 0.1 F 16V DGND BUFMEM LATCH R30 DNI U1 +3.3VD R25 DNI J1 MH4 +5VA DGND C30 0.1 F 16V J13 AGND AGND MH2 R27 DNI AGND J2 E15 ANALOG INPUT C14 10 F 10V C15 10 F 10V
VCC VCC VCC VCC O15 O14 O13 O12 O11 O10 O9 O8 42 31 7 18 23 22 20 19 17 16 14 13 R0 51.1 R1 51.1 R2 51.1 R3 51.1 R4 51.1 R5 51.1 R6 51.1 R7 51.1
C32 0.1 F 16V
+3.3VE
J6 ENCODE C12 0.1 F 16V
C10 0.1 F 16V
U5
C11 0.1 F 16V AGND
R16 51.1
1 2 3 4
NC VCC 8 Q7 D 6 Q D VBB VEE 5
1 3 5 7 9 11 13 15 17 19 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20
2 4 6 8 10 12 14 16 18 20
MC10EL16D
R8 51.1 R9 51.1 R10 51.1 R11 51.1 R12 51.1 R13 51.1 R14 51.1 R15 51.1 O7 O6 O5 O4 O3 O2 O1 O0 GND GND GND GND
AGND
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 12 11 9 8 6 5 3 2 21 15 10 4
C13 0.1 F 16V
R18 100
25 24 26 27 29 30 32 33 35 36 48 1 37 38 40 41 43 44 46 47 28 34 39 45 CP2 OE2 I15 I14 I13 I12 I11 I10 I9 I8 CP1 OE1 I7 I6 I5 I4 I3 I2 I1 I0 GND GND GND GND
+3.3VD
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
40-PIN HMS 74LCX16374MTD E7 E8 C1 0.1 F 16V DGND DGND DGND DGND
AGND
-13-
C26 0.1 F 16V C16 0.1 F 16V C18 0.1 F 16V C29 0.1 F 16V DGND C23 0.1 F 16V C28 0.1 F 16V
AGND
POWER CONNECTIONS
L3 P10 +3.3VE P1 AGND
1 3 2 4
P10
L1
+3.3VE
+3.3VD
+3.3VE
1 3
2 4
P1
AGND
C9 10 F 10V
C27 10 F 10V AGND DGND DGND
C24 0.1 F 16V
AGND
AGND
P9
L2
+5VA E2 C25 0.1 F 16V
OPTIONAL EVALUATION BOARD GROUND TIES
E6 E10 E12 E18 E19 E21 E4 E3 E20 E22 E13 E1 E5 E9 E11
+5VA
1 3
2 4
P2
AD10677
AGND
C8 10 F 10V
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
AD10677
AD10677/PCP EVALUATION BOARD
Figure 8a. Evaluation Board Mechanical Layout Top View
-14-
REV. 0
AD10677
Figure 8b. Evaluation Board Mechanical Layout Bottom View
REV. 0
-15-
AD10677
Figure 8c. Evaluation Board Top Layer Copper
Figure 8d. Evaluation Board Second Layer Copper
-16-
REV. 0
AD10677
Figure 8e. Evaluation Board Third Layer Copper
Figure 8f. Evaluation Board Bottom Layer Copper
REV. 0
-17-
AD10677
OUTLINE DIMENSIONS
Dimensions shown in millimeters
Tolerances: 0.xx = 10 mils 0.xxx = 5 mils
Bottom View
2.795 2.745 2.695 0.170 0.120 0.070
2.220 2.170 2.120
a
0.370 0.320 0.270
0.314 0.264 0.214
Top View
-18-
REV. 0
-19-
-20-
C03208-0-11/02(0)
PRINTED IN U.S.A.

▲Up To Search▲

Price & Availability of AD10677

	To Download AD10677 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .