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| STD60NH03L N-CHANNEL 30V - 0.0075 - 60A - DPAK STripFETTM III POWER MOSFET PRELIMINARY DATA TYPE STD60NH03L s s s s s s s VDSS 30 V RDS(on) < 0.009 ID 60 A TYPICAL RDS(on) = 0.0075 @ 10 V TYPICAL RDS(on) = 0.009 @ 5 V RDS(ON) * Qg INDUSTRY's BENCHMARK CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED LOW THRESHOLD DEVICE SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX "T4") 3 1 DPAK TO-252 (Suffix "T4") DESCRIPTION The STD60NH03L utilizes the latest advanced design rules of ST's proprietary STripFETTM technology. This is suitable for the most demanding DC-DC converter application where high efficiency is to be achieved. INTERNAL SCHEMATIC DIAGRAM s APPLICATIONS SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY DC/DC CONVERTERS ORDERING INFORMATION SALES TYPE STD60NH03LT4 MARKING D60NH03L PACKAGE DPAK PACKAGING TAPE & REEL July 2003 1/8 STD60NH03L ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM (1) PTOT EAS (2) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 30 30 20 60 43 240 70 0.47 300 -55 to 175 Unit V V V A A A W W/C mJ C C THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature for Soldering Purpose 2.14 100 275 C/W C/W C ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20 V VDS = VGS, ID = 250A VGS = 10 V, ID = 30 A VGS = 5 V, ID =30 A 1 0.0075 0.009 0.009 0.017 Min. 30 1 10 100 Typ. Max. Unit V A A nA 2/8 STD60NH03L ELECTRICAL CHARACTERISTICS (CONTINUED) DYNAMIC Symbol gfs (3) Ciss Coss Crss RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain Test Conditions VDS = 15 V , ID = 30 A VDS = 10V, f = 1 MHz, VGS = 0 Min. Typ. TBD 2200 380 49 1.5 Max. Unit S pF pF pF SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Qgls (4) Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Third-Quadrant Gate Charge Test Conditions VDD = 15 V, ID = 30 A RG = 4.7 VGS = 5 V (see test circuit, Figure 3) VDD = 15 V, ID = 60 A, VGS = 5 V VDS < 0 V, VGS = 5 V, ID = 60 A Min. Typ. 21 95 15.7 8.3 3.4 15 21 Max. Unit ns ns nC nC nC nC SWITCHING OFF Symbol td(off) tf Parameter Turn-off-Delay Time Fall Time Test Conditions VDD = 15 V, ID = 30 A, RG = 4.7 , VGS = 5 V (see test circuit, Figure 3) Min. Typ. 19 15 Max. Unit ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (1) VSD (3) trr Qrr IRRM 1. 2. 3. 4. Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Test Conditions Min. Typ. Max. 60 240 Unit A A V ns nC A ISD = 30 A, VGS = 0 ISD = 60 A, di/dt = 100A/s, VDD = 20 V, Tj = 150C (see test circuit, Figure 5) 32 51 3.2 1.3 Pulse width limited by safe operating area Starting Tj = 25C, ID = 30A, VDD = 20V Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. Gate charge for Syncronous Operation. See Appendix A 3/8 STD60NH03L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/8 STD60NH03L TO-252 (DPAK) MECHANICAL DATA mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 V2 0.60 0 o DIM. 2.20 0.90 0.03 0.64 5.20 0.45 0.48 6.00 6.40 4.40 9.35 inch MAX. 2.40 1.10 0.23 0.90 5.40 0.60 0.60 6.20 6.60 4.60 10.10 MIN. 0.087 0.035 0.001 0.025 0.204 0.018 0.019 0.236 0.252 0.173 0.368 0.031 1.00 8 o TYP. TYP. MAX. 0.094 0.043 0.009 0.035 0.213 0.024 0.024 0.244 0.260 0.181 0.398 0.8 0.024 0 o 0.039 0o P032P_B 5/8 STD60NH03L DPAK FOOTPRINT TUBE SHIPMENT (no suffix)* All dimensions are in millimeters All dimensions are in millimeters TAPE AND REEL SHIPMENT (suffix "T4")* REEL MECHANICAL DATA DIM. A B C D G N T 1.5 12.8 20.2 16.4 50 22.4 18.4 13.2 mm MIN. MAX. 330 0.059 0.504 0.520 0.795 0.645 0.724 1.968 0.881 BULK QTY 2500 inch MIN. MAX. 12.992 TAPE MECHANICAL DATA DIM. A0 B0 B1 D D1 E F K0 P0 P1 P2 R W BASE QTY 2500 mm MIN. 6.8 10.4 1.5 1.5 1.65 7.4 2.55 3.9 7.9 1.9 40 15.7 16.3 inch MIN. MAX. 7 0.267 0.275 0.409 0.417 0.476 0.059 0.063 0.059 0.065 0.073 0.291 0.299 0.100 0.108 0.153 0.161 0.311 0.319 0.075 0.082 1.574 0.618 0.641 MAX. 10.6 12.1 1.6 1.85 7.6 2.75 4.1 8.1 2.1 * on sales type 6/8 STD60NH03L Appendix A: Buck Converter Power Losses Estimation DESCRIPTION The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. The low side (SW2) device requires: - Very low RDS(on) to reduce conduction losses - Small Qgls to reduce the gate charge losses - Small Coss to reduce losses due to output capaci tance - Small Qrr to reduce losses on SW1 during its turn-on - The Cgd/C gs ratio lower than Vth /VGG ratio especially with low drain to source voltage to avoid the cross conduction phenomenon The high side (SW1) device requires: - Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate - Small Qg to have a faster commutation and to reduce gate charge losses - Low RDS(on) to reduce the conduction losses High Side Switch (SW1) Low Side Switch (SW2) Pconduction Pswitching RDS(on)SW1 I * * 2 L RDS(on)SW2* I2 *(1- ) L Vin *(Qgsth(SW1)+ Qgd(SW1)) *f * IL Ig Zero Voltage Switching Pdiode Recovery Not Applicable 1 Vin * Qrr(SW2)*f Conduction Not Applicable Vf(SW2) * IL * t deadtime*f Qgls(SW2)* Vgg * f Vin *Qoss(SW2)*f 2 Pgate(Q ) G PQoss Qg(SW1)* Vgg * f Vin *Qoss(SW1)*f 2 Parameter Qgsth Qgls Pconduction Pswitching Pdiode Pdiode PQoss Meaning Duty-Cycle Post Threshold Gate Charge Third Quadrant Gate Charge On State Losses On-off Transition Losses Conduction and Reverse Recovery Diode Losses Gate Drive Losses Output Capacitance Losses 1 Dissipated by SW1 during turn-on 7/8 STD60NH03L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 8/8 |
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