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INDEX
MX96037
FEATURES
* 16-bit, 47/54/65 ns cycle (21/18/15 MIPs) DSP controller. * 16x16 multiplier, one cycle multiply-accumulate. * 32-bit ALU and 16-bit auxiliary ALU (ARAU) work in parallel. * 8 auxiliary registers for indirect addressing work with ARAU. * 16-level hardware stack and nestable interrupt support. * 32-bit barrel shifter. * 8-instruction looped up to 128 times capability. * Block program move. * 64k words program ROM space, 18k words may be internal. * External ROM option may replace internal 18K for fast prototyping. * 64k words SRAM space, 2048 words internal. 32 internal IO address. 1 independent interrupt pin, 1 NMI pin. 8 input pins. 8 bi-direction I/O pins. 16 output pins. Hold or slow system clock for power management. 1 ms system tick timer for system timing. One Codec interface. Built-in DRAM Controller;1G addressing space, with 1/4/8/16 data bit interface support. * Single 5V supply, 100 pins PQFP * * * * * * * * *
PIN CONFIGURATION
100 PQFP
ED10 ED9 ED8 ED7 ED6 ED5 ED4 ED3 ED2 ED1 GND VDD ED0 HOLD\ HOLDA\ EDCE\ EPCE\ ERD\ EWR\ EAD0 EAD1 EAD2 EAD3 EAD4 EAD5 EAD6 TEST GND EAD7 EAD8 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
ED11 ED12 ED13 VDD GND ED14 ED15 X1 X2 CAS\ DRD\ DWR\ RAS\ POPT15 POPT14 RST\ EROM POPT13 OPT12 OPT11
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
MX96037
EAD9 EAD10 EAD11 EAD12 EAD13 EAD14 GND VDD EAD15 NMI\ INT1\ PHILO\ CDR0 PHRDB\ CMCK CFS CDX0 PHWRB\ PHDB0 PHDB1
OPT10 OPT9 OPT8 OPT7 OPT6 OPT5 OPT4 OPT3 OPT2 OPT1 OPT0 X32I X32O PACKB\ IPT7 IPT6 IPT5 IPT4 IPT3 IPT2 IPT1 IPT0 VDD GND PHDB7 PHDB6 PHDB5 PHDB4 PHDB3 PHDB2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P/N: PM0232
1
REV. 1.1, NOV 15, 1995
INDEX
MX96037
PIN DESCRIPTIONS A. DSP BASIC (22 PINS)
SYMBOL VDD PIN TYPE PIN NUMBER 23, 43, 69, 84 24, 44, 53, 70, 85 88 89 I OA 96 14 DESCRIPTION 5V power source
GND
Ground
X1 X2 RST\ PACKB\(XF\)
Crystal input Crystal output Power-on Reset, Schmite-triggered If UPMODX=1 External flag, this pin can be directly written by one DSP instruction. Default inactive (5V output). UPMODX=0, ACKNOWLEDGE to host, data is ready in CMR. Hold DSP clock down and release bus Ack to HOLD\ signal Disable internal ROM; use external ROM only. Non maskable interrupt pin. Interrupt pin 32k Crystal output. 32k Crystal input. Connect to VDD ( for test only).
HOLD\ HOLDA\ EROM NMI\ INT1\ X32O X32I TEST
I OA I I I OA
67 66 97 41 40 13 12
I
54
2
INDEX
MX96037
PIN DESCRIPTIONS (Continued) B. DSP EXTERNAL MEMORY (41 PINS)
SYMBOL PIN TYPE PIN NUMBER 61-55, 52-45, 42 DESCRIPTION DSP IO/RAM/ROM external address bus. EAD0-EAD14 are for DRAM address also. DSP IO/RAM/ROM/DRAM external data bus. External data chip enable. External program chip enable. SRAM/ROM/IO external read. SRAM/ROM/IO external write. DRAM column address select. DRAM row address select. DRAM read. DRAM write.
EAD0-EAD15 OB
ED0-ED15 EDCE\ EPCE\ ERD\ EWR\ CAS\ RAS\ DRD\ DWR\
I/OB OB OB OB OB OB OB OB OB
68, 71-83, 86-87 65 64 63 62 90 93 91 92
MP INTERFACE
SYMBOL PHILO\ PIN TYPE I PIN NUMBER 39 DESCRIPTION High- or low-byte select (UPMODX =0). Output port OPT 18 (UPMODX =1). Host read (UPMODX =0.) Output port OPT 17 (UPMODX=1).
PHRDB\ PHWR\ PHDB(7:0)
I I B
37 33 25~32
Host write (UPMODX =0). Output port OPT 16 (UPMODX =1). Host data bus (UPMODX =0). Bidirectional IO port (UPMODX =1).
3
INDEX
MX96037
PIN DESCRIPTIONS (Continued) D. CODEC (6 PINS)
SYMBOL CFS CMCK CDX0 CDR0 PIN TYPE OB OB OA I PIN NUMBER 35 36 34 38 DESCRIPTION Codec frame sync, 8 KHz. (6KHz) Codec master clock, 1.536 MHz (default output). Codec data transmit Codec data receive
E. OPT : Output port (13 PINS)
SYMBOL PIN TYPE PIN NUMBER 1-11,94,95,98 99, 100 DESCRIPTION Output to pin, all output values are registered and may be read back when read by 'IN' instruction.
OPT0-OPT15 OC
F. IPT : Input port (8 PINS)
SYMBOL IPT7-IPT0 PIN TYPE I PIN NUMBER 15-22 DESCRIPTION Input port. IPT0-IPT3 with internal pull high
G. BIO : Bi-direction I/O (8 PINS)
SYMBOL BIO0-BIO7 PIN TYPE I/OB PIN NUMBER 25-32 DESCRIPTION Input/output port. Direction is controlled by BIO15-BIO8, (see BIOR).
NOTE: OA = 2mA, OB = 4mA, OC = 16mA output current. Symbol with backslash or bar is low active.
4
INDEX
MX96037
FUNCTIONAL DESCRIPTION
MULTIPLIER
A 16x16 with 32-bit result multiplier is included. Efficient FIR operation can be realized through MB and MPA instructions. Since multiplication is an important operation in DSPalgorithm, flexible multiplication is important in DSP implementation. The MX96037 supports complex multiplication (MB) for communication application. General multiplication operations may use MPA and MX. AUXILIARY REGISTERS Eight 16 bits auxiliary registers are allocated together with a 16-bit adder/subtractor. The results of adder/ subtractor always go through a modulator to get modular addressing before being stored to the auxiliary registers. The process provides an independent processor to do address calculation and update in parallel with main data path which performs the instruction execution. Of course, AR registers can also be used as temporary registers and as another unsigned adder/subtractor. AR register modification of (0,1,2,AR0) on the fly is also included. STACK Hardware contains 16 deep dedicated stack memories, which support deep hierarchy code. Stack manipulation is transparent to firmware. RAM/ROM MAP The MX96037 provides 64k words address space for both RAM and ROM.18k words ROM and 2k words RAM are on- chip. The other memory spaces are for external use. The internal 18k words ROM can be disabled by pulling EROM pin high, then external memory will be addressed for the first 18k words spaces. The MX96037 also provides 32 on-chip IO port for DSP use. These IO ports can be accessed by IN, OUT or specific instructions (see register definition). HOLD Hardware hold is supported through pins HOLD and HOLDA. When HOLD is activated, the MX96037 will enter hold state after the present instruction cycle is completed(instructions inside Loop and inherent repeat instruction cycles is considered one instruction cycle). At hold state, the MX96037 will release address and data bus to high impedence, stop executing instruction and output HOLDA. After HOLD is invalid the MX96037 will bring HOLDA to high and resume normal operation.
LOOP
Repeat or loop instruction is important in DSP operation. The MX96037 supports this function by implementing many instructions which are implictly repeated with the number stored in the RCR register. Examples are TBR, MPA, etc. Loop up to 8 instructions with specified number of times (can be variable) is also implemented with hardware. Again, flexible usage format is supported which makes the instruction more useful. MODULAR ADDRESSING Modular addressing is by modular operation at the output of ARAU. To use modular addressing user must first store non-zero number m which is stored to the MODR register. With this in effect, memory space beginning from k*2 n to k*2 n+m, where k is an integer greater than or equal to zero and 2n is a power-of-two integer greater than m, will form a circular memory space. Whenever boundary location, 0 or m, is addressed, the next AR content will be set/reset to m/0, independent of the instruction specification. Set MODR to 0 will deactivate modular addressing. For example, if MODR is set to 23, circular memory spaces will start from 32*k to 32*k+23. Any instruction can be indirectly addressed to 55, assuming that using AR1, with increasing operation, will make the next AR1 content to be reset to 32. Likewise, if AR1 content is in decreasing operation and the content of AR1 is set to 0, then the next value of AR1 will be reset to 23. If normal addressing mode is desired, simply output a 0 into the MODR registers. This instruction can help construct data RAM into circular buffer or delay line, thereby eliminating the need of physical data movement in the buffer or delay. However, the pointer need to be kept in the data RAM for easy access to the head/tail of this buffer/delay line.
5
INDEX
MX96037
HOST INTERFACE
UPMODX=0 will enable p command interface hardware and firmware to support external p operations. If UPMODX=0, CMDR, a 16-bit bidirection register, can be accessed by HOST via PHDB(7:0) pins in two accesses selected by PHILO\ pin. DSP accesses CMDR by 16-bit width. When HOST writes to high byte of this register, CRDY bit in register 7 (bit 6) will be set. When DSP reads CMDR, CRDY bit will be reset. PACKB\ signal is defaultly set to high. When DSP writes to CMDR, PACKB\ is reset(active low). The host read will set this PACKB\ pin to high. External p may use this parallel interface to set DAM_BIOS command and read responses from this port. INTERNAL/EXTERNAL MEMORY CONSIDERATIONS 1. DSP internal RAM is always selected, if external RAM is overlapped, the external portion is invisible by DSP. 2. DSP internal ROM may be disabled by active EROM pin. For initial program development, EROM\ may be active to use full range of external ROM. For sake of smarter ROM planning , DSP could write a test of external ROM presence, if external rom exists, just jump to the external directly. There are many possible configurations to be considered such as building DSP fast routine in internal ROM (just like IBM PC BIOS) or basic control system inside while leaving flexibility outside using shower memory.
SYSTEM TICK System tick always exists. It periodically interrupts DSP every 1 ms in normal mode or 32 ms in power down mode unles system tick interrup is masked (IMR:STMRM=1). Standard timer system may be implemented by this tick. POWER MANAGEMENT There are several ways to do power management. Users can program, PWDN or/and SWHOLD or assert HOLD\. 1. if SWHOD bit is set or hardware HOLD\ signal is activated, DSP operations and Codec clock will be halted. Any interrupt source at SWHOLD mode will reset SWHOLD then DSP will resume normal operation. Interrupt can't affect HOLD\. 2. When PWDN is set, DSP will run at 32.768 kHz and hi-crystal oscillation circuit is de-activated until it is reset to zero. Normally, It takes 62 mini second to re-activate crystal oscillation circuit and status bit LSRUN indicates the speed of DSP of current operation.
6
INDEX
MX96037
REGISTER DESCRIPTIONS
NAME optr iptr bior svr imr isr ctrl wstr mmacr mmapl mmaph rcr modr xr BIT 16 8 16 4 4 3 15 8 16 15 16 7 7 16 o o o CTLR o o o IO ADDRESS RELATED INSTRUCTIONS 0 1 2 3 4 5 7 8 9 10 11 12 13 14 IN/OUT IN/OUT IN/OUT IN/OUT IN/RPT/TBR/MPA/LUP IN/MOD IN/LX/LXA/LXM/LXS multiply instructions sp 4 15 PSH/POP/IN/PSHH/POPH TBR, MPA,PSHL,POPL cdrr0 cdxr0 pregl pregh 16 16 16 16 o o 16 17 18 19 IN OUT codec 0 receive buffer codec 0 transmit buffer product register low word product register high word stack pointer register IN/OUT IN IN/OUT IN/OUT/SFR/SFL IN/OUT IN DESCRIPTIONS output register input port register bidirectional io register shifter count (scr) and sign interrupt mask register interrupt status register control register wait state control register dram access control register dram access pointer low dram access pointer high repeat counter modulo register one of multiplier operands
7
INDEX
MX96037
REGISTER DESCRIPTIONS (Continued)
NAME tstr acch accl ar0-7 BIT 8 16 16 16x8 CTLR o IO 20 - - - RELATED INSTRUCTIONS IN/OUT (many instr.) SAL/ADL/SBL LAR/MAR/SAR for indirect memory access basically; also used in macro instructions accx p ssr 32 32 16 - - SBL, ADL, SFL SFR,multiply multiply instructions PAC/APAC SSS/OUT/BS/BZ INTM : EINT/DINT TB : BIT OVM : ROVM/SOVM ARP : MAR pc 16 - CALL, CALA, TRAP, BS, BZ BACC, RET, RETI, interrupt, hardware reset program counter acch+accl=accx product register status register DESCRIPTIONS test and codec control register DSP accumulator, the basic ALU
8
INDEX
MX96037
TABLE OF IO MAPPED REGISTERS
F E D C B A 9 8 7 6 5 4 3 2 1 0
OPTR:(00) IPTR:(01) BIOR:(02) SVR:(03) IMR:(04) ISR:(05)
0
OPT15
0
OPT14
0
OPT13
0
OPT12
0
OPT11
0
OPT10
0
OPT9
0
OPT8
0
OPT7
0
OPT6
0
OPT5
0
OPT4
0
OPT3
0
OPT2
0
OPT1
0
OPT0
RW RO RW RW RW RO RW RW RW RW RW RO RO RO RO RO WO WO WO
x
IPT7
x
IPT6 BIOR6
x
IPT5 BIOR5
x
IPT4 BIOR4
x
IPT3 BIOR3
x
IPT2 BIOR2
x
IPT1 BIOR1
x
IPT0 BIOR0
0
BIOR15
0
BIOR14
0
BIOR13
0
BIOR12
0
BIOR11
0
BIOR10
0
BIOR9
0
BIOR8
0
BIOR7
0
0
0
0
0
0
0
0 1
SSM
0 1
STMRM
0 1
CODCM
0 1
INTIM
SCR3 ~ SCR0
0
STMRS
0
CODCS
0
INTIS
0 CTLR:(07) WSTR:(08)
0 OPT18
0
OPT17
0
OPT16
0
0
0
FAST1
0
FAST0
0
HMOD
0
0
1
0
SS
0
HSSRC 1 1 MMWAIT
0
SNSEL
0
0
PWDN SWHOLD
CMDRDY LSRUNS
UPMODX C6KSEL 1 1 ROMWAIT
0 1 MMSIZE 0 0 0 0 MMCNT (Mass Memory move Count, 6 bits) 0 0 0
1 SRAMWAIT
MMAC:(09)
0 0 0 0 0 IRA (Internal RAM Address, bank one, 10 bits)
0
0
0
MMAPL:(10) MMAPH:(11) 0
TOIRAM
x x
x x
x x
x x
x x
x x
x x
x x
x x 0
x x 0 0 0
x x 0 0 0
x x 0 0 0 0
x x 0 0 0 0 x x x
x x 0 0 0 0 x x x
x x 0 0 0 0 x x x
RCR:(12)
^ ^ ^ ^ ^ ^ ^ ^ ^
MODR:(13) XR:(14) SPR:(15) CDRR:(16) CDXR:(17) x x x x x x x x x 0 0 0 0 0 0 0 0 0
0 0
x
x
x
x
x x x
x x x
x x x
x x x
x x
x x x
x x x
x x x
x x
x x
x x
x x
x x
PREGL:(18) PREGH:(19) TSTR:(20)
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
RO
*NOTE : Register 6 is revised for future use.
9
INDEX
MX96037
1. ACC:ACCUMULATOR
ACC = ACCH + ACCL
ACCH
ACCL
* * * *
acch+accl=acc Logic ALU operation is 16 bits and executed on acch. (ACCL is not affected) ADL/SBL is 32-bit operation. (SVR:SNSEL determine sige-extended) Lac will put ACCL to 0
SSR : STATUS REGISTER ssr includes 8 testable status/register bits (ssr:15~8), and 3 arp bits, 2 IOP bits, 4 DP bits SGN and ACZ reflect status of ACCH. (can not be saved)
This bit has two functions. It provides an "always true" condition for effectively unconditional branch (jump). On the other hand, it's also treated as "INTM",a global interrupt mask status. It ACC zero flag can be only set or reset by EINT or DINT. This bit reflects ACCH If INTM=1, interrupt is prohibited. current status directly. so, it is read only. sign flag reflects ACCH directly, read-only
overflow mode enable, used for overflow protection during +/ -/shift operations.
4-bit data page pointer defines 16 pages,128 address in each page, of internal RAM
RO 1/INTM
RW ARZ SGN
RO OV
RW ACZ
RO TB
RW
RW OVM
RO ARP2~ARP0
RW IOPR4~3 DPR3~DPR0
WO
testable
overflow flag for the last acch operation ARZ registering the last operated AR=0
Test bit, the tested memory bit is moved to TB register (BIT instructions) a conditional test is normally followed but not necessary
current active AR register Pointer.. There are 8 16-bit AR registers in DSPC.
IOPR define 4 Pages, 8 address in each page,of IO space.
10
INDEX
MX96037
AR (AUXILIARY REGISTER) AND ARAU (AUXILIARY ALU)
AUXILIARY REGISTERS
ar0 ar1 ar2 ar3 ar4 ar5 ar6 ar7
16-bit register
ARAU AUXILIARY ALU
* 16x8 AR registers provide powerful indirect memory access. * Modulo addressing (modulo memory indexing) provides easy implementation of ring buffer or delay line. See modulo register (MODR) for more details. * ARAU provides +/ - (0, 1, 2, AR0) post execution after each addressing of ARs. * ARAU works in parallel with main ALU. * ARs may be also used as scratch registers.
PC AND PROGRAM FLOW CONTROL
PC
Program Counter
Program flow is affected by: 1. 2. 3. 4. 5. 6. BS/BZ (branch-if-set/branch-if-zero) conditional branch. BACC - branch indirectly by ACCH. CALA - call indirectly by ACCH, return address is pushed. CALL - call subroutine, see 'Addressing Modes, Misc. Addressing mode' TRAP - Trapped to call fixed hex 000C address. Power-on reset and interrupt see 'interrupt Operations'
11
INDEX
MX96037
ADDRESSING MODES IMMEDIATE CONSTANT Immediate constant is coded directly in opcode. DIRECT MEMORY ADDRESSING DPR and IOPR are used to completely specify addressing spaces. 4 bits in DPR combined with 7-bits coded in opcode, make direct memory address. (direct memory addressing ONLY FOR INTERNAL 2K WORDS RAM)
INDIRECT ADDRESSING The memory address may be pointed by ARs. ARs also has post-addressing execution which provides powerful increment(s)/decrement(s) and modulo indexing. It takes only 7 bits to code all these into one opcode to enable program size compact. See AR, ARAU and MODR for more details.
MISCELLANEOUS ADDRESSING MODE CALL--Call subroutine at the second word of call instruction. CALA--ACCH indirect call, ACCH=called address BACC-- ACCH indirect branch, ACCH=branch address TRAP-- Always call to hex 000C address
MACRO OPERATIONS * LUP - repeat instruction-block (max 8 instructions) - repeat count = RCR +1 - Each time PC hits loop boundary (starting address +LC), loop count is increased by 1 * MPA - Vectored inner product, see 'P, X, Y Register and Multiplier Operations.
12
INDEX
MX96037
INTERRUPT : OPERATIONS The Interrupt source, vectoring address and priority are as follows:
NAME RST\ NMI\ SS VECTORED ADDRESS DESCRIPTIONS 0000 0002 0004 Power-on reset (top priority) NMI\non.maskable interrupt, edge-triggered (high to low) Single-Step, Single step interrupt is for debugging purpose. If set, MX96037 will be interrupted after every instruction cycle (instructions inside LOOP and inherent repeat instruction cycles is considered as one instruction cycle). User can put debugging service INT1\ 0006 as the interrupt service routine. INT1\ pin interrupt, edge trigged Triggered when Codec registers get/send 16 bit data (see Timing diagram) Triggered every 1 msec Triggered when executes TRAP
CODEC 0008 STMR TRAP 000A 000C
Interrupt Process: (Execute by hardware) 1. 2. 3. 4. 5. Release related ISR pending flag Push SSR on to stack Push return-address on to stack Disable global interrupt (same to excuting DINT instruction) If it is in software hold state ( see WSTR register and power management), reset SWHOLD 0, and come out of software hold state.
Issues of RETI instruction: (Execute by hardware) 1. POP return address to PC 2. POP SSR Note that ACC normally need to be saved. All other registers should also be carefully maintained when doing an in-and-out interrupt.
13
INDEX
MX96037
P, X, Y REGISTER AND MULTIPLIER OPERATIONS
Y Register
(not accessable by user)
X Register
Product Register
Multiplier operand is fed from X and Y registers (see Architecture). X is visible by instruction, Y is supplied from various source (such as constant, memory, acch). The result of multiplication is put in p register. Accumulation is done through pipelining. Note that the result of multiplication is always shift-left one bit before being put in register(do not use ox 8000 multiply which will cause overflow).
BASIC MULTIPLY MX/MXP MXK/MXL (x)*(dma) p (x)*constant p
ACCUMULATE PREVIOUS PRODUCT AND MULTIPLY MXA/MXAP (accx) + (p) accx, (x) * (dma) p
SUBTRACT PREVIOUS PRODUCT AND MULTIPLY MXS/MXSP (accx) - (p) accx, (x) * (dma) p
MULTIPLY BANKED COMPLEX NUMBER (a+bj)*(c+dj) MB MB MB MB RR, * RI, * IR, * II, * a*c p a*d p b*c p b*d p
ar ar pointing a a must be in bank0 even address (b in odd) BANK0 BANK1
RR a b II
IR RI
c d
c at the same address offset in bank one
Note : When working with repeat counter (rcr), loop instruction and ARAU operation, array of complex number may be calculated efficiently.
14
INDEX
MX96037
MULTIPLY BANK AND ACCUMULATE MBA MBA MBA MBA RR, * RI, * IR, * II, * (acch) (acch) (acch) (acch) + + + + (p) (p) (p) (p) acch, acch, acch, acch, a*c p a*d p b*c p b*d p
MULTIPLY BANK AND SUBTRACT MBS MBS MBS MBS RR, * RI, * IR, * II, * (acch) (acch) (acch) (acch) (p) (p) (p) (p) acch, acch, acch, acch, a*c p a*d p b*c p b*d p
VECTORS INNER PRODUCT X = [a b c] X*Y=a*d+b*e+c*f Y = [d e f]
BANK0 BANK1
ar ar pointing a a must be in bank0, any address
a rc b c pc d e f d can start from any address in bank 1
repeat count should be loaded before this operation
offset index must be prepared in acch, and it will be loaded to pc during operation
MPA *, NAR [(accx) +(p) p, (ar)*(pc) p, (pc) +1 pc] repeat rc+1 times.
15
INDEX
MX96037
IO REGISTERS OPTR : Output Register (mapped to IO register 00)
F E D C B A 9 8 7 6 5 4 3 2 1 0
OPTR15
OPTR0
RW
Output Register (OPTR:15 ~ OPTR:0) 16 bit, connect to OPT15~OPT0 pins. positive Logic, '1' will output 5 Volt on output pin. ('0' for 0 V) All these bits can memory output value (read by 'IN' instruction) to eliminate shadow memory requirement.
IPT : Input Port Register (mapped IO address 01)
F
E
D
C
B
A
9
8
7 IPT7
6 IPT6
5 IPT5
4
3 IPT3
2
1
0 IPT0
IPT4
IPT2
IPT1
RO
Input Port Positive Logic, 5 Volt input will read '1' (0V for '0') IPT:7~IPT:0 connect IPT7~IPT0 pins. IPT3~IPT0 are internally pull high
BIOR/CMDR : BI-DIRECTION IO REGISTER IN NON-UP MODE OR COMMAND REGISTER IN UP MODE (mapped to IO register 02)
F E D C B A 9 8 7 6 5 4 3 2 1 0
BIOR15
BIOR14
BIOR13
BIOR12
BIOR11
BIOR10
BIOR9
BIOR8
BIOR7
BIOR6
BIOR5
BIOR4
BIOR3
BIOR2
BIOR1
BIOR0
RW
as UPMODX=1, used for bidirectional io register. Programable bidirectional IO. BIOR15~BIOR8 control I/O direction of BIOR7~BIOR0, respectively (bit 8 control bit 0) BIOR7~BIOR0 connect to BIO7~BIO0 pins, respectively. UPMODX=0, used for 16-bit parallel interface command register.
16
INDEX
MX96037
SVR : Shift Variable Register (mapped to IO register 03) SVR includes Shift-Count Register (SCR)
F E D C B A 9 8 7 6 5 4 3 0 2 0 1 0 0 0
SCR3~SCR0
RW
When SFL/SFR instruction gives 0 as shift count, DSP uses the SCR default count as shifting count. This mechanism provides run-time assigned shifting value.
IMR : Interrupt Mask Register (mapped to IO register 04)
F E D C B A 9 8 7 6 5 4 3 1 SSM 2 1 STMRM 1 1
CODCM
0 1 INT1M
RW
ISR : Interrupt Status Register (mapped to IO register 05)
F E D C B A 9 8 7 6 5 4 3 2 1 1 1 0 1
INT1S
STMRS CODCS
RO
INT1M STMRM CODCM SSM
Note 1:
-
INT1 \ Interrupt Mask 1 System tick Timer interrupt Mask Codec Interrupt Mask Single Step Interrupt Mask
Note 2: Note 3:
Codec Tx/Rx use this same mask. This is because the 2 events are synchronized and always happen at the same time. Programmers should take care of these 2 events (if necessary) in this interrupt. ISR:2~0 will reflect interrupt pending status on IMR:2~0. Note that Single-Step (CTLR:SS, register 07) is directly controlled by the program; no status exists. Read ISR will read and clear all pending flags.
17
INDEX
MX96037
CTLR : CONTROL REGISTER (MAPPED TO IO REGISTER 07)
0: up mode. 1: DSP will hold after the current fetched 1: non_up mode. instruction has been excuted. 0: DSP runs until external bus is accessed. 1: 32768 HZ clock is generated from Hi-crystal instead of from low crystal 0: 32768 HZ clock is from low crystal 6 0 5 0
LSRUNS
1: DSP runs at 32768 HZ until reset to 0 0: normal operation.
1: It works as external hardware HOLD\ pin except issued by instructions and cleared by interrupt. 0: normal operation.
F
E 0
OPT18
D 0
OPT17
C 0
OPT16
B 0
PWDN
A 0
9 0
8 0
FAST0
7 0
4 0
SS
3 0
HSSRC
2 0
1 0
0 0
SWHOLD FAST1
HMOD CMDRDY
SNSEL UPMODX C6KSEL
RW
It's a status bit. 0: DSP is running at high speed mode. 1: DSP clock is 32768 HZ
0: normal operation. 1: single step mode. A interrupt will occur at end of each instruction.
1: select 6 KHZ codec frame sync. 0: select 8 KHZ codec frame sync.
In non-p mode, The statuses of OPT18, OPT17, OPT16 will be reflected to PHILO\, PHRDB\, PHWR\ respectively. 1: output 5v to PHILO\, PHRDB\ and PHWRB\ pins in up mode. 0: output 0v to PHILO\, PHRDB\ and PHWRB\ pins in up mode.
00: select 23.040 MHZ external clock 01: select 27.648 MHZ external clock 10: select 32.256 MHZ external clock 11: select 32.256 MHZ external clock CMDRDY is cleared by CMDR read. 1: External up writes a command to DSP. 0: no write operation.
0: no sign extension 1: MSBs sign extented in ADL, ADLL, SBL and SBLL instructions.
WAIT STATE: ROM/RAM Timing Requirement = (3+2W)C- 20ns W=0/1/2/3 (wait state number on IO/RAMWAIT/ROMWAIT field) C=21.7/18.08/15.5ns (internal clock timing for external crystal 23.040/27.648/32.256 MHz)
WAIT-STATE NUMBER ROM/RAM C=15.5 C=18.08 C=21.7 0 1 2 3
26.5 34.2 45.1 -
57.5 70.8 88.5 -
88.5 107.4 133.6 -
119.5 144.0 179 70-120ns
DRAM
NOTE: The MX96037 may have 23.040/27.648/32.256 MHz crystal options. This clock is doubled internally. Instructions will use 3 clocks as an instruction cycle (SAH/SAHP, SAL/SALP, SSS/SSP extend 1 internal clock).
18
INDEX
MX96037
WSTR: WAIT STATE, SINGLE-STEP AND DRAM SIZE (MAPPED TO IO REGISTER 08)
F E D C B A 9 8 7 0 MMSIZE 6 1 5 1 4 1 SRAMWAIT 3 1 MMWAIT 2 1 1 1 0 1 ROMWAIT
RW
Mass Memory Size (ARAM) Select the external DRAM bit-size 0 0 -- 1 bit 0 1 -- 4 bits 1 0 -- 8 bits 1 1 -- 16 bits
19
INDEX
MX96037
DRAM CONTROLLER : MMACR, MMAPH AND MMAPL MMACR : Mass Memory Access Control register (mapped to IO register 9)
F 0 E 0 D 0 C 0 B 0 A 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
MMCNT (Mass Memory move Count, 6 bits)
IRA (Internal RAM Address, bank one, 10 bits)
RW
write (OUT) a non-zero count to MMCNT will start DRAM move and hold DSP until MMCNT=0 movement of DRAM address count for a 1M-by-4 DRAM, 60 DRAM address will move and make-up 15 16-bit words.
specified address 1024 in bank 1, physically is addressed. (only bank 1 space may interface with DRAM)
MMAPL : Mass Memory Access Pointer Low register (mapped to IO regsiter 10)
F E D C B A 9 8 7 6 5 4 3 2 1 0
x
x
x
x
x
x
x
x
x
x
x
x
RW
MMAPH : Mass Memory Access Pointer High register (mapped to IO register 11)
F E D C B A 9 8 7 6 5 4 3 2 1 0
o
TOIRAM
x
x
x
x
x
x
x
x
x
x
x
x
RW
TOIRAM=1, DRAM Internal RAM TOIRAM=0, Internal RAM DRAM MMAPH+MMAPL make-up 30 bits, 1G addressing space. This space may have max 1G words DRAM capacity.
20
INDEX
MX96037
RCR : Repeat Counter Register (mapped to IO register 12)
F E D C B A 9 8 7 6 5 4 3 2 1 0
o
o
o
o
o
o
o
RO
* RCR provides repeat count on TBR, LUP, and MPA types macro instructions. * RCR must be prepared before macro instructions are being executed. (RPT instruction) * Repeat time is RCR+1 MODR : MODULAR REGISTER (MAPPED TO IO REGISTER 13)
F E D C B A 9 8 7 6 5 4 3 2 1 0
x
x
x
x
x
x
x
x
x
o
o
o
o
o
o
o
RO
As MODR=M 0, 1, 2, .., M-1, M modulo mechanism will be enforced (note: bounded by M --- not M-1) Modular addressing is always performed at the output of ARAU. As MODR=0, modulo addressing is disabled. MOD type instructions are used to load MODR; use IN instruction to read MODR.
XR : X REGISTER (MAPPED TO IO REGISTER 14)
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
RO
* One of multiplier inputs * Can be accessed by IN/LX/LXM/LXS/LXA/LXAK etc... instructions.
SPR : Stack Pointer Register (mapped to IO register 15)
F E D C B A 9 8 7 6 5 4 3 2 1 0
o
o
o
o
RO
* * * *
16-level stack provides nestable interrupt and controller level nested call capabilities. SPR is pointing to 'next-available' word, and initialized to 0. As SPR is over address 15, it wraps around to 0. As SPR=0, POP will also wrap SPR to 15. SPR can only be read by IN instructions; no write capability.
21
INDEX
MX96037
CDRR : Codec Data Receive Register (Mapped to IO register 16)
F E D C B A 9 8 7 6 5 4 3 2 1 0
RO
CDXR : Codec Data Transmit Register (Mapped to IO register 17)
F E D C B A 9 8 7 6 5 4 3 2 1 0
WO
1. Two Codec events from the above registers are always synchronized, so there is only one Codec interrupt for them. 2. These codecs are in 16-bit mechanism; however, 8-bit Codec is also applicable. In 8-bit case, to tx, the data byte to be transmitted must be in bit15~bit8. The received data byte is at bit15~bit8 as read from receive register. 3. MSB (Most-Significant-Bit) is shifted first. 4. Codec registers has shadow registers as buffer.
PREGL : Product Register Low Word (Mapped to IO register 18)
F E D C B A 9 8 7 6 5 4 3 2 1 0
WO
PREGH : Product Register High Word (Mapped to IO register 19)
F E D C B A 9 8 7 6 5 4 3 2 1 0
WO
TSTR: Test Register Mapped to Register (mapped to register 20)
F E D C B A 9 8 7 6 5 4 3 2 1 0
0
0
0
0
0
0
0
0
0
RO
Internal use, always put 0; invalid value may cause unexpected result !!!. Internal use always put 0
22
INDEX
MX96037
INSTRUCTION SET SUMMARY ABBREVIATIONS a ar acc c d dp i k I L mr mb0 mb1 o p pa pc R rc s sp ss sv x xr y : : : : : : : : : : : : : : : : : : : : : : : : : : AR pointer AR accumulator short constant data memory address data page pointer Addressing mode select bit odd/even address select loop counter constant for shift left modulo register internal memory bank 0 internal memory bank 1 io page pointer product register port address program counter constant for shift right repeat counter shift right sign extention select bit stack pointer status register shift register don't care x register AR arithmetic operation select
Mnemonic and Description abs ; adh ; adhk ; adhl ; adl ; adlk ; adll ; and ; andk ; andl ; apac ; bacc ; bit ; absolute value of accumulator add to high acc add to high acc. short immediate add to high acc. immediate add to low acc add to low acc. short immediate add to low acc. immediate and with high acc and short immediate with high acc and immediate with high acc add p reggister to acc branch to address specified by acc test bit
Words & cycles 1,1 1.1 1,1 2,2 1,1 1,1 2,2 1,1 1,1 2,2 1,1 1,2 1,1
16-bit MSB 1001 0000 0000 1000 0000 0000 1000 0000 0000 1000 1001 1111 0110
opcode 1000 0000 0001 0000 0010 0011 0001 1010 1011 0101 0010 1010 bbbb 0xxx iddd 0ccc 0xxx iddd 0xxx 0xxx iddd 0ccc 0xxx 0xxx 0xxx iddd LSB xxxx dddd cccc xxxx dddd xxxx xxxx dddd cccc xxxx xxxx xxxx dddd
23
INDEX
MX96037
Mnemonic and Description bs bz cala call dint eint in lac lack lacl lar lark larl ldp ldpk lip lipk lup lupk lx lxk lxl lxa lxak lxal lxm ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Words & cycles 16-bit opcode MSB LSB 1101 1bbb 0xxx xxxx 1101 0bbb 0xxx xxxx 1,2 1100 0000 0xxx xxxx 1111 1100 0000 0000 1111 0000 0xxx xxxx 1111 0001 0xxx xxxx 1010 ppp0 iddd dddd 0000 1110 iddd dddd 0000 1111 0ccc cccc 1000 0111 0xxx xxxx 0111 aaa0 iddd dddd 0111 aaa1 0ccc cccc 1000 1000 0aaa 0000 0001 0100 iddd dddd 0001 0101 0xxx cccc 0001 0001 0101 0101 0010 0010 1000 0011 0011 1000 0011 0011 1000 0011 0011 1000 0011 0011 1111 0010 iddd dddd 0011 0xxo oxxx 0100 iddd dddd 0101 0ccc cccc 0000 0001 1010 1100 iddd 0ccc 0xxx iddd dddd cccc xxxx dddd
lxmk ; lxml lxs lxsk lxsl mba mbs mar ; ; ; ; ; ; ;
branch immediate if bit set 2,3 branch immediate if bit reset 2,3 call subroutine indirect specified by acc call subroutine 2,3 disable interrupt 1,1 enable interrupt 1,1 input data from port 1,1 load acc 1,1 load acc. short immediate 1,1 load acc. immediate 2,2 load auxiliary register 1,1 load auxiliary register short immediate 1,1 load auxiliary register immediate 2,2 load data page register 1,1 load short immediate to data page 1,1 register load io page register 1,1 load io page register with short 1,1 immediate loop instruction 1,1 load rc with 7-bit constant and enable 1,1 loop operation load x register 1,1 load short immediate to x register 1,1 load immediate to x register 2,2 load x register and accumulate 1,1 previous product load short immediate to x registeri 1,1 and accumulate previous product load immediate to x register and 2,2 accumulate previous product load x register and store 1,1 p register to acc load short immediate to x register 1,1 and store p register to acc load immediate to x register and 2,2 store p register to acc load x register and subtract 1,1 previous product load short immediate to x register 1,1 and subtract previous product load immediate to x register and 2,2 subtract previous product multiply and accumulate previous 1,1 product multiply and subtract previous 1,1 product modify auxiliary register 1,1
1101 0ccc cccc 1011 0xxx xxxx 1110 iddd dddd 1111 0ccc cccc 1100 0xxx xxxx 0100 iddd dddd 0101 0ccc cccc 1101 0xxx xxxx 1000 00kk 0yyy 0000 00kk 0yyy 0110 iddd dddd
24
INDEX
MX96037
Mnemonic and Description mod modk mpa mpc mx mxk mxl mxa ; ; ; ; ; ; ; ; Words & cycles 16-bit opcode MSB LSB 0001 0110 iddd dddd 0001 0111 0ccc cccc 1100 1110 iddd dddd 0010 0100 00kk 0yyy 0010 0010 iddd dddd 0010 0011 0ccc cccc 1000 1110 0xxx xxxx 0011 1010 iddd dddd 0011 0011 0011 1111 0000 0000 1000 0100 0100 1000 1001 1001 1001 1011 1100 1100 1100 1111 1111 1111 1111 0001 0001 1011 1011 1001 1001 1111 1001 1111 1011 1011 1011 0000 0000 1000 1011 0ccc cccc 0010 iddd dddd 0011 0ccc cccc 1111 1000 1001 0100 ppp0 ppp1 1111 0100 1010 1011 0101 1000 1001 1010 0100 0010 1000 1001 0000 0001 0001 1aaa 1100 1110 0101 0110 1011 0010 0011 0100 0100 0101 0010 1111 iddd 0ccc 0xxx iddd 0ccc 0ppp iddd iddd iddd iddd iddd iddd iddd 0xxx 0xxx 0xxx 0xxx iddd 0ccc iddd iddd 0000 000s 0xxx 0xxx iddd iddd iddd iddd iddd 0ccc 0xxx 1111 dddd cccc xxxx dddd cccc 0000 dddd dddd dddd dddd dddd dddd dddd xxxx xxxx xxxx xxxx dddd cccc dddd dddd LLLL RRRR xxxx xxxx dddd dddd dddd dddd dddd cccc xxxx
mxak ; mxs ;
mxsk ; nop or ork orl out outk outl pac poph popl pop pshh pshl psh rovm rxf ret reti rpt rptk sal sar sfl sfr sovm spac sqra sip sss sdp sbh sbhk sbhl ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
load modulo register 1,1 load modulo register short immediate 1,1 array multiplication 1,3+rc ram_bank_0 multiply ram_bank_1 1,1 (x) multiply (dma) 1,1 (x) multiply (7-bit constant) 1,1 (x) multiply (16-bit constant) 2,2 (x) multiply (dma) and accumulate 1,1 previous product (x) multiply (7-bit constant) and 1,1 accumulate previous product (x) multiply (dma) and subtract 1,1 previous product (x) multiply (7-bit constant) and 1,1 subtract previous product no operation 1,1 or with high acc 1,1 or short immediate with high acc 1,1 or immediate with high acc 2,2 output data to port 1,1 output short immediate to port 1,1 output immediate to port 2,2 load acc. with p register 1,1 pop top of stack to high accumulator 1,1 pop top of stack to low accumulator 1,1 pop top of stack to data memory 1,1 push high accumulator onto stack 1,1 push low accumulator onto stack 1,1 push data memory value onto stack 1,1 reset overflow mode 1,1 reset external flag 1,1 return from subroutine 1,2 return from interrupt 1,2 load repeat counter 1,1 load rc with 7-bit constant 1,1 store low acc 1,1 store auxiliary register 1,1 shift acc left 1,1 shift acc right 1,1 set overflow mode 1,1 subtract p register from acc 1,1 square and accumulate previous 1,3+rc product store iopage register 1,1 store ss register 1,1 store datapage register 1,1 subtract from high acc 1,1 subtract short immediate from high acc1,1 subtract immediate from high acc 2,2
25
INDEX
MX96037
Mnemonic and Description sbl sblk sbll sxf tbr trap xor xork xorl ; ; ; ; ; ; ; ; ; Words & cycles 16-bit opcode MSB LSB 0000 0110 iddd dddd 0000 0111 0ccc cccc 1000 0011 0xxx xxxx 1111 0011 iddd dddd 1100 1100 iddd dddd 1100 0010 0xxx xxxx 0000 1100 iddd dddd 0000 1101 0ccc cccc 1000 0110 0xxx xxxx
subtract from low acc 2, 2 subtract short immediate from low acc 1,1 subtract immediate from low acc 1,1 set external flag 1,1 table read 1,3+rc software interrupt 1,2 xor with high acc 1,1 xor short immediate with high acc 1,1 xor immediate with high acc 2,2
26
INDEX
MX96037
abs absolute value of accumulator. Bit: 15 14 13 12 11 10 9 1 SYNTAX: EXECUTION: ABS (pc) + 1 pc |acc(31:16)| (acc (31:16)) 1 1 0 0 1 1 0 0 8 0 7 0 6 5 4 3 2 1 0
WORDS: CYCLES:
adh
add to high acc. direct: 15 14 13 12 11 10 9 0 indirect: 0 0 0 0 0 0 8 0 8 0 7 0 7 1 6 5 4 3 2 1 0
data memory address 6 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 0 0 0 0 0
see note 1
SYNTAX:
adh adh
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (acc(31:16))+(dma) (acc (31:16)) 1 1(DI) 2(DE)
WORDS: CYCLES:
Adhk
add to high acc. Short immediate. BIT: 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 1 7 0 6 5 4 3 2 1 0
7-bit constant
SYNTAX: EXECUTION:
adhk
cnst 7
(pc) + 1 pc (acc(31:16)) + (7-bit constant) (acc (31:16)) 1 1
WORDS: CYCLES:
27
INDEX
MX96037
adhl
add to high acc. Immediate. BIT: 15 14 13 12 11 10 9 1 0 0 0 0 0 0 8 0 7 0 6 5 4 3 2 1 0
16-bit constant
SYNTAX: EXECUTION:
adhl
cnst16
(pc) + 2 pc (acc(31:16))+(16-bit constant) (acc (31:16)) 2 2
WORDS: CYCLES:
adl
add to low acc. Direct: 15 14 13 12 11 10 9 0 Indirect: 0 0 0 0 0 1 8 0 8 0 7 0 7 1 6 6 5 4 32 1 0
data memory address 5 4 32 1 0
15 14 13 12 11 10 9 0 0 0 0 0 0 1
see note 1
SYNTAX:
adl adl
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (acc)+(dma with optional MSBs sign extension) (acc) 1 1(DI) 2(DE) Option is controlled by CTRL: SNSEL bit
WORDS: CYCLES: NOTE:
28
INDEX
MX96037
adlk
add to low acc. Short immediate. BIT: 15 14 13 12 0 0 0 0 11 10 9 0 0 1 8 1 7 0 6 5 4 3 2 1 0
7-bit constant
SYNTAX: EXECUTION:
adlk
cnst7
(pc) + 1 pc (acc)+(7-bit constant) (acc) 1 1
WORDS: CYCLES:
adll
add to low acc. Immediate. BIT: 15 14 13 12 11 10 9 1 0 0 0 0 0 0 8 1 7 0 6 5 4 3 21 0
16-bit constant SYNTAX: EXECUTION: adll cnst16 (pc) + 2 pc (acc)+(16-bit constant with optional MSBs sign extension*) (acc) 2 2
WORDS: CYCLES:
Note:option is controlled by CTRL :SENSE bit
29
INDEX
MX96037
and
and with high acc. direct: 15 14 13 12 11 10 9 0 indirect: 0 0 0 1 0 1 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 0 0 1 0 1
see note 1
SYNTAX:
and and
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (acc(31:16)) .and. (dma) (acc(31:16)) 1 1(DI) 2(DE)
WORDS: CYCLES:
andk
and short immediate with high acc. BIT: 15 14 13 12 11 10 9 0 0 0 0 1 0 1 8 1 7 0 6 5 4 3 2 1 0
7-bit constant
SYNTAX: EXECUTION:
andk
cnst7
(pc) + 1 pc (acc(23:16) .and. (7-bit constant) (acc(23:16)) 0 acc(31:24) 1 1
WORDS: CYCLES:
30
INDEX
MX96037
andl and immediate with high acc. BIT: 15 14 13 12 11 10 9 1 0 0 0 0 1 0 8 1 7 0 6 5 4 3 2 1 0
16-bit constnat SYNTAX: EXECUTION: andl cnst16
(pc) + 2 pc (acc(31:16)) .and. (16-bit constant) (acc(31:16))
WORDS: CYCLES: apac
2 2 add p register to acc. BIT: 15 14 13 1 0 0 12 11 10 9 1 0 0 1 8 0 7 0 6 5 4 3 2 1 0
SYNTAX: EXECUTION:
apac (pc) + 1 pc (acc)+(p) (acc) 1 1 branch to address specified by acc. BIT: 15 14 13 12 11 10 9 1 1 1 1 1 0 1 8 0 7 0 6 5 4 3 2 1 0
WORDS: CYCLES: bacc
SYNTAX: EXECUTION: WORDS: CYCLES:
bacc (acc (31:16)) pc 1 2
31
INDEX
MX96037
bit
test bit. direct: 15 14 13 12 11 10 9 0 indirect 1 1 0 bbbb 8 8 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 0 1 1 0 bbbb
see note 1
SYNTAX:
bit bit
dma7, bbbb *,bbbb((,nar)
EXECUTION:
(pc) + 1 pc (dma) ss(tb) 1 1(DI) 2(DE)
WORDS: CYCLES:
bs
branch immediate if bit set. BIT: 15 14 13 12 11 10 9 1 1 0 1 1 bbb 8 7 0 6 5 4 3 2 1 0
program memory address SYNTAX: EXECUTION: bbb, pma16 if ss(#1bbb)=1 then (pma) pc else (pc)+2 pc 2 3
WORDS: CYCLES:
32
INDEX
MX96037
bz
branch immediate if bit reset. BIT: 15 14 13 12 11 10 9 1 1 0 1 0 bbb 8 7 0 6 5 4 3 2 1 0
program memory address
SYNTAX:
bz
bbb, pma16
EXECUTION:
if ss(#1bbb)=0 then (pma) pc else (pc)+2 pc 2 3
WORDS: CYCLES:
cala
call subroutine indirect. BIT: 15 14 13 12 11 10 9 1 1 0 0 0 0 0 8 0 7 0 6 5 4 3 2 1 0
SYNTAX:
cala (pc)+1 (sp) (acc(31:16)) pc 1 2
EXECUTION:
WORDS: CYCLES:
33
INDEX
MX96037
call
subroutine . BIT: 15 14 13 12 11 10 9 1 1 1 1 1 1 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
16-bit constant
SYNTAX:
call
pma16
EXECUTION:
(pc)+1 (sp) (16-bit constant) pc 2 3 disable interrupt. Bit: 15 14 13 12 11 10 9 1 1 1 1 0 0 0 8 0 7 0 6 5 4 3 2 1 0
WORDS: CYCLES: dint
SYNTAX: EXECUTION:
dint (pc) + 1 pc 1 (INTM) status bit 1 1
WORDS: CYCLES:
34
INDEX
MX96037
eint
enable interrupt. Bit: 15 14 13 12 11 10 9 1 1 1 1 0 0 0 8 1 7 0 6 5 4 3 2 1 0
SYNTAX: EXECUTION:
eint (pc) + 1 pc 0 (INTM) status bit 1 1
WORDS: CYCLES:
in
input data from port. direct: 15 14 13 12 11 10 9 1 indirect: 0 1 0
port address
8 0 8 0
7 0 7 1
6
5
4
3
2
1
0
data memory address 6 5 4 3 2 1 0
15 14 13 12 11 10 9 1 0 1 0
port address
see note 1
SYNTAX:
in in
dma7,port *,port(,nar)
EXECUTION:
(pc) + 1 pc port address a2-a0 (IOPR(4:3)) a4-a3 0 a15-a6 (IOR) dma 1 1; note:only for internal memory
WORDS: CYCLES:
35
INDEX
MX96037
lac load acc. direct: 15 14 13 12 11 10 9 0 indirect: 0 0 0 1 1 1 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 0 0 1 1 1
see note 1
SYNTAX:
lac lac
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (dma) acc(31:16) 0 acc(15:0) 1 1(DI) 2(DE) load acc. short immediate. Bit: 15 14 13 12 11 10 9 0 0 0 0 1 1 1 8 1 7 0 6 5 4 3 2 1 0
WORDS: CYCLES: lack
7-bit sonstant
SYNTAX: EXECUTION:
lack
cnst7
(pc) + 1 pc (7-bit constant) acc(23:16) 0 acc(31:24) 0 acc(15:0) 1 1 load acc. Immediate Bit: 15 14 13 12 11 10 9 1 0 0 0 0 1 1 8 1 7 0 6 5 4 3 2 1 0
WORDS: CYCLES: lacl
16-bit constant
SYNTAX: EXECUTION:
lacl
cnst16
(pc) + 2 pc (16-bit constant) acc(31:16) 0 acc(15:0) 2 2
WORDS: CYCLES:
36
INDEX
MX96037
lar
load auxiliary register. direct: 15 14 13 12 11 10 9 0 indirect: 1 1 1 arp
8 0 8 0
7 0 7 1
6
5
4
3
2
1
0
data memory address 6 5 4 3 2 1 0
15 14 13 12 11 10 9 0 1 1 1 arp
see note 1
SYNTAX:
lar lar
dma7, arp *,arp(,nar)
EXECUTION:
(pc) + 1 pc (dma) (ar) 1 1(DI) 2(DE) ; no manipulation on ars
WORDS: CYCLES:
lark
load auxiliary register short immediate. Bit: 15 14 13 12 11 10 9 0 1 1 1 arp 8 1 7 0 6 5 4 3 2 1 0
7-bit constant
SYNTAX: EXECUTION:
lark
cnst7, arp
(pc) + 1 pc (7-bit constant) (ar(6:0)) 0 ar(15:7) 1 1
WORDS: CYCLES:
37
INDEX
MX96037
larl load auxiliary register immediate. Bit: 15 14 13 12 11 10 9 8 1 0 0 0 1 0 0 0 8 7 0 7 6 6 5 arp 5 4 4 3 0 3 2 0 2 1 0 1 0 0 0
15 14 13 12 11 10 9
16-bit constant SYNTAX: EXECUTION: larl cnst16, arp
(pc) + 2 pc (16-bit constant) ar (15:0) 2 2
WORDS: CYCLES:
ldp
load data-page register. direct: 15 14 13 12 11 10 9 0 indirect: 0 0 1 0 1 0 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 0 1 0 1 0
see note 1
SYNTAX:
ldp ldp
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (dma(3:0)) (dp(3:0)) 1 1(DI) 2(DE) load short immediate to datapage register. Bit: 15 14 13 12 11 10 9 0 0 0 1 0 1 0 8 1 7 0 6 x 5 x 4 x 3 2 1 0
WORDS: CYCLES: ldpk
4-bit constant
SYNTAX: EXECUTION:
ldpk
cnst4
(pc) + 1 pc (4-bit constant) (dp(3:0)) 1 1
WORDS: CYCLES:
38
INDEX
MX96037
lip
load io page register direct: 15 14 13 12 11 10 9 0 indirect: 0 0 1 0 0 1
8 0 8 0
7 0 7 1
6
5
4
3
2
1
0
data memory address 6 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 0 1 0 0 1
see note 1
SYNTAX:
lip lip
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (dma) (iop(1:0)) 1 1(DI) 2(DE)
WORDS: CYCLES:
lipk
load iopage register with short immediate. Bit: 15 14 13 12 11 10 9 0 0 0 1 0 0 1 8 1 7 0 6 x 5 x 4 3 2 1 x 0 x
s1 s0 x
SYNTAX: EXECUTION:
lipk
cnst2
(pc) + 1 pc s1 iop(1), s0 iop(0) 1 1
WORDS: CYCLES:
39
INDEX
MX96037
lup
loop instruction. direct: 15 14 13 12 11 10 9 0 indirect: 1 0 1
loop number
8 0 8 0
7 0 7 1
6
5
4
3
2
1
0
data memory address 6 5 4 3 2 1 0
15 14 13 12 11 10 9 0 1 0 1
loop number
see note 1
SYNTAX:
lup lup
dma, lic *,lic(,nar)
EXECUTION:
(pc) + 1 pc (dma) (rc) (loop number) (loop counter) 1 1(DI) 2(DE); the next (loop number+1) words will be repeat (rc+1) times
WORDS: CYCLES:
lupk
load rc with 7-bit constant and enable loop operation. Bit: 15 14 13 12 11 10 9 0 1 0 1
loop number
8 1
7 0
6
5
4
3
2
1
0
7-bit constant
SYNTAX: EXECUTION:
lupk
cnst7, lic
(pc) + 1 pc (7-bit constant) (rc) (loop number) (loop counter) 1 1
WORDS: CYCLES:
40
INDEX
MX96037
lx
load x register. direct: 15 14 13 12 11 10 9 0 indirect: 0 1 0 0 0 0 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 1 0 0 0 0
see note 1
SYNTAX:
lx lx
dma7 *(,nar)
EXECUTION:
(pc) +1 pc (dma) (xr) 1 1(DI) 2(DE)
WORDS: CYCLES:
lxk
load short immediate to x register. Bit: 15 14 13 12 11 10 9 0 0 1 0 0 0 0 8 1 7 0 6 5 4 3 2 1 0
7-bit constant
SYNTAX:
lxk
cnst7
EXECUTION:
(pc) + 1 pc (7-bit constant) xr(6:0) 0 xr(15:0) 1 1
WORDS: CYCLES:
41
INDEX
MX96037
lxl
load immediate to x register. Bit: 15 14 13 12 11 10 9 1 0 0 0 1 0 1 8 0 7 0 6 5 4 3 2 1 0
16-bit constant SYNTAX: EXECUTION: lxl cnst16
(pc) + 2 pc (16-bit constant) (xr) 2 2
WORDS: CYCLES:
lxa
load x register and accumulate previous product. direct: 15 14 13 12 11 10 9 0 indirect: 0 1 1 1 1 0 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 1 1 1 1 0
see note 1
SYNTAX:
lxa lxa
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (dma) (xr) (acc)+(P) (acc) 1 1(DI) 2(DE)
WORDS: CYCLES:
42
INDEX
MX96037
lxak
load short immediate to x register and accumulate previous product. Bit: 15 14 13 12 11 10 9 0 0 1 1 1 1 0 8 1 7 0 6 5 4 3 2 1 0
7-bit constant
SYNTAX:
lxak
cnst7
EXECUTION:
(pc) + 1 pc (7-bit constant) xr(6:0) 0 xr(15:8) (acc)+(p) acc 1 1
WORDS: CYCLES:
lxal
load immediate to x register and accumulate previous product. Bit: 15 14 13 12 11 10 9 1 0 0 0 1 0 1 8 1 7 0 6 5 4 3 2 1 0
16-bit constant SYNTAX: lxal cnst16
EXECUTION:
(pc) + 2 pc (16-bit constant) (xr) (acc)+(p) acc 2 2
WORDS: CYCLES:
43
INDEX
MX96037
lxs
load x register and subtract previous product. direct: 15 14 13 12 11 10 9 0 indirect: 0 1 1 0 1 0 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 1 1 0 1 0
see note 1
SYNTAX:
lxs lxs
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (dma) xr (acc)-(p) (acc) 1 1(DI) 2(DE) load short immediate to x register and subtract previous product. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 1 0 1 0 7-bit constant
WORDS: CYCLES: lxsk
0
SYNTAX:
lxsk
cnst7
EXECUTION:
(pc) + 1 pc (7-bit constant) xr(6:0) 0 xr(15:8) (acc)- (p) acc 1 1
WORDS: CYCLES:
44
INDEX
MX96037
lxsl
load immediate to x register and subtract previous product. Bit: 15 14 13 12 11 10 9 1 0 0 0 1 1 0 8 1 7 0 6 5 4 3 2 1 0
16-bit constant SYNTAX: lxsl cnst16
EXECUTION:
(pc) + 2 pc (16-bit constant) (xr) (acc)- (p) acc 2 2
WORDS: CYCLES:
lxm
load x register and store p register to acc. direct: 15 14 13 12 11 10 9 0 indirect: 0 1 1 1 1 1 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 1 1 1 1 1
see note 1
SYNTAX:
lxm lxm
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (dma) (xr) (p) (acc) 1 1(DI) 2(DE)
WORDS: CYCLES:
45
INDEX
MX96037
lxmk load short immediate to x register and store p register to acc. Bit: 15 14 13 12 11 10 9 0 SYNTAX: EXECUTION: lxmk 0 1 1 1 1 1 8 1 7 0 6 5 4 3 2 1 0
7-bit constant
cnst7
(pc) + 1 pc (7-bit constant) xr(6:0) 0 xr(15:8) (p) acc 1 1 load immediate to x register and store p register to acc. Bit: 15 14 13 12 11 10 9 1 0 0 0 1 1 0 8 0 7 0 6 5 4 3 2 1 0
WORDS: CYCLES: lxml
16-bit constant SYNTAX: lxml cnst16
EXECUTION:
(pc) + 2 pc (16-bit constant) (xr) (p) acc 2 2 multiply and accumulate previous product. Bit: 15 14 13 12 11 10 9 0 0 1 1 1 0 0 8 0 7 0 6 0 5 r 4 i 3 0 2 1 0
WORDS: CYCLES: mba
note 2
SYNTAX:
mba
riB,*
EXECUTION:
(pc) + 1 pc (acc)+(p) acc (Mb0(addressed by arp(7:1)*(r)))*(mb1(addressed by arb(7:1)*(i)))p 1 1; note: r=0/1, i=0/1
46
WORDS: CYCLES:
INDEX
MX96037
mbs
multiply and subtract previous product. Bit: 15 14 13 12 11 10 9 0 0 1 1 0 0 0 8 0 7 0 6 0 5 r 4 i 3 0 2 1 0
note 2
SYNTAX:
mbs
ri,*
EXECUTION:
(pc) + 1 pc (acc)-(p) acc (mb0(addressed by arb(7:1). (r)))* (mb1(addressed by arb(7:1). (i))) (p) 1 1; note : r=0/1, i=0/1
WORDS: CYCLES:
mar
modify auxiliary register. indirect: 15 14 13 12 11 10 9 1 1 1 1 0 1 1 8 0 7 1 6 5 4 3 2 1 0
see note 1
SYNTAX:
MAR
*(,nar)
EXECUTION:
(pc) + 1 pc modifies arp, ar(arp) as specified by the indirect addressing field 1 1
WORDS: CYCLES:
47
INDEX
MX96037
mod
load modulo register. direct: 15 14 13 12 11 10 9 0 indirect 0 0 1 0 1 1 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 0 1 0 1 1
see note 1
SYNTAX:
mod mod
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (dma(6:0)) mr(6:0) 1 1(DI) 2(DE)
WORDS: CYCLES:
modk
load modulo register short immediate. Bit: 15 14 13 12 11 10 9 0 0 0 1 0 1 1 8 1 7 0 6 5 4 3 2 1 0
7-bit constant
SYNTAX:
modk
cnst7
EXECUTION:
(pc) + 1 pc (7-bit constant) mr(6:0) 1 1
WORDS: CYCLES:
48
INDEX
MX96037
mpa
array multiplication. Bit: 15 14 13 12 11 10 9 1 1 0 0 1 1 1 8 0 7 1 6 5 4 3 2 1 0
see note 1
SYNTAX:
MPA
*(,nar)
EXECUTION:
(pc) + 1 sp (acc) (pc) 0 acc do begin (mb0(addressed by arb(7:0))) * (mb1(addressed by pc(7:0))) (p) (acc)+ (p) acc (rc) - 1 rc (pc) + 1 pc end ((rc) + 1) times (sp) pc 1 3+ (rc); enable repeat operation.
WORDS: CYCLES:
mb
ram_bank_0 multiply ram_bank_1. Bit: 15 14 13 12 11 10 9 0 0 1 0 0 1 0 8 0 7 0 6 0 5 r 4 i 3 0 2 1 0
note 2
SYNTAX:
mpc
ri,*
EXECUTION:
(pc) + 1 pc (mb0(addressed by arb(7:1) . (r))) * (mb1(addressed by arb(7:1) . (i))) (p) 1 1; note: r=0/1, i=0/1
WORDS: CYCLES:
49
INDEX
MX96037
mx
(x) multiply (dma) direct: 15 14 13 12 11 10 9 0 indirect: 0 1 0 0 0 1 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 1 0 0 0 1
see note 1
SYNTAX:
mx mx
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (x) * (dma) (p) 1 1(DI) 2(DE)
WORDS: CYCLES:
mxk
(x) multiply (7-bit constant). Bit: 15 14 13 12 11 10 9 0 0 1 0 0 0 1 8 1 7 0 6 5 4 3 2 1 0
7-bit constnat
SYNTAX:
mxk
cnst7
EXECUTION:
(pc) + 1 pc (x)* (7-bit constant) (p) 1 1
WORDS: CYCLES:
50
INDEX
MX96037
mxl
(x) multiply (16-bit constant). Bit: 15 14 13 12 11 10 9 1 0 0 0 1 1 1 8 0 7 0 6 5 4 3 2 1 0
16-bit constant
SYNTAX:
mxl
cnst16
EXECUTION:
(pc) + 1 pc (x) * (16-bit constant) (p) 2 2
WORDS: CYCLES:
mxa
(x) multiply (dma) and accumulate previous product. direct: 15 14 13 12 11 10 9 0 indirect: 0 1 1 1 0 1 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 1 1 1 0 1
see note 1
SYNTAX:
mxa mxa
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (acc) + (p) acc (x) * (dma) (p) 1 1(DI) 2(DE)
WORDS: CYCLES:
51
INDEX
MX96037
mxak
(x) multiply (7-bit constant) and accumulate previous product. Bit: 15 14 13 12 11 10 9 0 0 1 1 1 0 1 8 1 7 0 6 5 4 3 2 1 0
7-bit constant
SYNTAX: EXECUTION:
mxak
cnst7
(pc) + 1 pc (acc) + (p) acc (x) * (7-bit constant) (p) 1 1
WORDS: CYCLES:
mxs
(x) multiply (dma) and subtract previous product. direct: 15 14 13 12 11 10 9 0 indirect: 0 1 1 0 0 1 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 1 1 0 0 1
see note 1
SYNTAX:
mxs mxs
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (acc) - (p) acc (x) * (dma) (p) 1 1(DI) 2(DE)
WORDS: CYCLES:
52
INDEX
MX96037
mxsk (x) multiply (7-bit constant) and subtract previous product. Bit: 15 14 13 12 11 10 9 0 0 1 1 0 0 1 8 1 7 0 6 5 4 3 2 1 0
7-bit constant
SYNTAX:
mxsk
cnst7
EXECUTION:
(acc) - (p) acc (x) * (7-bit constant) (p) 1 1 no operation. Bit: 15 14 13 12 11 10 9 1 1 1 1 1 1 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
WORDS: CYCLES: nop
SYNTAX: EXECUTION: WORDS: CYCLES: or
nop (pc) + 1 pc 1 1 or with high acc. direct: 15 14 13 12 11 10 9 0 indirect: 0 0 0 1 0 0 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 0 0 1 0 0
see note 1
SYNTAX:
or or
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (acc(31:16)).or. (dma) (acc(31:16)) 1 1(DI) 2(DE)
WORDS: CYCLES:
53
INDEX
MX96037
ork
or short immediate with high acc. Bit: 15 14 13 12 11 10 9 0 0 0 0 1 0 0 8 1 7 0 6 5 4 3 2 1 0
7-bit constant
SYNTAX:
ork
cnst7
EXECUTION:
(pc) + 1 pc (acc(23:16) ).or. (7-bit constant) (acc(23:16) (acc(31:24)) acc(31:24) 1 1
WORDS: CYCLES:
orl
or immediate with high acc. Bit: 15 14 13 12 11 10 9 1 0 0 0 0 1 0 8 0 7 0 6 5 4 3 2 1 0
16-bit constant SYNTAX: EXECUTION: orl cnst16
(pc) + 2 pc (acc(31:16)) .or. (16-bit constant) (acc(31:16) 2 2
WORDS: CYCLES:
54
INDEX
MX96037
out
output data to port. direct: 15 14 13 12 11 10 9 0 indirect: 1 0 0 8 7 0 7 1 6 5 4 3 2 1 0
port address 0
data memory address 6 5 4 3 2 1 0
15 14 13 12 11 10 9 0 1 0 0
8
port address 0
see note 1
SYNTAX:
out out
dma7, port port *(,nar)
EXECUTION:
(pc) + 1 pc (pa) address bus a1-a0 (IOPR)(4:3) a4-a0 0 a15-a5 1 1;note: For internal memory only
WORDS: CYCLES:
outk
output short immediate to port. Bit: 15 14 13 12 11 10 9 0 1 0 0 8 7 0 6 5 4 3 2 1 0
port address 1
7-bit constant
SYNTAX:
outk
cnst7, port
EXECUTION:
(pc) + 1 pc (pa) address bus a2-a0 (IOPR)(4:3) a4-a3 0 a15-a5 (7-bit constant ) IOR (addressed by a4-a0) 1 1; note: For internal memory only
WORDS: CYCLES:
55
INDEX
MX96037
outl
output immediate to port. direct: 15 14 13 12 11 10 9 1 0 0 0 1 1 1 8 1 7 0 6 5 4 3 2 0 1 0 0 0
port address 0
16-bit constant SYNTAX: outl cnst16, port
EXECUTION:
(pc) + 1 pc (pa) address bus a2-a0 (IOPR)(4:3) a4-a3 0 a15-a5 (16-bit constant) IOR(addressed by a4-a0) 1 1;note: for internal memory only
WORDS: CYCLES:
pac
load acc. With p register Bit: 15 14 13 12 11 10 9 1 0 0 1 0 1 0 8 0 7 0 6 5 4 3 2 1 0
SYNTAX: EXECUTION:
pac (pc) + 1 pc (p) (acc) 1 1
WORDS: CYCLES:
56
INDEX
MX96037
poph pop top of stack to high accumulator. Bit: 15 14 13 12 11 10 9 1 SYNTAX: EXECUTION: poph (pc) + 1 pc (tos) acc(31:16) 1 1 pop top of stack to low accumulator. Bit: 15 14 13 12 11 10 9 1 SYNTAX: EXECUTION: popl (pc) + 1 pc (tos) acc(15:0) 1 1 pop top of stack to data memory. direct: 15 14 13 12 11 10 9 1 indirect: 0 1 1 0 1 0 8 1 8 1 7 0 7 1 6 5 4 3 2 1 0 0 0 1 1 0 1 8 1 7 0 6 5 4 3 2 1 0 0 0 1 0 1 0 8 0 7 0 6 5 4 3 2 1 0
WORDS: CYCLES: popl
WORDS: CYCLES: pop
data memory address 6 5 4 3 2 1 0
15 14 13 12 11 10 9 1 0 1 1 0 1 0
see note 1
SYNTAX:
pop pop
dma *(,nar)
EXECUTION:
(pc) + 1 pc (tos) dma 1 1(DI) 2(DE)
WORDS: CYCLES:
57
INDEX
MX96037
psh
push data memory value onto stack. direct: 15 14 13 12 11 10 9 1 indirect: 1 0 0 1 0 1 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 1 1 0 0 1 0 1
see note 1
SYNTAX:
psh psh
dma *(,nar)
EXECUTION:
(pc) + 1 pc dma (tos) 1 1
WORDS: CYCLES:
pshh
push high accumulator onto stack. Bit: 15 14 13 12 11 10 9 1 1 0 0 1 0 0 8 0 7 1 6 5 4 3 2 1 0
see note 1
SYNTAX:
pshh (pc) + 1 pc acc(31:16) (tos)
EXECUTION:
WORDS: CYCLES:
1 1
58
INDEX
MX96037
pshl
push low accumulator onto stack. Bits: 15 14 13 12 11 10 9 1 1 0 0 1 0 0 8 1 7 1 6 5 4 3 2 1 0
see note 1
SYNTAX:
pshl (pc) + 1 pc acc(15:0) (tos)
EXECUTION:
WORDS: CYCLES:
1 1
ret
return from subroutine. Bits: 15 14 13 12 11 10 9 1 1 1 1 1 0 0 8 0 7 0 6 5 4 3 2 1 0
SYNTAX:
ret (sp) pc sp-1 sp
EXECUTION:
WORDS: CYCLES:
1 2
59
INDEX
MX96037
reti
return from interrupt. Bit: 15 14 13 12 11 10 9 1 1 1 1 1 0 0 8 1 7 0 6 5 4 3 2 1 0
SYNTAX:
reti (sp) pc (sp)-1 sp (sp) ss sp-1 sp
EXECUTION:
WORDS: CYCLES:
1 2
rovm
reset overflow mode. Bit: 15 14 13 12 11 10 9 1 1 1 1 0 1 0 8 0 7 0 6 5 4 3 2 1 0
SYNTAX:
rovm (pc) + 1 pc 0 (ovm) status bit.
EXECUTION:
WORDS: CYCLES:
1 1
60
INDEX
MX96037
rpt
load repeat counter. direct: 15 14 13 12 11 10 9 0 0 0 1 0 0 0 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address
indirect:L
15 14 13 12 11 10 9 0 0 0 1 0 0 0
5
4
3
2
1
0
see note1
SYNTAX:
rpt rpt
dam7 *(,nar)
EXECUTION:
(pc) + 1 pc (dma) (rc)
WORDS: CYCLES:
1 1(DI) 2(DE)
rptk
load rc with 7-bit constant. direct: 15 14 13 12 11 10 9 0 0 0 1 0 0 0 8 1 7 0 6 5 4 3 2 1 0
7-bit constant
SYNTAX:
rptk
cnst7
EXECUTION:
(pc) + 1 pc (7-bit constant) (rc)
WORDS: CYCLES:
1 1
61
INDEX
MX96037
rxf
reset external flag. Bit: 15 14 13 12 11 10 9 1 1 1 1 0 0 1 8 0 7 0 6 5 4 3 2 1 0
SYNTAX:
rxf (pc) + 1 pc 0 (XF) pin and status bit.
EXECUTION:
WORDS: CYCLES:
1 1
sah
store high acc. direct: 15 14 13 12 11 10 9 1 indirect: 0 1 1 0 0 0 8 0 8 0 7 0 7 1 6 5 4 3 2 1 0
data memory address 6 5 4 3 2 1 0
15 14 13 12 11 10 9 1 0 1 1 0 0 0
see note 1
SYNTAX:
sah sah
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (acc(31:16)) (dma)
WORDS: CYCLES:
1 1(DI) 2(DE)
62
INDEX
MX96037
sal
store low acc. direct: 15 14 13 12 11 10 9 1 indirect: 0 1 1 0 0 0 8 1 8 1 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 1 0 1 1 0 0 0
see note 1
SYNTAX:
sal sal
dma7 *(,nar)
EXECUTION:
(pc) + 1 pc (acc(15:0)) (dma)
WORDS: CYCLES: sar
1 1(DI) 2(DE) store auxiliary register. direct: 15 14 13 12 11 10 9 1 indirect: 0 1 1 1 ar 8 8 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 1 0 1 1 1 ar
see note 1
SYNTAX:
sar sar
dma7, arp *, arp (,nar)
EXECUTION:
(pc)+1 pc (ar) (dma)
WORDS: CYCLES:
1 1(DI) 2(DE)
63
INDEX
MX96037
sbh
subtract from high acc. direct: 15 14 13 12 11 10 9 0 indirect: 0 0 0 0 1 0 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 0 0 0 1 0
see note 1
SYNTAX:
sbh sbh
dma7 *(,nar)
EXECUTION:
(pc) +1 pc (acc(31:16)) - (dma) (acc(31:16))
WORDS: CYCLES:
1 1(DI) 2(DE)
sbhk
subtract short immediate from high acc. Bit: 15 14 13 12 11 10 9 0 0 0 0 0 1 0 8 1 7 0 6 5 4 3 2 1 0
7-bit constant
SYNTAX:
sbhk
cnst7
EXECUTION:
(pc)+1 pc (acc(31:16)) - (7-bit constant) (acc(31:16))
WORDS: CYCLES:
1 1
64
INDEX
MX96037
sbhl
subtract immediate from high acc. Bit: 15 14 13 12 11 10 9 1 0 0 0 0 0 1 8 0 7 0 6 5 4 3 2 1 0
16-bit constant
SYNTAX:
sbhl
cnst16
EXECUTION:
(pc)+2 pc (acc(31:16)) - (16-bit constant) (acc(31:16))
WORDS: CYCLES:
2 2
sbl
subtract from low acc. direct: 15 14 13 12 11 10 9 0 indirect: 0 0 0 0 1 1 8 0 8 0 7 0 7 1 6 5 4 3 2 1 0
data memory address 6 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 0 0 0 1 1
see note 1
SYNTAX:
sbl sbl
dma7 *(,nar)
EXECUTION:
(pc)+1 pc (acc) - (dma with optional MSBs sign extension*) (acc)
WORDS: CYCLES:
1 1(DI) 2(DE) ; note : Option is controlled by CTRL : SENSE bit
65
INDEX
MX96037
sblk
subtract short immediate from low acc. Bit: 15 14 13 12 11 10 9 0 0 0 0 0 1 1 8 1 7 0 6 5 4 3 2 1 0
7-bit constant
SYNTAX:
sblk
cnst7
EXECUTION:
(pc)+1 pc (acc) - (7-bit constant) (acc)
WORDS: CYCLES:
1 1
sbll
subtract immediate from low acc. Bit: 15 14 13 12 11 10 9 1 0 0 0 0 0 1 8 1 7 0 6 5 4 3 2 1 0
16-bit constant
SYNTAX:
sbll
cnst16
EXECUTION:
(pc)+2 pc (acc) - (16-bit constant with optional MSBs sign extension*) (acc)
WORDS: CYCLES:
2 2 ; note:Option is controlled by CTRL: SENSE bit
66
INDEX
MX96037
sdp
store data_page register. direct: 15 14 13 12 11 10 9 1 indirect: 0 1 1 0 1 0 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 1 0 1 1 0 1 0
see note 1
SYNTAX:
sdp sdp
dma7 *(,nar)
EXECUTION:
(pc)+1 pc (dp) (dma)
WORDS: CYCLES:
1 1(DI) 2(DE)
sfl
shift acc left. Bit: 15 14 13 12 11 10 9 1 0 0 1 1 1 0 8 1 7 0 6 0 5 0 4 0 3 2 1 0
shift
SYNTAX:
sfl
cnst4
EXECUTION:
(pc)+1 pc if (shift>< 0) then acc * (2** shift) acc else acc*(2**(sv(3:0))) acc 1 1 ; note:15-bit overflow protection.
WORDS: CYCLES:
67
INDEX
MX96037
sfr/sfrs
shift acc right. Bit: 15 14 13 12 11 10 9 1 0 0 1 1 1 1 8 0 7 0 6 0 5 0 4 s 3 2 1 0
shift
SYNTAX:
sfr sfrs
cnst4 cnst4
EXECUTION:
(pc)+1 pc if (shift>< 0) then acc * (2**( -shift)) acc else acc*(2**(-sv(3:0)) acc * s=0 the msbs zero-filled * s=1 the msbs sign-extended 1 1
WORDS: CYCLES:
sip
store io_page register direct: 15 14 13 12 11 10 9 1 indirect: 0 1 1 0 0 1 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 1 0 1 1 0 0 1
see note 1
SYNTAX:
sip sip
dma7 *(,nar)
EXECUTION:
(pc)+1 pc IOPR(4:3) (dma (1:0)) 1 1(DI) 2(DE)
WORDS: CYCLES:
68
INDEX
MX96037
sovm
set overflow mode. Bit: 15 14 13 12 11 10 9 1 1 1 1 0 1 0 8 1 7 0 6 5 4 3 2 1 0
SYNTAX:
sovm (pc)+1 pc 1 (OVM) status bit. 1 1
EXECUTION:
WORDS: CYCLES:
spac
subtract p register from acc. Bit: 15 14 13 12 11 10 9 1 0 0 1 0 1 1 8 0 7 0 6 5 4 3 2 1 0
SYNTAX:
spac (pc)+1 pc (acc) - (p) acc 1 1
EXECUTION:
WORDS: CYCLES:
69
INDEX
MX96037
sqra sqra and accumulate previous product. Bit: 15 14 13 12 11 10 9 1 1 1 1 1 0 1 8 1 7 1 6 5 4 3 2 1 0
see note 1
SYNTAX:
sqra sqra
dma7 *(,nar)
EXECUTION:
0 acc do begin (dma) * (dma) (p) (acc)+(p) acc (rc) - 1 rc (pc) +1 pc end ((rc) + 1) times 1 3+ (rc) ; enable repeat operation.
WORDS: CYCLES:
sss
store ss register. direct: 15 14 13 12 11 10 9 1 indirect: 0 1 1 0 0 1 8 1 8 1 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 1 0 1 1 0 0 1
see note 1
SYNTAX:
sss sss
dma7 *(,nar)
EXECUTION:
(pc)+1 pc (ss) (dma)
WORDS: CYCLES:
1 1(DI) 2(DE)
70
INDEX
MX96037
sxf
set external flag. Bit: 15 14 13 12 11 10 9 1 1 1 1 0 0 1 8 1 7 0 6 5 4 3 2 1
SYNTAX:
sxf (pc)+1 pc 1 (XF) pin and status bit.
EXECUTION:
WORDS: CYCLES:
1 1
tbr
table read. direct: 15 14 13 12 11 10 9 1 indirect: 1 0 0 1 1 0 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 1 1 0 0 1 1 0
see note 1
SYNTAX:
tbr
*(,nar)
EXECUTION:
(pc)+1 sp (acc) pc do ((pma, addressed by pc) dma)) ((rc) +1)) times (sp)pc
WORDS: CYCLES:
1 3+(rc) ; enable repeat operation.
71
INDEX
MX96037
trap
software interrupt. Bit: 15 14 13 12 11 10 9 1 1 0 0 0 0 1 8 0 7 0 6 5 4 3 2 1 0
SYNTAX:
trap (pc)+1 sp 0c pc 1 2
EXECUTION:
WORDS: CYCLES:
xor
xor with high acc. direct: 15 14 13 12 11 10 9 0 indirect: 0 0 0 1 1 0 8 0 8 0 7 0 7 1 6 6 5 4 3 2 1 0
data memory address 5 4 3 2 1 0
15 14 13 12 11 10 9 0 0 0 0 1 1 0
see note 1
SYNTAX:
xor xor
dma7 *(,nar)
EXECUTION:
(pc)+1 pc (acc(31:16)) .xor. (dma) (acc(31:16) 1 1(DI) 2(DE)
WORDS: CYCLES:
72
INDEX
MX96037
xork xor short immediate with high acc. Bit: 15 14 13 12 11 10 9 0 0 0 0 1 1 0 8 1 7 0 6 5 4 3 2 1 0
7-bit constant
SYNTAX:
xork
cnst7
EXECUTION:
(pc)+1 pc (acc(23:16)) .xor. (7-bit constant) (acc(23:16)) (acc(31:24)) acc(31:24)
WORDS: CYCLES:
1 1
xorl
xor short immediate with high acc. Bit: 15 14 13 12 11 10 9 1 0 0 0 0 1 1 8 0 7 0 6 5 4 3 2 1 0
16-bit constant
SYNTAX:
xorl
cnst16
EXECUTION:
(pc)+2 pc (acc(31:16)) .xor. (16-bit constant) (acc(31:16))
WORDS: CYCLES:
2 2
73
INDEX
MX96037
* note 1 : 15 14 13 12 11 10 9 8 7 1 6 v 5 v 4 v 3 v 2 1 y 0
opcode
operation:
case(vvvv) 0000: no manipulation of ars/arp 0001: y arp 0010: ar(arp) - ar0 ar(arp) 0011: ar(arp) - ar0 ar(arp), y arp 0100: ar(arp) + ar0 ar(arp) 0101: ar(arp) + ar0 ar(arp), y arp 1000: ar(arp) +1 ar(arp) 1001: ar(arp) +1 ar(arp), y arp 1010: ar(arp) - 1 ar(arp) 1011: ar(arp) -1 ar(arp), y arp 1100: ar(arp) +2 ar(arp) 1101: ar(arp) +2 ar(arp), y arp 1110: ar(arp) -2 ar(arp) 1111: ar(arp) -2 ar(arp), y arp
operand: +0 + 0 ,y - ARO - ARO , y + ARO + ARO , y + +,y -,y ++ ++ , y --- , y
* note 2 : 15 14 13 12 11 10 9 8 7 6 5 4 3 x 2 y 1 y 0 y
opcode
operation:
case(yyy) 000: no operation on ar(arp) 001: ar(arp) - ar0 ar(arp) 010: ar(arp) + ar0 ar(arp) 111: reserved 100: ar(arp) +1 ar(arp) 101: ar(arp) -1 ar(arp) 110: ar(arp) +2 ar(arp) 111: ar(arp) -2 ar(arp)
74
INDEX
MX96037
DC CHARACTERISTICS: TA = 0 to 70 C, VCC = 5V 10%
SYMBOL PARAMETER VCC VOL VOH VOL VIH Supply voltage Supply voltage Output high voltage Output low voltage Input high voltage BIO(7:0), ED(15:0), HOLD\, EROM(schmite-trigger) 3.5 all others VIL Input low voltage BIO(7:0), ED(15:0), HOLD\, EROM(schmite-trigger) -0.1 all others IOLA IOLB IOLC IOHA IOHB IOHC ICC Output low current type A Output low current type B Output low current type C Supply high current (HOLD\) Supply high current(HOLD\) Supply high current(HOLD\) Supply current(HOLD\) 4 4 16 2 2 8 10 OA OB OC 2.0 1.5 0.8 MIN 4.5 TYPE 5 0 4 0.3 0.6 MAX 5.5 UNIT V V V V V V V V mA mA mA mA mA mA mA
AC CHARACTERISTICS:
ROM/RAM/IO READ/WRITE TIMING
SYMBOL Tcs Taa Trds Twds Tdh Tah Ts(a-w) Ts(a-r) PARAMETER Chip select access time (ROM, RAM, IO) Address access time (ROM, RAM, IO) Data set-up time before ERD\ high (ROM, RAM, IO) Data set-up time before EWR\ high (ROM, RAM, IO) Data hold time after ERD\/EWR\ high (ROM, RAM, IO) Address hold time after ERD\/EWR\ high (ROM, RAM, IO) Address set-up time before EWR\ Address set-up time before ERD\ MIN 25+wTc 25+wTc 12 12 0 0 0-5 NOM MAX UNIT ns ns ns ns ns ns ns
0-5
ns NOM MAX 10 UNIT ns
OUTPUT PORTS AND EXTERNAL FLAG (XF\) TIMING
SYMBOL Td (a-o) PARAMETER Address to output ports (xf\) delay time MIN 0
RESET TIMING
SYMBOL Tw (rst) PARAMETER Reset low pulse width MIN 3Tc NOM MAX UNIT
75
INDEX
MX96037
AC CHARACTERISTICS: (Continued)
CLOCK TIMING
SYMBOL Tc(c) Tlpd(c) Thpd(c) Td(c-m) PARAMETER CLKIN cycle time CLKIN low pulse duration(tc=30ns) CLKIN high pulse duration (tc=30ns) CLKIN to MCO delay time MIN 30 12 12 0 NOM MAX 42 18 18 15 UNIT ns ns ns ns
CODEC TRANSMIT AND RECEIVE TIMING
SYMBOL Tc (mck) Tlpd (mck) Thpd (mck) Td (ch-fs) Td (ch-dx) Ts (dr) Th (dr) PARAMETER MCK cycle time MCK low pulse duration MCK high pulse duration MCK to FS delay time DX valid after MCK rising edge DR set-up time before MCK falling edge DR hold time before MCK falling edge 10 10 315 315 MIN NOM 650 335 335 20 10 MAX UNIT ns ns ns ns ns ns ns
INTERRUPT TIMING
SYMBOL Tw Tf Ts (int) PARAMETER INT\ low pulse duration INT\ fall time INT\ set-up time before MCO falling edge 5 MIN 3Q* NOM MAX 10 10 3Q-5 UNIT ns ns ns
HOLD\TIMING
SYMBO Ts (a-h) Tdt Td(al-a) Td (hh-ha) Ten (ah-a) PARAMETER Address set-up time before HOLD\ low Address tri-state after MCO low HOLDA\ low to address tri-state HOLD\ high to HOLDA\ high Address driven after HOLDA\ high MIN 5 1Q-5 0 0 1Q-10 1Q 1Q 1Q+10 2Q ns ns NOM MAX 3Q-10 1Q+10 UNIT ns ns
76
INDEX
MX96037
SRAM/ROM READ TIMING
Tcs
Th(ce-a)
EDCE\,EPCE\
Taa
EAD15-EAD0
Ts(a-r)
VALID Ts(rd-d)
ERD\
Th(rd-d)
ED15-ED0
DATA IN
SRAM/WRITE TIMING
EDEC\
Td(ce-a)
EAD15-EAD0
VALID
Ts(a-w)
Th(a-w) Th(d-w)
EWR\
Twds
ED15-ED0
DATA OUT
77
INDEX
MX96037
AC CHARACTERISTIC: (Continued)
DRAM TIMING
SYMBO Tras Trp Trcd Tcas Tcp Tasr Trah Tasc Qah Td(rd-c) Td(wr-c) Ts(cas) Th(cas) Ts(w-ca) Th(w-ca) PARAMETER RAS\low pulse duration RAS\ precharge time RAS\ to CAS\ delay time CAS\ low pulse duration CAS\ precharge time Row address set-up time Row address hold time Column address hold time Column address hold time DRD\ low to CAS\ low DWR\ low to CAS\low Data set-up time before CAS\ high Data hold time after CAS\high Data set-up time before CAS\low Data hold time before CAS\low MIN 10Q-10 7Q-10 4Q-10 6Q-10 2Q-5 1Q-10 3Q-10 6Q-10 6Q-10 1Q-10 1Q-10 1Q 5 1Q-10 4Q-10 4Q NOM 10Q 7Q 4Q 6Q 2Q 1Q 3Q 1Q 6Q 1Q 1Q MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
UP INTERFACE
SYMBOL Thra Thdh Thsw Thwh PARAMETER Host read access time Read data hold time Write data set up time Write data hold time 5 20 10 MIN MON 50 MAX UNIT ns ns ns ns
Note:*w=number of wait state *Q=1/2 TC
78
INDEX
MX96037
DRAM READ/WRITE TIMING
Tras
Trp
RAS\
Trcd
Tcas
Tcp
CAS\
Tasr Trah Tasc
ROW ADDRESS COLUMN ADDRESS
Tach
EAD15-EAD0
COLUMN ADDRESS
DRD\
Td(rd-c)
Ts(cas)
Th(cas)
DATA IN DATA IN
ED15-ED0 READ CYCLE
Td(wr-c)
DWR\
Ts(w-ca) Th(w-ca)
DATA OUT
ED15-ED0 WRITE CYCLE
CODEC PORT TRANSMIT AND RECEIVE TIMING
Tc(mck)
Tw(mck)
CMCK
Td(ch-fs) Td(ch-fs) Th(dr) Tw(mck)
CFS
Ts(dr)
CDR0, CDR1
N=1 Td(ch-dx)
N=2
N=3
N=4
SAMPLING 16 BITS
CDX0, CDX1
N=1
N=2
N=3
N=4
TRANSMIT 16 BITS
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INDEX
MX96037
CODEC TRANSMIT RECEIVE OPERATION
CMCK
CDX0, CDR0
D15 MSB D14 D13 D12 D1 D0 LSB
CFS
Internal Codec Interrupt
80
INDEX
MX96037
OUTPUT PORT AND EXTERNAL FLAG(XF\) TIMING
AD15-AD0 EAD15-EAD0
PC=N, SXF/RXF or OUT XX
PC=N+1
PC=N+2 Td(a-o)
OPT12-OP10
XF\
P INTERFACE TIMING
P READ CYCLE
PHRDB\
Tsr
Thr
PHILO
PHDB[7:0]
DATA VALID
DATA VALID
PACKB\
P WRITE CYCLE
PHWRB\
Tsw
Tww
PHILO
Thw PHDB[7:0] DATA VALID DATA VALID
PACKB\
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INDEX
MX96037
RESET TIMING
CLK IN
Tw(rst)
RST\
ADDRESS BUS
PC=0000
0001
DATA BUS CONTROL SIGNALS CODEC SIGNAL OUTPUT PORT
(inactive)
valid
valid
0000
BIO PORT
Note: Control Signals XF\ HOLDA\ EDCE\EPCE\ ERD\ ERD\ EWR\ CAS\ RAS\ DRD\ DWR\
82
INDEX
MX96037
HOLD TIMING
MCO0
EAD15-EAD0
N
N+1
N+2 Tdt
N+3 Ten(ah-a)
N+4
ED15-ED0 EPCE\ EDCE\ EWR\ ERD\
Ts(a-h) Tdt
Tdt
HOLD\
Td(hh-ha)
HOLDA\
Td(a-al)
INTERRUPT TIMING
Tf
INT0\ INT1\ INT2\
Tw
Ts(v)
MCO
AD15-AD0
fetch N+0
fetch N+1
fetch N+1
fetch N+1
fetch I
83
INDEX
MX96037
TIMING WAVEFORMS
CLOCK TIMING
Tc(c)
Thpd(c)
CLK IN
Td(c-m) Tlpd(c)
MCO (no wait state)
MCO (1 wait state)
MCO (2 wait state)
MCO (3 wait state)
84
INDEX
MX96037
ORDERING INFORMATION
PART NO. MX96037 PACKAGE PQFP
MX
MXIC COMPONY PREFIX
96
037
F
C
COMMERCIAL 0 ~ 70C
FAMILY PREFIX
PACKAGE TYPE F : PQFP Q : PLCC
PRODUCT NUMBER
85
INDEX
MX96037
PACKAGE INFORMATION
100-PIN PQFP
A
ITEM A B C D E F G H I J K L M N O P
MILLIMETERS 24.80 .40 20.00 .13 14.00 .13 18.80 .40 12.35 [REF] .83 [REF] .58 [REF] .30 [Typ.] .65[Typ.] 2.40 [Typ.] 1.20 [Typ.] .15 [Typ.] .10 max. 2.75 .15 .10 min. 3.30 max.
INCHES .967 .016 .787 .005 .551 .005 .740 .016 .486 [REF] .033 [REF] .023 [REF] .012 [Typ.] .026 [Typ.] .094 [Typ.] .047 [Typ.] .006 [Typ.] .004 max. .018 .006 .004 min. .103 max.
G H I J O F 100 1 31 30 P E C D 80 81 51 50 B
NOTE: Each lead centerline is located within .25mm[.01 inch] of its true position [TP] at a maximum material condition.
N L M K
86
INDEX
MX96037
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS: No. 3, Creation Road III, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. TEL : +886-3-578-8888 FAX: +886-3-578-8887 TAIPEI OFFICE: 12F, No. 4, Min-Chuan E. Rd., Sec. 3, Taipei, Taiwan, R.O.C. TEL : +886-2-509-3300 FAX: +886-2-509-2200 EUROPE OFFICE: Grote Winkellaan 95, Bus 1 1853 Strombeek, Belgium TEL : +32-2-267-7050 FAX: +32-2-267-9700 SINGAPORE OFFICE: 5 Jalan Masjid Kembangan Court #01-12 Singapore 418924 TEL : +65-747-2309 FAX: +65-748-4090
MACRONIX AMERICA, INC.
1338 Ridder Park Drive, San Jose, CA95131 U.S.A. TEL : +1-408-453-8088 FAX: +1-408-453-8488 JAPAN OFFICE: NFK Kawasaki Building, 8F, 1-2 Higashida-cho, Kawasaki-ku Kawasaki-shi, Kawasaki-ken 210, Japan TEL : +81-44-246-9100 FAX: +81-44-246-9105
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
87

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