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PSD4000 FAMILY
Flash Programmable System Devices For 16-bit MCUs
DATA BRIEFING
FEATURES SUMMARY Members of the PSD4000 Family provide an integrated solution to 16-bit MCU based applications that includes configurable memories, PLD logic and I/O: s Dual Bank Flash Memories - 4 or 8 Mbit of Primary Flash Memory - 256 or 512 Kbit Secondary Flash Memory - Concurrent operation: read from one memory while erasing and writing the other
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Figure 1. Packages
64 or 256 Kbit SRAM (Battery Backed) PLD with Macrocells - Over 3000 Gates of PLD: CPLD and DPLD - CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs) - DPLD - user defined internal chip select decoding
TQFP80 (U)
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Seven l/O Ports with 52 I/O pins - 52 individually configurable I/O port pins that can be used for the following functions: - MCU I/Os - PLD I/Os - Latched MCU address output - Special function l/Os - l/O ports may be configured as open-drain outputs
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Programmable power management High Endurance: - 100,000 Erase/Write Cycles of Flash Memory - 1,000 EraseWrite Cycles of PLD - 15 Year Data Retention
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In-System Programming (ISP) with JTAG - Built-in JTAG compliant serial port allows fullchip In-System Programmability - Efficient manufacturing allow easy product testing and programming - Use low cost FlashLINK cable with PC
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Single Supply Voltage - 5V (10%) - 3.3V (10%)
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Page Register - Internal page register that can be used to expand the microcontroller address space by a factor of 256
October 2001
Complete data available on Data-on-Disc CD-ROM or at www.st.com.
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PSD4000 FAMILY
SUMMARY DESCRIPTION The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications. PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices. The PSD family offers two methods to program the PSD Flash memory while the PSD is soldered to the circuit board: In-System Programming (ISP) via JTAG, and In-Application Programming (IAP). In-System Programming (ISP) via JTAG An IEEE 1149.1 compliant JTAG In-System Programming (ISP) interface is included on the PSD enabling the entire device (Flash memories, PLD, configuration) to be rapidly programmed while soldered to the circuit board. This requires no MCU participation, which means the PSD can be programmed anytime, even when completely blank. The innovative JTAG interface to Flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as: s First time programming. Program blank Flash PSDs directly on the circuit board. Inventory build-up of pre-programmed devices. Build your hardware with blank PSDs soldered directly to the board and then custom program just before they are shipped to the customer. No more labels on chips, and no more wasted inventory. Expensive sockets. Solder the PSD directly to the circuit board. Program first time and subsequent times with JTAG. No need to handle devices and bend the fragile leads.
In-Application Programming (IAP) Two independent Flash memory arrays are included so that the MCU can execute code from one while erasing and programming the other. Robust product firmware updates in the filed are possible over any communication channel (CAN, Ethernet, UART, J1850, etc) using this unique architecture. Designers are relieved of these problems: s Simultaneous read and write to Flash memory. The PSD allows the MCU to operate the two Flash memory blocks concurrently, reading code from one while erasing and programming the other during IAP. Complex memory mapping. A programmable Decode PLD (DPLD) is embedded in the PSD. The concurrent PSD memories can be mapped anywhere in MCU address space, segment by segment with extermely high address resolution. As an option, the secondary Flash memory can be swapped out of the system memory map when IAP is complete. A built-in page register breaks the MCU address limit. Separate Program and Data space.
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The PSD provides means to reclassify Flash memory as Data space during IAP, then back to Program space when complete. This solves an inherint problem with concurrent programming in 8051 based designs. PSDsoft Express PSDsoft Express, a software development tool from ST, guides you through the design process step-by-step making it possible to complete an embedded MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft Express takes you through the remainder of the design with point and click entry, covering PSD selection, pin definitions, programmable logic inputs and outpus, MCU memory map definition, ANSI-C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft Express: FlashLINK (JTAG) and PSDpro.
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ADDRESS/DATA/CONTROL BUS
PLD INPUT BUS PAGE REGISTER EMBEDDED ALGORITHM 16 SECTORS 8 MBIT PRIMARY FLASH MEMORY
POWER MANGMT UNIT
VSTDBY (PE6 )
8
CNTL0, CNTL1, CNTL2 SECTOR SELECTS FLASH DECODE PLD (DPLD) 82 SECTOR SELECTS SRAM SELECT ADIO PORT CSIOP RUNTIME CONTROL AND I/O REGISTERS 8 EXT CS TO PORT C or F 16 OUTPUT MACROCELLS PORT A & B 24 INPUT MACROCELLS CLKIN PROG. PORT PORT G CLKIN MACROCELL FEEDBACK OR PORT INPUT PORT F PORT A ,B & C PERIP I/O MODE SELECTS 256 KBIT BATTERY BACKUP SRAM PROG. MCU BUS INTRF. 512 KBIT SECONDARY FLASH MEMORY (BOOT OR DATA) 4 SECTORS
Figure 2. PSD4256G6 Block Diagram
PA0 - PA7 PORT A
Figure 2 shows the block diagram for the PSD42xx family (specifically, the PSD4256G6). The PSD41xx family has a similar block diagram, but
PROG. PORT PROG. PORT PORT F 82 FLASH ISP CPLD (CPLD) PROG. PORT PORT B PB0 - PB7 PROG. PORT PORT C PC0 - PC7 PROG. PORT PORT D PD0 - PD3 CLKIN GLOBAL CONFIG. & SECURITY PLD, CONFIGURATION & FLASH MEMORY LOADER JTAG SERIAL CHANNEL PROG. PORT PORT E PE0 - PE7
AD0 - AD15
Note: Additional address lines can be brought in to the device via Port A, B, C, D or F.
PF0 - PF7
PG0 - PG7
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with a simpler General Purpose PLD in place of the Complex PLD (CPLD).
PSD4000 FAMILY
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PSD4000 FAMILY
PSD ARCHITECTURAL OVERVIEW PSD devices contain several major functional blocks. Figure 2 shows the architecture of the PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. Memory Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discussion can be found in the data sheet. s The 4 or 8 Mbit primary Flash memory is the main memory of the PSD. It is divided into 16 equally-sized sectors that are individually selectable.
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I/O Ports The PSD has 52 I/O pins divided among seven ports (Port A, B, C, D, E, F and G). Each I/O pin can be individually configured for different functions. Ports can be configured as standard MCU I/ O ports, PLD I/O, or latched address outputs for MCUs using multiplexed address/data buses The JTAG pins can be enabled on Port E for InSystem Programming (ISP). Table 1. PLD I/O
Name Decode PLD (DPLD) Complex PLD (CPLD) Inputs 82 82 Outputs 17 24 Product Terms 43 150
The 256 or 512 Kbit secondary Flash memory is divided into 4 equally-sized sectors that are individually selectable. The 64 or 256 Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the MCU SRAM. If an external battery is connected to the PSD's Voltage Stand-by (VSTBY, PE6) signal, data is retained in the event of power failure.
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Each memory block can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time. PLDs The device contains two PLD blocks, the Decode PLD (DPLD) and the Complex PLD (CPLD), as shown in Table 1, each optimized for a different function. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. The DPLD is used to decode addresses and to generate Sector Select signals for the PSD internal memory and registers. The DPLD has combinatorial outputs, while the CPLD can implement more general user-defined logic functions. The CPLD has 16 Output Macrocells (OMC) and 8 combinatorial outputs. The PSD also has 24 Input Macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations, number of product terms, and Macrocells. The PLDs consume minimal power. The speed and power consumption of the PLD is controlled by the Turbo bit in PMMR0 and other bits in PMMR2. These registers are set by the MCU at run-time. There is a slight penalty to PLD propagation time when not in the Turbo mode.
MCU Bus Interface The PSD easily interfaces easily with most 16-bit MCUs, either with multiplexed or non-multiplexed address/data buses. The device is configured to respond to the MCU's control pins, which are also used as inputs to the PLDs. ISP via JTAG Port In-System Programming (ISP) can be performed through the JTAG signals on Port E. This serial interface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on Port E. In-System Programming (ISP) Using the JTAG signals on Port E, the entire PSD device (memory, logic, configuration) can be programmed or erased without the use of the MCU. In-Application Programming (IAP) The primary Flash memory can also be programmed, or re-programmed, in-system by the MCU executing the programming algorithms out of the secondary Flash memory, or SRAM. The secondary Flash memory can be programmed the same way by executing out of the primary Flash memory. Table 2 indicates which programming methods can program different functional blocks of the PSD. Page Register The 8-bit Page Register expands the address range of the MCU by up to 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or internal memory and I/O. The Page Register can also be used to change the address mapping of the Flash memory blocks into different memory spaces for IAP.
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PSD4000 FAMILY
Power Management Unit (PMU) The Power Management Unit (PMU) gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD Unit has a Power-down mode that helps reduce power consumption. The PSD also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The Turbo bit in PMMR0 can be reset to 0 and the CPLD latches its outputs and goes to Stand-by mode until the next transition on its inputs. Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD to reduce power consumption. See the section entitled "PSD Register Description and Address Offsets" on page 9 for more details.
Table 2. Methods of Programming Different Functional Blocks of the PSD
Functional Block Primary Flash Memory Secondary Flash memory PLD Array (DPLD and CPLD) PSD Configuration JTAG-ISP Yes Yes Yes Yes Device Programmer Yes Yes Yes Yes IAP Yes Yes No No
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PSD4000 FAMILY
DEVELOPMENT SYSTEM The PSD4000 Family is supported by PSDsoft Express, a Windows-based software development tool (Windows-95, Windows-98, Windows-2000, Windows-NT). A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD pin functions and memory map information. The general design flow is shown in Figure 3. PSDsoft Express is available from our web site: www.st.com/psd Figure 3. PSDsoft Express Development Tool
Choose MCU and PSD
Automatically configures MCU bus interface and other PSD attributes
PSDsoft Express directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/ representative, or directly from our web site using a credit card. The PSD is also supported by thid party device programmers. See our web site for the current list.
Define PSD Pin and Node Functions
Point and click definition of PSD pin functions, internal nodes, and MCU system memory map
Define General Purpose Logic in CPLD
Point and click definition of combinatorial and registered logic in CPLD. Access HDL is available if needed
C Code Generation
GENERATE C CODE SPECIFIC TO PSD FUNCTIONS
Merge MCU Firmware with PSD Configuration
A composite object file is created containing MCU firmware and PSD configuration
MCU FIRMWARE HEX OR S-RECORD FORMAT
USER'S CHOICE OF MICROCONTROLLER COMPILER/LINKER
*.OBJ FILE
PSD Programmer
PSDPro, or FlashLINK (JTAG)
*.OBJ FILE AVAILABLE FOR 3rd PARTY PROGRAMMERS (CONVENTIONAL or JTAG-ISC)
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PSD4000 FAMILY
PIN DESCRIPTION Table 3 describes the signal names and signal functions of the PSD. Those that have multiple Table 3. Pin Description (for the TQFP package)
Pin Name Type Description This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD0-AD7 to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this port. 3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the read signal is active and one of the PSD functional blocks has been selected. The addresses on this port are passed to the PLDs. Configurable MCU control signals. Active Low input. Resets I/O Ports, PLD Macrocells and some of the Configuration Registers and JTAG registers. Must be Low at Power-up. Reset also aborts any Flash memory Program or Erase cycle that is currently in progress. These pins make up Port A. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. CPLD Macrocell (McellA0-McellA7) outputs. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). These pins make up Port B. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. CPLD Macrocell (McellB0-McellB7) outputs. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). These pins make up Port C. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. External Chip Select (ECS0-ECS7) outputs. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). These pins make up Port D. This port pin can be configured to have the following functions: 1. ALE/AS input - latches address on ADIO0-ADIO15. 2. AS input - latches address on ADIO0-ADIO15 on the rising edge. 3. MCU I/O - standard output or input port. 4. Transparent PLD input (can also be PLD input for address A16 and above). 5. CLKIN - clock input to the CPLD Macrocells, the APD Unit's Power-down counter, and the CPLD AND Array. 6. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/O. When High, the PSD memory blocks are disabled to conserve power. The falling edge of this signal can be used to get the device out of Power-down mode. 7. WRH - for 16-bit data bus, write to high byte, active low. These pins make up Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. JTAG Serial Interface signals. 3. SRAM battery backup connections.
names or functions are defined using PSDsoft Express.
ADIO0ADIO15
I/O
CNTL0CNTL2 Reset
I
I
PA0-PA7
I/O CMOS or Open Drain I/O CMOS or Open Drain I/O CMOS or Slew Rate
PB0-PB7
PC0-PC7
PD0-PD3
I/O CMOS or Open Drain
PE0-PE7
I/O CMOS or Open Drain
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PSD4000 FAMILY
Pin Name Type Description These pins make up Port F. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. External Chip Select (ECS0-ECS7) outputs, or inputs to CPLD. 3. Latched address outputs. 4. Address A1-A3 inputs in 80C51XA mode (PF0 is grounded) 5. Data bus port (D0-D7) in a non-multiplexed bus configuration. 6. Peripheral I/O mode. 7. MCU reset mode. These pins make up Port G. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address outputs. 3. Data bus port (D8-D15) in a non-multiplexed bus configuration. 4. MCU reset mode. Supply Voltage Ground pins
PF0-PF7
I/O CMOS or Open Drain
PG0-PG7
I/O CMOS or Open Drain
VCC GND
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PSD REGISTER DESCRIPTION AND ADDRESS OFFSETS Table 4 shows the offset addresses to the PSD Table 4 provides brief descriptions of the registers registers relative to the CSIOP base address. The in CSIOP space. The following sections give a CSIOP space is the 256 bytes of address that is almore detailed description. located by the user to the internal PSD registers. Table 4. PSD4256G6 Register Address Offset
Register Name Data In Control Data Out Direction Drive Select Input Macrocell Enable Out Output Macrocells A Output Macrocells B Mask Macrocells A Mask Macrocells B Flash Memory Protection 1 Flash Memory Protection 2 Flash Boot Protection JTAG Enable PMMR0 PMMR2 Page VM Memory_ID0 Memory_ID1
Note: 1. Other registers that are not part of the I/O ports.
Port Port Port Port Port Port Port Other1 A B C D E F G 00 01 10 11 30 32 04 06 08 0A 0C 20 21 22 23 C0 C1 C2 C7 B0 B4 E0 E2 F0 F1 05 07 09 0B 0D 1C 14 16 18 15 17 19 1A 4C 34 36 38 40 42 44 46 48 41 43 45 47 49
Description Reads Port pin as input, MCU I/O input mode Selects mode between MCU I/O or Address Out Stores data for output to Port pins, MCU I/O output mode Configures Port pin as input or output Configures Port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins. Reads Input Macrocells Reads the status of the output enable to the I/O Port driver Read - reads output of Macrocells A Write - loads Macrocell Flip-flops Read - reads output of Macrocells B Write - loads Macrocell Flip-flops Blocks writing to the Output Macrocells A Blocks writing to the Output Macrocells B Read only - Primary Flash Sector Protection Read only - Primary Flash Sector Protection Read only - PSD Security and Secondary Flash memory Sector Protection Enables JTAG Port Power Management Register 0 Power Management Register 2 Page Register Places PSD memory areas in Program and/ or Data space on an individual basis. Read only - SRAM and Primary memory size Read only - Secondary memory type and size
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Figure 4. An Example of a Typical 16-bit Multiplexed Bus Interface
MCU
AD [ 7:0]
PSD
PORT F A [ 7: 0] (OPTIONAL)
AD[ 15:8]
ADIO PORT
PORT G WR RD BHE WR (CNTRL0) RD (CNTRL1) BHE (CNTRL2) RST ALE ALE (PD0) PORT D RESET PORT A, B or C
A [ 15: 8] (OPTIONAL)
A [ 23:16] (OPTIONAL)
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Figure 5. An Example of a Typical 16-bit Non-Multiplexed Bus Interface
MCU
D [ 15:0]
PSD
PORT F D [ 7:0]
ADIO PORT A [ 15:0]
PORT G WR RD BHE WR (CNTRL0) RD (CNTRL1) BHE (CNTRL2) RST PORT A, B or C
D[ 15:8]
A [ 23:16] (OPTIONAL)
ALE
ALE (PD0) PORT D
RESET
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PSD4000 FAMILY
POWER MANAGEMENT The PSD device offers configurable power saving options. These options may be used individually or in combinations, as follows: s All memory blocks in a PSD (primary Flash memory, secondary Flash memory, and SRAM) are built with power management technology. In addition to using special silicon design methodology, power management technology puts the memories into standby mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory "wakes up", changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve memory Stand-by mode when no inputs are changing--it happens automatically. The PLD sections can also achieve Stand-by mode when its inputs are not changing, as described for the Power Management Mode Registers (PMMR), later. The Automatic Power Down (APD) block allows the PSD to reduce to stand-by current automatically. The APD Unit also blocks MCU address/data signals from reaching the memories and PLDs. This feature is available on all PSD devices. The APD Unit is described in more detail in the full data sheet. Built in logic monitors the Address Strobe of the MCU for activity. If there is no activity for a certain period (the MCU is asleep), the APD Unit initiates Power-down mode (if enabled). Once in Power-down mode, all address/data signals are blocked from reaching the PSD memories and PLDs, and the memories are deselected internally. This allows the memories and PLDs to remain in Stand-by mode even if the address/data signals are changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind that any unblocked PLD input signals that
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are changing states keeps the PLD out of Stand-by mode, but not the memories. PSD Chip Select Input (CSI, PD2) can be used to disable the internal memories, placing them in Stand-by mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD Unit, especially if your MCU has a chip select output. There is a slight penalty in memory access time when PSD Chip Select Input (CSI, PD2) makes its initial transition from deselected to selected. The Power Management Mode Registers (PMMR) can be written by the MCU at run-time to manage power. All PSD devices support "blocking bits" in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs. Significant power savings can be achieved by blocking signals that are not used in DPLD or CPLD logic equations at run-time. PSDsoft Express creates a fuse map that automatically blocks the low address byte (A7-A0) or the control signals (CNTL0-CNTL2, ALE and Write Enable High-byte (WRH/DBE, PD3)) if none of these signals are used in PLD logic equations. PSD devices have a Turbo bit in PMMR0. This bit can be set to turn the Turbo mode off (the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can achieve Stand-by current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo mode is on. When the Turbo mode is on, there is a significant DC current component, and the AC component is higher.
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s
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PACKAGE MECHANICAL TQFP80 - 80 lead Plastic Quad Flatpack
D D1 D2 A2
e Ne E2 E1 E b
N 1
Nd L1
A CP
c
QFP-A
A1
L
Note: Drawing is not to scale.
TQFP80 - 80 lead Plastic Quad Flatpack
Symb. A A1 A2 b c D D1 D2 E E1 E2 e L L1 CP N Nd Ne 14.000 12.000 9.500 14.000 12.000 9.500 0.500 0.600 1.000 0.080 80 20 20 -- -- 0.450 -- -- 0.750 -- -- 3.5 0.220 0.050 0.950 0.0 0.170 0.090 mm Typ. Min. Max. 1.200 0.150 1.050 7.0 0.270 0.200 0.5512 0.4724 0.3740 0.5512 0.4724 0.3740 0.0197 0.0236 0.0394 0.0031 80 20 20 -- -- 0.0177 -- -- 0.0295 -- -- 3.5 0.0087 0.0020 0.0374 0.0 0.0067 0.0035 Typ. inches Min. Max. 0.0472 0.0059 0.0413 7.0 0.0106 0.0079
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Table 5. Pin Assignments - TQFP80
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Assign ments PD2 PD3 AD0 AD1 AD2 AD3 AD4 GND VCC AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Assign ments PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 VCC GND PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 RESET CNTL2 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin Assign ments PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND GND PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 CNTL0 CNTL1 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Assign ments PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VCC GND PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PD0 PD1
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Figure 6. TQFP Connections
70 GND
69 VCC 68 PB7
80 PD1
79 PD0
67 PB6
66 PB5
65 PB4
64 PB3
63 PB2
62 PB1
PD2 1 PD3 2 AD0 3 AD1 4 AD2 5 AD3 6 AD4 7 GND 8 VCC 9 AD5 10 AD6 11 AD7 12 AD8 13 AD9 14 AD10 15 AD11 16 AD12 17 AD13 18 AD14 19 AD15 20
61 PB0
78 PE7
77 PE6
76 PE5
75 PE4
74 PE3
73 PE2
72 PE1
71 PE0
60 CNTL1 59 CNTL0 58 PA7 57 PA6 56 PA5 55 PA4 54 PA3 53 PA2 52 PA1 51 PA0 50 GND 49 GND 48 PC7 47 PC6 46 PC5 45 PC4 44 PC3 43 PC2 42 PC1 41 PC0
PG0 21
PG1 22
PG2 23
PG3 24
PG4 25
PG5 26
PG6 27
PG7 28
VCC 29
GND 30
PF0 31
PF1 32
PF2 33
PF3 34
PF4 35
PF5 36
PF6 37
PF7 38
RESET 39
CNTL2 40
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PART NUMBERING Table 6. Ordering Information Scheme
Example: PSD42 5 6G 6 V - 90 U I T
Device Type PSD42 = Flash PSD for 16-bit MCUs (with Complex PLD) PSD41 = Flash PSD for 16-bit MCUs (with Simple PLD) SRAM Size 0 = none 1 = 16 Kbit 2 = 32 Kbit Flash Memory Size 1 = 256 Kbit 2 = 512 Kbit 3 = 1 Mbit I/O Count F = 27 I/O G = 52 I/O 2nd Non Volatile Memory 1 = 256 Kbit EEPROM 3 = none Operating Voltage blank = VCC = 4.5 to 5.5V V = VCC = 3.0 to 3.6V Speed 70 = 70 ns 90 = 90 ns
3 = 64 Kbit 4 = 128 Kbit 5 = 256 Kbit
4 = 2 Mbit 5 = 4 Mbit 6 = 8 Mbit
2 = 256 Kbit Flash memory 6 = 512 Kbit Flash memory
12 = 120 ns 15 = 150 ns 20 = 200 ns
Package U = TQFP Temperature Range blank = 0 to 70 C (commercial) I = -40 to 85 C (industrial) Option T = Tape & Reel Packing
For a list of available options (speed, package, etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Office.
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PSD4000 FAMILY
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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