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| IDT74FCT841AT/CT FAST CMOS BUS INTERFACE LATCH INDUSTRIAL TEMPERATURE RANGE FAST CMOS BUS INTERFACE LATCH IDT74FCT841AT/CT FEATURES: * * * * * * * * A and C grades Low input and output leakage 1A (max.) CMOS power levels True TTL input and output compatibility: - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Power off disable outputs permit "live insertion" Available in SOIC, SSOP, and QSOP packages DESCRIPTION: The FCT841T series is built using an advanced dual metal CMOS technology. The FCT841T bus interface latches are designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The FCT841T are buffered, 10-bit wide versions of the popular FCT373T function. They are ideal for use as an output port requiring high IOL/IOH. All of the FCT841T high-performance interface family can drive large capacitive loads, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes to ground and all outputs are designed for low-capacitance bus loading in high-impedance state. FUNCTIONAL BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 D8 D9 D LE Q D LE Q D LE Q D LE Q D LE Q D LE Q D LE Q D LE Q LE OE Y0 Y1 Y2 Y3 Y4 Y5 Y8 Y9 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 1 JUNE 2002 DSC-2571/9 (c) 2002 Integrated Device Technology, Inc. IDT74FCT841AT/CT FAST CMOS BUS INTERFACE LATCH INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 LE ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM(2) VTERM(3) TSTG IOUT Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max -0.5 to +7 -0.5 to VCC+0.5 -65 to +150 -60 to +120 Unit V V C mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only. CAPACITANCE (TA = +25C, F = 1.0MHz) Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF NOTE: 1. This parameter is measured at characterization but not tested. SOIC/ SSOP/ QSOP TOP VIEW PIN DESCRIPTION Pin Names Dx LE I/O I I Description Latch Data Inputs Latch Enable Input. The latches are transparent when LE is HIGH. Input data is latched on the HIGH-toLOW transition. 3-State Latch Outputs Output Enable Control. When OE is LOW, the outputs are enabled. When OE is HIGH, the outputs Yx are in high-impedance (off) state. FUNCTION TABLE(1) OE H H H L L L Inputs LE H H L H H L Dx L H X L H X Internal Qx L H NC L H NC Output Yx Z Z Z L H NC Function High Z High Z Latched (High Z) Transparent Transparent Latched Yx OE O I NOTE: 1. H = HIGH Voltage Level X = Don't Care L = LOW Voltage Level Z = High Impedance NC = No Change 2 IDT74FCT841AT/CT FAST CMOS BUS INTERFACE LATCH INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 5% Symbol VIH VIL IIH IIL IOZH IOZL II VIK VH ICC Input HIGH Current(4) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = Max. VIN = GND or VCC VCC = Max., VI = VCC (Max.) VCC = Min., IIN = -18mA -- Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current(4) High Impedance Output Current(4) Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max., VI = VCC (Max.) VI = 2.7V VI = 0.5V VI = 2.7V VI = 0.5V Min. 2 -- -- -- -- -- -- -- -- -- Typ.(2) -- -- -- -- -- -- -- -0.7 200 0.01 Max. -- 0.8 1 1 1 1 1 -1.2 -- 1 A V mV mA Unit V V A A A OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL IOS IOFF Parameter Output HIGH Voltage Output LOW Voltage Short Circuit Current Input/Output Power Off Leakage(5) VCC = Min VIN = VIH or VIL VCC = Min VIN = VIH or VIL VCC = Max., VO = GND(3) Test Conditions(1) IOH = -8mA IOH = -15mA IOL = 48mA Min. 2.4 2 -- -60 -- Typ.(2) 3.3 3 0.3 -120 -- Max. -- -- 0.5 -225 1 Unit V V mA A VCC = 0V, VIN or VO 4.5V NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is 5A at TA = -55C. 5. This parameter is guaranteed but not tested. 3 IDT74FCT841AT/CT FAST CMOS BUS INTERFACE LATCH INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OE = GND LE = VCC One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle OE = GND LE = VCC One Bit Toggling VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle OE = GND LE = VCC Eight Bits Toggling VIN = VCC VIN = GND Test Conditions(1) Min. -- -- Typ.(2) 0.5 0.15 Max. 2 0.25 Unit mA mA/ MHz IC Total Power Supply Current(6) VIN = VCC VIN = GND VIN = 3.4V VIN = GND -- 1.5 3.5 mA -- 1.8 4.5 VIN = VCC VIN = GND VIN = 3.4V VIN = GND -- 3 6(5) mA -- 5 14(5) NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz. 4 IDT74FCT841AT/CT FAST CMOS BUS INTERFACE LATCH INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol tPLH tPHL Parameter Propagation Delay Dx to Yx (LE = HIGH) Condition(1) CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 5pF(4) RL = 500 CL = 50pF RL = 500 CL = 50pF RL = 500 74FCT841AT Min.(2) Max. 1.5 9 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.5 4 13 12 16 11.5 23 7 18 -- -- -- 74FCT841CT Min.(2) Max. 1.5 5.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.5 4 13 6.4 15 6.5 12 5.7 6 -- -- -- ns ns ns ns ns ns Unit ns tPLH tPHL Propagation Delay LE to Yx tPZH tPZL Output Enable Time, OE to Yx tPHZ tPLZ Output Disable Time, OE to Yx tSU tH tW Data to LE Set-up Time Data to LE Hold Time LE Pulse Width HIGH(3) NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. These parameters are guaranteed but not tested. 4. This condition is guaranteed but not tested. 5 IDT74FCT841AT/CT FAST CMOS BUS INTERFACE LATCH INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS V CC 500 VIN Pulse Generator RT D.U.T . VOUT 7.0V SWITCH POSITION Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open 50pF CL 500 DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Octal link Test Circuits for All Outputs DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU tH tREM 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V Octal link LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE Octal link 1.5V 1.5V tSU tH Pulse Width Set-Up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V Octal link DISABLE 3V 1.5V CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPHZ 0.3V 1.5V 0V tPLZ 0V 3.5V 0.3V VOL VOH 0V Octal link Propagation Delay Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 6 IDT74FCT841AT/CT FAST CMOS BUS INTERFACE LATCH INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION FCT IDT XX XXXX Temp. Range Device Type X Package SO PY Q Small Outline IC Shrink Small Outline Package Quarter-size Small Outline Package 841AT 10-Bit Non-Inverting Latch 841CT 74 - 40C to +85C DATA SHEET DOCUMENT HISTORY 6/25/2002 Updated as per PDNs Logic-00-07 and Logic-01-04 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 7 for Tech Support: logichelp@idt.com (408) 654-6459 |
Price & Availability of 74FCT841TDS49068
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