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IDT74ALVCH16543 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * VCC = 2.5V 0.2V * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * Available in SSOP, TSSOP, and TVSOP packages
IDT74ALVCH16543
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
* High Output Drivers: 24mA * Suitable for heavy loads
APPLICATIONS:
* 3.3V high speed systems * 3.3V and lower voltage computing systems
This 16-bit registered transceiver is built using advanced dual metal CMOS technology. The ALVCH16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using CEBA, LEBA, and OEBA. The ALVCH16543 has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH16543 has "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 1A1
56 54 55
2OEBA 2CEBA 2LEBA
29 31 30 28 26 27 15 C1 1D 42
1 3 2
2OEAB 2CEAB 2LEAB
5
C1 1D 52
2A1 1B1
2B1
C1 1D
C1 1D
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 1999 Integrated Device Technology, Inc.
JULY 1999
DSC-4490/2
IDT74ALVCH16543 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1OEAB 1LEAB 1CEAB
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM(2) Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND -0.5 to +4.6 -0.5 to VCC+0.5 -65 to +150 -50 to +50 50 -50 100
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OEBA 1LEBA 1CEBA
Unit V V C mA mA mA mA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VTERM(3) TSTG IOUT IIK IOK ICC ISS
GND
1A1 1A2
GND
1B1 1B2
VCC
1A3 1A4 1A5
VCC
1B3 1B4 1B5
GND
1A6 1A7 1A8 2A1 2A2 2A3
GND
1B6 1B7 1B8 2B1 2B2 2B3
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
GND
2A4 2A5 2A6
GND
2B4 2B5 2B6
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
VCC
2A7 2A8
VCC
2B7 2B8
NOTE: 1. As applicable to the device type.
GND
2CE AB 2LEAB 2OEAB
GND
2CEBA 2LEBA 2OEBA
FUNCTION TABLE(1,2)
Inputs Output xOEAB X H L L L xAx X X X L H xBx Z Z B(3) L H xCEAB X X L L L xLEAB X X H L L
SSOP/ TSSOP/ TVSOP TOP VIEW
PIN DESCRIPTION
Pin Names xOEAB xOEBA xCEAB xCEBA xLEAB xLEBA xAx xBx Description A-to-B Output Enable Inputs (Active LOW) B-to-A Output Enable Inputs (Active LOW) A-to-B Enable Inputs (Active LOW) B-to-A Enable Inputs (Active LOW) A-to-B Latch Enable Inputs (Active LOW) B-to-A Latch Enable Inputs (Active LOW) A-to-B Data Inputs or B-to-A 3-State Outputs(1) B-to-A Data Inputs or A-to-B 3-State Outputs(1)
NOTES: 1. A-to-B data flow is shown. B-to-A data flow is similar but uses xCEBA, xLEBA, and xOEBA. 2. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance 3. Level of B before the indicated steady-state inputs were established.
NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
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IDT74ALVCH16543 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- -0.7 100 0.1 Max. -- -- 0.7 0.8 5 5 10 10 -1.2 -- 40 V mV A A A A V Unit V
Quiescent Power Supply Current Variation
--
--
750
A
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. - 75 75 - 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- 500
Unit A A A
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IDT74ALVCH16543 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, TA = 25C
VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 54 6 VCC = 3.3V 0.3V Typical 64 7 Unit pF
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IDT74ALVCH16543 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V 0.2V Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tSU tSU tH tH tW tSK(o) Parameter Propagation Delay xAx to xBx or xBx to xAx Propagation Delay xLEAB to xBx or xLEAB to xAx Output Enable Time xCEAB to xBx or xCEAB to xAx Output Disable Time xCEAB to xBx or xCEAB to xAx Output Enable Time xOEAB to xBx or xOEAB to xAx Output Disable Time xOEAB to xBx or xOEAB to xAx Set-up Time, data before CE Set-up Time, data before LE, CE LOW Hold Time, Ax data after CE Hold Time, Bx data after LE, CE LOW Pulse Duration, LE or CE LOW Output Skew(2) 1.2 1.2 1.2 1.2 3.3 -- -- -- -- -- -- -- 1.5 1.5 0.8 0.8 3.3 -- -- -- -- -- -- -- 1.2 1.2 1.3 1.3 3.3 -- -- -- -- -- -- 500 ns ns ns ns ns ps 1 5.7 -- 4.8 1.1 4.6 ns 1 6.8 -- 6.3 1 5.3 ns 1.3 6.1 -- 6.2 1.5 5.1 ns 1 7.2 -- 6.9 1 5.6 ns 1 6.5 -- 6.2 1.1 5 ns Min. 1 Max. 5.1 VCC = 2.7V Min. -- Max. 4.8 VCC = 3.3V 0.3V Min. 1 Max. 4.3 Unit ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2 Skew between any two outputs of the same package and switching in the same direction.
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IDT74ALVCH16543 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50 6 2.7 1.5 300 300 50 VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
ALVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
ALVC Link
VCC 500 Pulse Generator
(1, 2)
VLOAD Open GND
VIN D.U.T. RT
VOUT
500 CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALVC Link
INPUT
tPLH1
tPHL1
VIH VT 0V VOH VT VOL VOH VT VOL
Set-up, Hold, and Release Times
OUTPUT 1
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
VT
tSK (x)
tSK (x)
OUTPUT 2 tPLH2 tPHL2
VT
ALVC Link
Pulse Width
ALVC Link
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74ALVCH16543 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX ALVC X Bus-Hold Temp. Range XX Family XX XXX Device Type Package
PV PA PF 543 16 H 74
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package 16-Bit Registered Transceiver with 3-State Outputs Double-Density, 24mA Bus-Hold -40C to +85C
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for Tech Support: logichelp@idt.com (408) 654-6459
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