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PRELIMINARY
GALVANTECH, INC. ASYNCHRONOUS ULTRA LOW POWER FULL CMOS SRAM
FEATURE
* * * Low standby current: 5ua (max.) Low operating current: 1.5mA/MHz (typ.) Wide power supply voltage range: 3.0V to 3.6V for GVT73024UL8XX family 2.7V to 3.3V for GVT73024UL8XXB family 2.3V to 2.7V for GVT73024UL8XXC family 1.8V to 2.2V for GVT73024UL8XXD family Low data retention voltage: 1.5V (Min) Full CMOS 6-transistor memory cell Fully static -- no clock or timing strobes necessary All inputs and outputs are TTL-compatible Three state outputs Easy memory expansion with CE1#, CE2 and OE# options Automactic power-down when deselected
GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM
128K x 8 SRAM
LOW POWER SUPPLY VOLTAGE LOW STANDBY CURRENT
GENERAL DESCRIPTION
The GVT73024UL8 is organized as a 131,072 x 8 SRAM using a six-transistor full CMOS memory cell along with lowpower CMOS process, using double-layer polysilicon, double-layer metal technology. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers two chip enables (CE1# and CE2) along with output enable (OE#) for this organization. The chip is enabled when CE1# is LOW and CE2 is HIGH. With chip being enabled, writing to this device is accomplished when write enable (WE#) is LOW and reading is accomplished when (OE#) go LOW with (WE#) remaining HIGH. The device offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements.
PIN ASSIGNMENT 32-Pin SOJ 32-Pin DIP
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
* * * * * * * *
OPTIONS
Power supply voltage 3.3V + 0.3V 3.0V + 0.3V 2.5V + 0.2V 2.0V + 0.2V Timing 55ns access 70ns access 85ns access 100ns access 300ns access Packages 32-pin SOJ (300 mil) 32-pin TSOP (type I) 32-pin sTSOP (type I) Temperature Commercial Industrial
MARKING
-None -B -C -D
*
-55 -70 -85 -100 -300
*
SJ TS ST
A11 A9 A8 A13 WE# CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VCC A15 CE2 WE# A13 A8 A9 A11 OE# A10 CE1# DQ8 DQ7 DQ6 DQ5 DQ4
PIN ASSIGNMENT 32-Pin TSOP (Type (TYPE I) 32-PIN TSOP/sTSOPI)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
*
None I
(0C to 70C) (-40C to 85C)
OE# A10 CE1# DQ8 DQ7 DQ6 DQ5 DQ4 VSS DQ3 DQ2 DQ1 A0 A1 A2 A3
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699 Web Site http://www.galvantech.com
Rev. 5/98
Galvantech, Inc. reserves the right to change products or specifications without notice.
PRELIMINARY
GALVANTECH, INC.
FUNCTIONAL BLOCK DIAGRAM
GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM
VCC VSS A0 DQ1
ROW DECODER
ADDRESS BUFFER
MEMORY ARRAY 512 ROWS X 256 X 8 COLUMNS
I/O CONTROL
DQ8
CE2 CE1# WE#
OE#
A16
COLUMN DECODER
TRUTH TABLE
MODE READ WRITE OUTPUT DISABLE STANDBY STANDBY CE1# L L L H X CE2 H H H X L WE# H L H X X OE# L X H X X DQ Q D HIGH-Z HIGH-Z HIGH-Z POWER ACTIVE ACTIVE ACTIVE STANDBY STANDBY
POWER DOWN
PIN DESCRIPTIONS
SOJ Pin Numbers TSOP & sTSOP Pin Numbers SYMBOL
A0-A16
TYPE
Input
DESCRIPTION
Address Inputs: These inputs determine which cell is addressed.
12, 11, 10, 9, 8, 7, 20, 19, 18, 17, 16, 6, 5, 27, 28, 23, 15, 14, 13, 3, 2, 31, 25, 4, 28, 3, 31, 2 1, 12, 4, 11, 7, 10 29 22, 30 5 30, 6
WE# CE1#, CE2
Input
Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW for a WRITE cycle and HIGH for a READ cycle. Chip Enables: These inputs are used to enable the device. When CE1# is LOW and CE2 is HIGH, the chip is selected. When either CE1# is HIGH or CE2 is LOW, the chip is disabled and automatically goes into standby power mode. Output Enable: This active LOW input enables the output drivers. SRAM Data I/O: Data inputs and data outputs.
Input
24 13, 14, 15, 17, 18, 19, 20, 21 32 16
32 21, 22, 23, 25, 26, 27, 28, 29 8 24
OE# DQ1-DQ8 VCC VSS
Input Input/ Output
Supply Power Supply: 1.8V to 3.6V, depending upon the product family. Supply Ground
May 28, 1998
2
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
PRELIMINARY
GALVANTECH, INC.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS........-0.3V to +4.0V VIN ..........................................................-0.5V to VCC+0.5V Storage Temperature (plastic) ......................-65oC to +150oC Power Dissipation ...........................................................0.7W Soldering Temperature (10s) ........................................260oC
GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
DESCRIPTION
Supply Voltage
SYMBOL PRODUCT
VCC GVT73024UL8XX GVT73024UL8XXB GVT73024UL8XXC GVT73024UL8XXD
MIN
3.0 2.7 2.3 1.8 2.2 2.2 2.0 1.6 -0.2
TYP
3.3 3.0 2.5 2.0 -
MAX
3.6 3.3 2.7 2.2 VCC+0.2
UNITS
V
NOTES
1
Input High (Logic 1) voltage
VIH
GVT73024UL8XX GVT73024UL8XXB GVT73024UL8XXC GVT73024UL8XXD
V
1, 2
Input Low (Logic 0) Voltage
VIl
0.4
V
1, 2
DC AND OPERATING ELECTRICAL CHARACTERISTICS
(All Temperature Ranges; VCC = 1.8 V to 3.6V. unless otherwise noted, VLC=0.2V, VHC=VCC-0.2V)
DESCRIPTION
Input Leakage Current Output Leakage Current Operating Power Supply Current
SYM CONDITIONS
ILI ILO Icc1 Icc2 0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC Cycle Time=1us; CE1# = VIL & CE2 = VIH;Other Inputs = VIH/VIL; IOUT = 0mA Cycle Time=Min; CE1# = VIL & CE2 = VIH;Other Inputs = VIH /VIL; IOUT = 0mA VCC=3.6V@55ns VCC=3.3V@70ns VCC=2.7V@85ns VCC=2.2V@300ns
MIN.
-1 -1 -
TYP. MAX. UNITS
1 1 1.5 3 55 50 30 15 0.3 5 0.4 mA uA V uA uA mA mA
NOTES
3, 14 3
TTL Standby Current CMOS Standby Current Output Low Voltage
ISB ISB1 VOL
CE1# > VIH or CE2 < VIL; Other Inputs=VIH or VIL; f= 0 CE1# > VHC or CE2< VLC; Other Inputs=VHC or VLC; f= 0 IOL = 2.1mA @ VCC=2.7V IOL = 0.5mA @ VCC=2.3V IOL = 0.33mA @ VCC=1.8V IOH = -1.0mA @ VCC=3.0V IOH = -0.5mA @ VCC=2.5V IOH = -0.44mA @ VCC=2.0V
1
Output High Voltage
VOH
2.4 2.0 1.6
-
-
V
1
CAPACITANCE
DESCRIPTION
Input Capacitance Input/Output Capacitance (DQ)
CONDITIONS
TA = 25oC; f = 1 MHz VCC = 3V
SYMBOL
CI CI/O
MAX
6 8
UNITS
pF pF
NOTES
4 4
May 28, 1998
3
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
PRELIMINARY
GALVANTECH, INC.
PRODUCT LIST Part Name
GVT73024UL8XX GVT73024UL8XXB GVT73024UL8XXC GVT73024UL8XXD
GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM
Voltage Range & Speed Grade
3.3V + 0.3V; 55ns, 70ns and 85ns 3.0V + 0.3V; 55ns, 70ns and 85ns 2.5V + 0.2V; 70ns, 85ns and 100ns 2.0V + 0.2V; 300ns
AC ELECTRICAL CHARACTERISTICS (Note 5)
(All Temperature Ranges; VCC = 3.0V to 3.6V for GVT73024ULXX family; VCC = 2.7V to 3.3V for GVT73024ULXXB family; VCC = 2.3V to 2.7V for GVT73024ULXXC family; VCC = 1.8V to 2.2V for GVT73024ULXX family))
DESCRIPTION
READ Cycle READ cycle time Address access time Chip Enable access time Output hold from address change Chip Enable to output in Low-Z Chip disable to output in High-Z Output Enable access time Output Enable to output in Low-Z Output Enable to output in High-Z Chip Enable to power-up time Chip disable to power-down time WRITE Cycle WRITE cycle time Chip Enable to end of write Address valid to end of write, with OE# HIGH Address setup time Address hold from end of write WRITE pulse width WRITE pulse width, with OE# HIGH Data setup time Data hold time Write disable to output in Low-Z Write Enable to output in High-Z
tWC tCW tAW t t tRC tAA tACE tOH tLZCE tHZCE tAOE tLZOE tHZOE tPU tPD
- 55
SYM MIN MAX
- 70
MIN MAX
- 85
MIN MAX
- 100
MIN MAX
- 300
MIN MAX UNITS NOTES
55 55 55 10 10 20 20 5 20 0 55 55 40 40 0 0 40 40 25 0 5 20
70 70 70 10 10 25 30 5 25 0 70 70 45 45 0 0 45 45 30 0 5 25
85 85 85 15 10 25 40 5 25 0 85 85 50 50 0 0 50 50 35 0 5 25
100 100 100 15 10 25 50 5 25 0 100 100 60 60 0 0 60 60 40 0 5 25
300 300 300 30 50 60 150 30 60 0 300 300 300 300 0 0 200 200 120 0 20 60
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4, 7 4, 6, 7 4, 7 4, 6, 7 13 4, 7 4, 6, 7 4 4 13 13
AS
AH
tWP2 tWP1 tDS tDH tLZWE tHZWE
May 28, 1998
4
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
PRELIMINARY
GALVANTECH, INC.
AC TEST CONDITIONS Input pulse levels 0.4V to 2.4V for VCC=3.3V &3.0V; 0.4V to 2.2V for VCC=2.5V; 0.4V to 1.8V for VCC=2.0V 5ns 1.5V for VCC=3.3V and 3.0V; 1.1V for VCC=2.5V; 0.9V for VCC=2.0V CL = 100pF and 1 TTL Gate
GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM
Input rise and fall times Input and output reference levels Output load
NOTES
1. 2. 3. 4. 5. 6. All voltages referenced to VSS (GND). Undershoot:VIL -1.0V for t 20ns Overshoot:VIH > VCC+1.0V for t 20ns Icc is given with no output current. Icc increases with greater output loading and faster cycle times. This parameter is sampled. Test conditions as specified with the output loading as shown in the table of AC Test Conditions unless otherwise noted. High-Z is defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
7. 8. 9.
At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE. WE# is HIGH for READ cycle. Device is continuously selected. Chip enable and output enables are held in their active state.
10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip Enable and Write Enable can initiate and terminate a WRITE cycle. 13. Capacitance derating applies to capacitance different from the load capacitance shown in AC Test Condition table. 14. Typical values are measured at 3.3V and 25oC.
DATA RETENTION ELECTRICAL CHARACTERISTICS
DESCRIPTION
Vcc for Retention Data Data Retention Current CE1# >VCC -0.2 or CE2< VSS +0.2; all other inputs < VSS +0.2 or >VCC -0.2; all inputs static; f= 0;Vcc = 3.0V
CONDITIONS
SYMBOL
MIN
1.5 -
TYP
-
MAX
3.6 5
UNITS
V uA
NOTES
1
VDR ICCDR tCDR tR
Chip Deselect to Data Retention Time Operation Recovery Time
0
-
-
ns ns
4 4, 11
tRC
May 28, 1998
5
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
PRELIMINARY
GALVANTECH, INC.
GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
VDR tRC
VCC
VIH VIL
t
CDR
CE#
READ CYCLE NO. 1(8, 9)
t RC
ADDR
t AA t OH
VALID
Q
PREVIOUS DATA VALID
READ CYCLE NO. 2(7, 8, 10, 12)
tRC
DATA VALID
CE1#
CE2
tAOE tLZOE
OE#
tACE tLZCE
tHZCE
tHZOE
Q
HIGH Z
DATA VALID DON'T CARE UNDEFINED
May 28, 1998
6
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
PRELIMINARY
GALVANTECH, INC.
GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM
WRITE CYCLE NO. 1(7, 12) (Write Enable Controlled with Output Enable OE# active LOW))
t
WC
ADDR
t
AW
t
t
AH
CW
CE2
CE1#
t
AS
t WP2
WE#
t
DS
t
DH
D
t
DATA VALID
HZWE
t
LZWE
Q
HIGH Z
WRITE CYCLE NO. 2(12) (Write Enable Controlled with Output Enable OE# inactive HIGH)
t WC
ADDR
tAW t t AH
CW
CE2
CE1#
tAS tWP1
WE#
tDS tDH
D Q
DATA VALID HIGH Z DON'T CARE UNDEFINED
May 28, 1998
7
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
PRELIMINARY
GALVANTECH, INC.
GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM
WRITE CYCLE NO. 3(12) (Chip Enable Controlled)
t
WC
ADDR
t t
AW
tCW
t
AH
AS
CE2
CE1#
t
WP1
WE#
t
DS
t
DH
D
DATA VALID HIGH Z
Q
DON'T CARE
May 28, 1998
8
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
PRELIMINARY
GALVANTECH, INC.
Package Dimensions
GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM
32-pin 300 Mil Plastic SOJ (SJ)
.825 (20.96) .810 (20.57)
.305 (7.75) .292 (7.42)
.340 (8.64) .330 (8.38)
PIN #1 INDEX
.050 (1.27) TYP
.140 (3.55) .120 (3.04)
SEATING PLANE .020 (0.51) .015 (0.38)
.095 (2.41) .080 (2.03) .274 (6.95) .254 (6.44) .025 (0.63) MIN
Note: All dimensions in inches (millimeters)
MAX MIN
or typical, min where noted.
32-pin Plastic TSOP (TS)
.795 (20.20) .780 (19.80) .012 (0.30) .006 (0.15)
.020 (0.50) TYP
.319 (8.10) .311 (7.90)
.047 (1.20) MAX
.728 (18.50) .720 (18.30)
.041 (1.05) .037 (0.95)
Note: All dimensions in inches (millimeters)
MAX MIN
or typical, max where noted.
May 28, 1998
9
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
PRELIMINARY
GALVANTECH, INC.
Package Dimensions (continued)
GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM
32-pin Plastic STSOP (ST)
.536 (13.60) .520 (13.20) .012 (0.30) .006 (0.15)
.020 (0.50) TYP
.319 (8.10) .311 (7.90)
.047 (1.20) MAX
.469 (11.90) .461 (11.70)
.041 (1.05) .037 (0.95)
Note: All dimensions in inches (millimeters)
MAX MIN
or typical, max where noted.
Ordering Information GVT 73024UL8 XX X - XXX X
Galvantech Prefix Part Number Temperature (Blank = Commercial I = Industrial) , Speed (55 = 55ns, 70= 70ns, 85 = 85ns, 100 = 100ns, 300 = 300ns) Voltage (Blank = 3.0V to 3.6V, B = 2.7V to 3.3V, C = 2.3V to 2.7V, D = 1.8V to 2.2V) Package (SJ = 300 mil SOJ, TS= TSOP TYPE I, ST= sTSOP TYPE I)
May 28, 1998
10
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98

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